Paper Citation Record · LEDGER

Hardware/Software Co-Design of RISC-V Extensions for Accelerating Sparse DNNs on FPGAs

As of 22 August 2026, this Paper Citation Record lists 28 of 28 outbound references and 0 inbound Pith citation observations for arXiv:2504.19659.

A citation records a reference. It does not transfer a finding from one paper to another.

pith.paper-citation-record.v1
2504.19659 v1

Coverage vector

measured 28 of 28 reference resolution

Typed states for the displayed outbound observations.

Source: paper_references, paper_reference_links, observed 2026-08-16T05:52:37.826320Z

measured 28 of 28 standing notices

One-hop event checks from named stored sources.

Source: scholarly_work_events, retraction_status_cache, observed 2026-08-22T06:32:14.747728+00:00

measured 0 of 0 inbound itemization

Pith citing papers itemized under the disclosed page cap.

Source: paper_references, paper_reference_links

measured 0 of 1 external citation measurements

A source-named dated measurement, never combined with another source.

Source: cited_works

Reference resolution

28 of 28 outbound references displayed

verified exact5
verified fuzzy7
unresolved13
parse uncertain0
malformed identifier2
metadata mismatch1

External citation measurements

No source-named external measurement is stored.

Outbound references

Observation 4e25531e-4459-49d0-bc26-300266d37dee · outbound

This paper cites The Internet of Things (IoT): Applications, In- vestments, and Challenges for Enterprises.

Hardware/Software Co-Design of RISC-V Extensions for Accelerating Sparse DNNs on FPGAs The Internet of Things (IoT): Applications, In- vestments, and Challenges for Enterprises

Reference 1

Resolution: verified exact; doi, observed 2026-08-16T05:52:37.957651Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-22T06:32:14.747728+00:00.

Observation 1dd81cab-6743-49b5-a159-2a1b2776f00a · outbound

This paper cites Edge AI: A Survey.

Hardware/Software Co-Design of RISC-V Extensions for Accelerating Sparse DNNs on FPGAs Edge AI: A Survey

Reference 2

Resolution: unresolved; no resolver link, observed 2026-08-16T05:52:37.679703Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 82fc5834-c674-4e71-b9ad-2e45947484ab · outbound

This paper cites TinyML: Tools, Applications, Challenges, and Future Research Directions.

Hardware/Software Co-Design of RISC-V Extensions for Accelerating Sparse DNNs on FPGAs TinyML: Tools, Applications, Challenges, and Future Research Directions

Reference 3

Resolution: verified exact; doi, observed 2026-08-16T05:52:37.930998Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-22T06:32:14.747728+00:00.

Observation 3ba19d01-2819-4f6e-8d72-61871943943e · outbound

This paper cites Waterman and K.

Hardware/Software Co-Design of RISC-V Extensions for Accelerating Sparse DNNs on FPGAs Waterman and K

Reference 4

Resolution: verified fuzzy; raw_fallback, observed 2026-08-16T05:52:38.643165Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-22T06:32:14.747728+00:00.

Observation 3726830a-7c54-4214-9264-c1839c75c19e · outbound

This paper cites Ha and J.

Hardware/Software Co-Design of RISC-V Extensions for Accelerating Sparse DNNs on FPGAs Ha and J

Reference 5

Resolution: verified exact; doi, observed 2026-08-16T05:52:37.915370Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-22T06:32:14.747728+00:00.

Observation 51751867-b6b6-4d53-a679-38e9a1e6ce6b · outbound

This paper cites CFU Playground: Want a Faster ML Processor? Do it Yourself!.

Hardware/Software Co-Design of RISC-V Extensions for Accelerating Sparse DNNs on FPGAs CFU Playground: Want a Faster ML Processor? Do it Yourself!

Reference 6

Resolution: malformed identifier; no resolver link, observed 2026-08-16T05:52:37.700476Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation cc82b7a3-0d96-4e1a-9afb-55e7c7dfc299 · outbound

This paper cites A Survey on Deep Neural Network Pruning-Taxonomy, Comparison, Analysis, and Recommendations.

Hardware/Software Co-Design of RISC-V Extensions for Accelerating Sparse DNNs on FPGAs A Survey on Deep Neural Network Pruning-Taxonomy, Comparison, Analysis, and Recommendations

Reference 8

Resolution: unresolved; no resolver link, observed 2026-08-16T05:52:37.710746Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 83b7ab24-4f9c-4a9b-8243-fc5fab413c35 · outbound

This paper cites Hardware-Aware Evolutionary Explainable Filter Pruning for Convolutional Neural Networks.

Hardware/Software Co-Design of RISC-V Extensions for Accelerating Sparse DNNs on FPGAs Hardware-Aware Evolutionary Explainable Filter Pruning for Convolutional Neural Networks

Reference 9

Resolution: verified exact; doi, observed 2026-08-16T05:52:37.898257Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-22T06:32:14.747728+00:00.

Observation 30afe8f0-72b5-4d0a-a0e4-e7e55c1e2e8b · outbound

This paper cites ESL Power and Performance Estimation for Heterogeneous MPSoCs using SystemC.

Hardware/Software Co-Design of RISC-V Extensions for Accelerating Sparse DNNs on FPGAs ESL Power and Performance Estimation for Heterogeneous MPSoCs using SystemC

Reference 10

Resolution: verified fuzzy; raw_fallback, observed 2026-08-16T05:52:38.626543Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-22T06:32:14.747728+00:00.

Observation c6225708-bbd1-4fbe-aeb6-0e2556c3b8f9 · outbound

This paper cites What is the State of Neural Network Pruning?.

Hardware/Software Co-Design of RISC-V Extensions for Accelerating Sparse DNNs on FPGAs What is the State of Neural Network Pruning?

Reference 11

Resolution: verified fuzzy; raw_fallback, observed 2026-08-16T05:52:38.607271Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-22T06:32:14.747728+00:00.

Observation 41c1dc07-bb68-436e-ad8d-3e826f47f48a · outbound

This paper cites an unresolved cited work.

Hardware/Software Co-Design of RISC-V Extensions for Accelerating Sparse DNNs on FPGAs Unresolved cited work

Reference 12

Resolution: malformed identifier; no resolver link, observed 2026-08-16T05:52:37.734560Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 5cfaf7c5-317f-4f47-b6a1-f96272faa2c7 · outbound

This paper cites Accelerating Sparse Deep Neural Networks.

Hardware/Software Co-Design of RISC-V Extensions for Accelerating Sparse DNNs on FPGAs Accelerating Sparse Deep Neural Networks

Reference 13

Resolution: unresolved; no resolver link, observed 2026-08-16T05:52:37.742537Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation a1c4af31-0079-4327-8538-f9edeaaef2d0 · outbound

This paper cites SparseRT: Accelerating Unstructured Sparsity on GPUs for Deep Learning Inference.

Hardware/Software Co-Design of RISC-V Extensions for Accelerating Sparse DNNs on FPGAs SparseRT: Accelerating Unstructured Sparsity on GPUs for Deep Learning Inference

Reference 14

Resolution: unresolved; no resolver link, observed 2026-08-16T05:52:37.748232Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation c76a022e-94a5-44a6-90a9-9ae985d258a2 · outbound

This paper cites SNAP: An Efficient Sparse Neural Acceleration Processor for Unstructured Sparse Deep Neural Network Inference.

Hardware/Software Co-Design of RISC-V Extensions for Accelerating Sparse DNNs on FPGAs SNAP: An Efficient Sparse Neural Acceleration Processor for Unstructured Sparse Deep Neural Network Inference

Reference 15

Resolution: unresolved; no resolver link, observed 2026-08-16T05:52:37.753191Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation bc954b66-ee62-446f-ad75-35659e4e6422 · outbound

This paper cites DANNA: A Dimension-Aware Neural Net- work Accelerator for Unstructured Sparsity.

Hardware/Software Co-Design of RISC-V Extensions for Accelerating Sparse DNNs on FPGAs DANNA: A Dimension-Aware Neural Net- work Accelerator for Unstructured Sparsity

Reference 16

Resolution: unresolved; no resolver link, observed 2026-08-16T05:52:37.757756Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation b0cc59be-0140-4cc2-bfb9-2d57815aac65 · outbound

This paper cites IndexMAC: A Custom RISC-V Vector In- struction to Accelerate Structured-Sparse Matrix Multiplications.

Hardware/Software Co-Design of RISC-V Extensions for Accelerating Sparse DNNs on FPGAs IndexMAC: A Custom RISC-V Vector In- struction to Accelerate Structured-Sparse Matrix Multiplications

Reference 17

Resolution: unresolved; no resolver link, observed 2026-08-16T05:52:37.763739Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation d6feb38d-4109-4daa-9cfe-9302eab7cf95 · outbound

This paper cites VexRiscv Core.

Hardware/Software Co-Design of RISC-V Extensions for Accelerating Sparse DNNs on FPGAs VexRiscv Core

Reference 18

Resolution: verified fuzzy; raw_fallback, observed 2026-08-16T05:52:38.589958Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-22T06:32:14.747728+00:00.

Observation d36c03b6-609b-45ab-9988-ea6cbe74d1fa · outbound

This paper cites TensorFlow: Large-Scale Machine Learning on Heterogeneous Systems.

Hardware/Software Co-Design of RISC-V Extensions for Accelerating Sparse DNNs on FPGAs TensorFlow: Large-Scale Machine Learning on Heterogeneous Systems

Reference 19

Resolution: verified fuzzy; raw_fallback, observed 2026-08-16T05:52:38.574383Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-22T06:32:14.747728+00:00.

Observation ae93522c-1e00-4b32-aea4-6c2d6b151020 · outbound

This paper cites Learning Multiple Layers of Features from Tiny Images.

Hardware/Software Co-Design of RISC-V Extensions for Accelerating Sparse DNNs on FPGAs Learning Multiple Layers of Features from Tiny Images

Reference 20

Resolution: verified fuzzy; raw_fallback, observed 2026-08-16T05:52:38.544054Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-22T06:32:14.747728+00:00.

Observation 0bd2e9ba-bf9a-427d-85af-6dc79c411683 · outbound

This paper cites Speech Commands: A Dataset for Limited-Vocabulary Speech Recognition.

Hardware/Software Co-Design of RISC-V Extensions for Accelerating Sparse DNNs on FPGAs Speech Commands: A Dataset for Limited-Vocabulary Speech Recognition

Reference 21

Resolution: unresolved; no resolver link, observed 2026-08-16T05:52:37.790595Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 5a863929-b08c-4e04-abd9-aabb5d9dd2b1 · outbound

This paper cites Visual Wake Words Dataset.

Hardware/Software Co-Design of RISC-V Extensions for Accelerating Sparse DNNs on FPGAs Visual Wake Words Dataset

Reference 22

Resolution: unresolved; no resolver link, observed 2026-08-16T05:52:37.795622Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 310d7f54-d289-4d19-a4ce-1414bac816ae · outbound

This paper cites Microsoft COCO: Common Objects in Context.

Hardware/Software Co-Design of RISC-V Extensions for Accelerating Sparse DNNs on FPGAs Microsoft COCO: Common Objects in Context

Reference 23

Resolution: unresolved; no resolver link, observed 2026-08-16T05:52:37.800458Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation ec68fc37-5be3-48b3-a4a4-05d469d294f3 · outbound

This paper cites Utilizing Explainable AI for Quantization and Pruning of Deep Neural Networks.

Hardware/Software Co-Design of RISC-V Extensions for Accelerating Sparse DNNs on FPGAs Utilizing Explainable AI for Quantization and Pruning of Deep Neural Networks

Reference 24

Resolution: unresolved; no resolver link, observed 2026-08-16T05:52:37.805577Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 45b6df8d-8d07-4939-9487-f62204fef5f9 · outbound

This paper cites DyFiP: Explainable AI-based Dynamic Filter Pruning of Convolutional Neural Networks.

Hardware/Software Co-Design of RISC-V Extensions for Accelerating Sparse DNNs on FPGAs DyFiP: Explainable AI-based Dynamic Filter Pruning of Convolutional Neural Networks

Reference 25

Resolution: metadata mismatch; raw_fallback, observed 2026-08-16T05:52:38.075169Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-22T06:32:14.747728+00:00.

Observation eedda1e3-b115-4a83-b9e6-e2baddae6098 · outbound

This paper cites MOSP: Multi- Objective Sensitivity Pruning of Deep Neural Networks.

Hardware/Software Co-Design of RISC-V Extensions for Accelerating Sparse DNNs on FPGAs MOSP: Multi- Objective Sensitivity Pruning of Deep Neural Networks

Reference 26

Resolution: verified fuzzy; raw_fallback, observed 2026-08-16T05:52:38.527754Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-22T06:32:14.747728+00:00.

Observation 779e4d9f-f66b-413e-b852-f5f3c1214ca1 · outbound

This paper cites An Efficient Hardware Accelerator for Sparse Convolutional Neural Networks on FPGAs.

Hardware/Software Co-Design of RISC-V Extensions for Accelerating Sparse DNNs on FPGAs An Efficient Hardware Accelerator for Sparse Convolutional Neural Networks on FPGAs

Reference 27

Resolution: verified exact; doi, observed 2026-08-16T05:52:37.867029Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-22T06:32:14.747728+00:00.

Observation fc7e30ec-f26b-47cf-b8b6-9c5eff1e6e17 · outbound

This paper cites EasyQuant: Post-training Quantization via Scale Optimization.

Hardware/Software Co-Design of RISC-V Extensions for Accelerating Sparse DNNs on FPGAs EasyQuant: Post-training Quantization via Scale Optimization

Reference 28

Resolution: unresolved; no resolver link, observed 2026-08-16T05:52:37.826320Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 333a0e0b-d5d5-4eaa-a0d2-14327bd0e329 · outbound

This paper cites an unresolved cited work.

Hardware/Software Co-Design of RISC-V Extensions for Accelerating Sparse DNNs on FPGAs Unresolved cited work

Reference 2015

Resolution: unresolved; raw_fallback, observed 2026-08-16T05:52:38.559082Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-22T06:32:14.747728+00:00.

Pith citing papers

No inbound Pith citation observations are available.