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Development of an interface for digital neuromorphic hardware based on an FPGA

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arxiv 2308.09049 v1 pith:DWJMGTAD submitted 2023-08-17 eess.SP

Development of an interface for digital neuromorphic hardware based on an FPGA

classification eess.SP
keywords hardwareneuromorphicsystembiologicalbraindevelopmentdigitalengineering
verification ladder T0 review T1 audit T2 compute T3 formal T4 reserved
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Exploring and understanding the functioning of the human brain is one of the greatest challenges for current research. Neuromorphic engineering tries to address this challenge by abstracting biological mechanisms and translating them into technology. Via the abstraction process and experiments with the resulting technical system, an attempt is made to obtain information about the biological counterpart. One subsection of Neuromorphic Engineering (NE) are Spiking Neural Networks (SNN), which describe the structures of the human brain more and more closely than Artificial Neural Networks (ANN). Together with their dedicated hardware, SNNs provide a good platform for developing new algorithms for information processing. In the context of these neuromorphic hardware platforms, this paper aims to develop an interface for a digital hardware platform (SPINN-3 Development Board) to enable the use of industrial or conventional sensors and thus create new approaches for experimental research. The basis for this endeavor is a Field Programmable Gate Array (FPGA), which is placed as a gateway between the sensors and the neuromorphic hardware. Overall, the developed system provides a robust solution for a wide variety of investigations related to neuromorphic hardware and SNNs. Furthermore, the solution also offers suitable possibilities to monitor all processes within the system in order to obtain suitable measurements, which can be examined in search of meaningful results.

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