Revolution or Hype? Seeking the Limits of Large Models in Hardware Design

Grace Li Zhang; Igor L. Markov; Leon Stok; Qiang Xu; Rolf Drechsler; Xi Wang

REVIEW 3 major objections 6 minor 50 references

Revolution or Hype? Seeking the Limits of Large Models in Hardware Design

T0 review · 3 major / 6 minor · reviewed 2026-08-05 · deepseek-v4-flash

Challenge this review Re-run · record.json Download PDF Read on arXiv ↗

Pith's one-line read This paper argues that large models in hardware design become trustworthy only when paired with formal verification and a clear split between language models and circuit-native models.

desk verdict A useful, balanced panel position paper that reads as expert synthesis rather than research; the LLM/LCM division is a clean framing, but two citations point the wrong way and the central premise is asserted, not tested. read the letter →

arxiv 2509.04905 v1 pith:E2IKJYWK submitted 2025-09-05 cs.LG

Qiang Xu , Leon Stok , Rolf Drechsler , Xi Wang , Grace Li Zhang , Igor L. Markov This is my paper

classification cs.LG

keywords largelanguagemodelscircuitelectronicdesignautomationhardwareformalverificationRTLgenerationPPAoptimizationAIreliability

verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

The paper is a position statement, built around a 2025 design-automation panel, asking whether large AI models will transform chip design or remain overhyped. It argues that the honest answer is both: LLMs already help with specification, code snippets, assertions, and debugging, but they hallucinate, cannot be trusted with high-precision numerical work, and are trained on text rather than circuit structure. To move from demonstrations to production, the paper proposes a division of labor — LLMs interpret design intent, circuit-native LCMs handle structural optimization, and formal verification validates every generated artifact. The reader should care because chip bugs can cost millions and cause silicon failures; whether this roadmap works decides if AI-assisted design becomes a routine engineering tool or a permanent niche.

What carries the argument

The central mechanism is the 'What versus How' split: LLMs as the front-door natural-language interface ('what' the chip should do), LCMs as the back-end expert reasoning engine ('how' to build it correctly and efficiently), with formal verification as the mandatory trust anchor between them. The paper's motivation rests on the PPA ceiling (heuristics converging to local optima) and the semantic gap (circuit state changes have non-local effects invisible to sequential text models).

What would settle it

A controlled evaluation in which a general-purpose, text-only LLM or generic agentic system matches or beats a circuit-specialized model on held-out gate-level netlists for delay, area, and power would contradict the paper's claim that circuit data needs native LCMs.

Watch

Extended reading notes

Core claim

This paper, prepared as the basis for a 2025 design-automation panel debate, argues that large models are neither an instant revolution nor a passing fad. Their real contribution, the authors claim, will come from a division of labor: language models, good at interpreting high-level human intent, should turn specifications into formal descriptions and verification collateral; circuit-native models, trained on logic, topology, and geometry together, should carry the optimization-heavy 'how' work; and formal verification must sit at the center, certifying every generative output before it is trusted. The paper's skeptical corrections — hallucinations, data scarcity, the semantic gap between te

Load-bearing premise

The roadmap assumes that general-purpose language models trained on text cannot natively handle the graph-structured, multimodal nature of circuits, and that separate circuit-native models are therefore necessary.

Editorial extensions

If this is right

LLM-based tools are likely to be adopted early in the design flow for specification translation, testbench and assertion generation, and report triage, but not for final sign-off.
LCMs will need graph-native architectures and multimodal datasets spanning RTL to layout before they can become trusted PPA optimization engines.
Any AI-generated code, assertion, or testbench must pass formal or otherwise deterministic verification before entering production flows.
Benchmarks should shift from RTL code-generation accuracy toward real-world proxy metrics: timing closure, PPA, functional correctness under formal verification, and generalization without data leakage.
Synthetic data generation and privacy-preserving deployment, such as on-premise inference, are necessary to overcome proprietary data scarcity.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

If graph-native LLM backbones become practical, the boundary between LLM and LCM may dissolve, with a single model handling both intent and structure; the paper's division of labor is an assumption, not a law.
The paper's formal-verification anchor suggests a testable design: an automated loop where every LLM or LCM edit is checked by equivalence checking or model checking; its cost, not the model, will decide industrial adoption.
Because benchmark saturation is already happening, the next round of progress claims is likely to be on more holistic benchmarks, making independent third-party evaluation of training data the key trust mechanism.
If synthetic data generation matures for circuits, data scarcity may become a shorter-term bottleneck than the semantic gap, reversing the priority of LCM research.

Share X Bluesky LinkedIn Reddit HN

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Desk Editor's Note

read the letter

Colleague, quick take: this is a well-organized survey/panel summary, not a research paper. It gives the EDA community a readable map of where LLMs and LCMs stand, and the 'What vs How' split between LLMs (intent) and LCMs (circuit-native optimization) is genuinely clean. If you work in AI-for-EDA, you will find the literature coverage and the panelist positions useful as a shared reference.

What it does well: the paper is balanced. It doesn't just cheerlead; the panelists uniformly stress reliability, verification, data scarcity, and sign-off. The conclusion—generative outputs must be anchored in formal verification—is sensible and well-aligned with existing evidence. It also gives due credit to hybrid systems and LLM-plus-tool workflows, which is where most current value is.

Soft spots, in order of real impact. The citation mismatches are real and visible. [39] is a chain-of-thought/data-distribution paper, not support for Stok's practical LLM use cases. [43] is titled 'Transformers can do arithmetic with the right embeddings'—a positive result—yet the text cites it for the claim that LLMs struggle with basic arithmetic. Both are easy to fix but they signal careless sourcing. The load-bearing premise, in IV.B and V.A, is that text-trained LLMs cannot capture circuit structure because a minor netlist change can have non-local effects. That is plausible expert opinion, but it is stated, not demonstrated. If a future LLM or agent handles graph-structured data well, the sharp LLM/LCM division becomes one design choice among several, not a necessity. The paper should acknowledge that as an open question.

There is also a mild self-referential bias: much of the LCM advocacy is co-authored by Xu, who originated the LCM term. That's not a flaw by itself, but it means the roadmap should be read as advocacy plus expert opinion, not independent evidence.

Overall: for what it is—a foundational text for a panel—it does its job. It has no new data or derivations, so it won't change minds on its own. But as a synthesis it deserves a serious referee: someone should catch the citation errors, and the authors should soften the semantic-gap claim to 'currently underexplored' rather than 'not captured.' I'd accept it for workshop/panel publication after minor revision, and I'd cite it as a useful overview. Bring it to reading group if you want a snapshot of where the field's senior voices stand.

Referee Report

3 major / 6 minor

Summary. This manuscript is a position/panel paper prepared for an ICCAD 2025 panel. It surveys the recent wave of large language models (LLMs) and large circuit models (LCMs) for hardware design, summarizing current tools and benchmarks, enumerating opportunities (RTL generation, verification, design-space exploration, tool orchestration), and cataloguing challenges (reliability/hallucination, semantic gap, data scarcity, explainability). The central thesis is a division of labor: LLMs interpret high-level design intent ('the What') and LCMs, which natively understand circuit structure, perform optimization and implementation ('the How'), with formal verification anchoring all generative outputs. The paper synthesizes opinions from six experts and concludes that large models are a disruptive force but their integration requires solving reliability, data, and precision problems.

Significance. As a synthesis by leading EDA researchers, the paper provides a useful snapshot of the LLM/LCM landscape and articulates a concrete research roadmap. Its strengths are that it names and organizes many recent systems, distinguishes LLMs from LCMs, and explicitly prioritizes verification and trust. The paper is honest about its nature: it contains no new data or derivations, and its value rests on the expertise of the panelists. However, the central roadmap depends on a claim about a 'semantic gap' that is stated rather than demonstrated, and two supporting citations are mischaracterized. If the roadmap is understood as a testable research proposal, the paper is a valuable starting point; if it is taken as an established necessity, the evidence is currently insufficient.

major comments (3)

[§V.A and §IV.B] The central LLM/LCM division of labor rests on the premise that general-purpose LLMs trained on text cannot capture circuit structure because 'a minor change in a netlist's structure can trigger serious non-local effects' and 'this causality is not natively captured by models trained on sequential text.' This is asserted, not established. The paper's own survey of LLM-based RTL generation (e.g., RTLCoder, VerilogCoder) shows that text-based models can generate substantially correct RTL, suggesting that the semantic gap is not absolute. As written, the sharp division is one plausible design choice rather than a demonstrated necessity. Please either provide empirical evidence (e.g., controlled comparisons of text-only vs. graph-native models on circuit tasks) or explicitly reframe the roadmap as a hypothesis with falsifiable predictions.
[§V.A, Refs. [43] and [39]] Two citations point the wrong way. (1) Ref. [43] is cited to support 'They struggle with even basic arithmetic operations [43],' but this paper is titled 'Transformers can do arithmetic with the right embeddings' and reports positive results conditional on input embeddings. Citing it as evidence of a fundamental arithmetic limitation misrepresents the source; please replace it with work that actually demonstrates such a limitation, or qualify the claim to reflect that arithmetic accuracy is achievable with suitable encodings. (2) Ref. [39] is cited immediately after 'practical use cases where LLMs are already proving valuable,' but [39] is a study of chain-of-thought reasoning and data distributions, not a collection of EDA use cases. The actual practical examples are cited in [40] and [41]. Either remove [39] or move it to a context where its content is relevant.
[§V.A (Markov's arithmetic claim)] Independent of the citation issue, the manuscript treats 'standard transformers are generally inefficient at representing and reasoning over high-precision numerical values' as a settled limitation. This is a load-bearing assumption for the paper's recommendation that LCMs adopt different architectures. It is an expert opinion, not a demonstrated result, and it is important because the entire 'moat' argument for traditional algorithms depends on it. Please distinguish established findings from expert conjecture, and suggest how this claim could be evaluated empirically.

minor comments (6)

[§II.B] Typo: 'must use natively handle' should be 'must natively handle'.
[§IV.D] Punctuation error: 'with complex and opaque decision-making, .and especially' should be 'with complex and opaque decision-making, and especially'.
[§III.C] 'wholistic' should be 'holistic'. Also 'reveals patterns of PPA optimization gives them' has a subject-verb agreement issue.
[Panelist Biographies] Typo in Rolf Drechsler's biography: 'Internationa' should be 'International'.
[References [35]] Reference [35] has a stray comma in the author list: 'C. K. Jha, ,'.
[Figures 2 and 3] The timeline figures are dense and have no axes or legend. Consider adding a brief caption explanation of what the colors/positions mean, as this is important for a reader who encounters the figures outside the panel context.

Circularity Check

0 steps flagged · score 0.0 of 10

No circularity: the paper is an opinion/position piece with no derivation chain, equations, or fitted parameters; self-citations are background, not load-bearing.

full rationale

This paper is a panel-style position paper synthesizing expert opinions on large models in hardware design. It contains no equations, no fitted parameters, and no claimed prediction that reduces to its inputs. The central discussion—whether LLMs or specialized LCMs are needed—is presented as expert argument and recommendation, not as a derived result. Self-citations (e.g., DeepGate, ChatCPU, AutoBench) appear in background surveys and as examples of prior work, but the paper's main claims do not logically depend on those results being correct. The LLM-vs-LCM division of labor is justified by an asserted 'semantic gap' between text and circuit structure, but that assertion is an expert opinion, not a circular derivation. The skeptical note about misfiled references (e.g., [43] cited as showing arithmetic struggles when the paper actually shows transformers can do arithmetic with right embeddings) concerns citation accuracy and argument support, not circularity. No step in the paper reduces a 'prediction' or 'first-principles result' to its own inputs. Therefore, the appropriate circularity score is 0.

Assumptions & free parameters 0 free parameters · 4 assumptions · 0 invented entities

The paper introduces no new entities or free parameters. Its recommendations rest on domain assumptions about circuit representation, LLM reliability, data availability, and the limits of classical EDA heuristics. These assumptions are plausible and widely discussed, but not empirically validated within this paper.

assumptions (4)

domain assumption Circuit data is inherently multimodal and text encoding loses critical structure.
Section IV.B argues that natural language cannot capture the interplay of function, topology, and geometry. This motivates the need for LCMs and is load-bearing for the paper's central recommendation.
domain assumption LLMs are probabilistic and prone to hallucinations, so outputs must be formally verified.
Section IV.A and V.B repeatedly assert this as the key barrier to adoption. It underpins the recommendation to couple AI with formal methods.
domain assumption Public IC design data is scarce and mostly proprietary, limiting large-model training.
Section IV.C states that the amount of public data is orders of magnitude smaller than for natural language, and proprietary data is compartmentalized. This is cited as a major showstopper.
domain assumption Current EDA algorithms are approaching a 'PPA ceiling' with local optima, creating opportunity for AI.
Figure 1 and Section I postulate this qualitative ceiling, motivating the search for holistic, data-driven optimization. The panel does not provide quantitative evidence.

how reviews work

0 comments

Cite this review

Pith. "Pith review of Revolution or Hype? Seeking the Limits of Large Models in Hardware Design." pith.science (2026). https://pith.science/paper/E2IKJYWK

@misc{pith2026250904905,
  author       = {Pith},
  title        = {Pith review of: Revolution or Hype? Seeking the Limits of Large Models in Hardware Design},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/E2IKJYWK}},
  note         = {Machine review of arXiv:2509.04905}
}

read the original abstract

Recent breakthroughs in Large Language Models (LLMs) and Large Circuit Models (LCMs) have sparked excitement across the electronic design automation (EDA) community, promising a revolution in circuit design and optimization. Yet, this excitement is met with significant skepticism: Are these AI models a genuine revolution in circuit design, or a temporary wave of inflated expectations? This paper serves as a foundational text for the corresponding ICCAD 2025 panel, bringing together perspectives from leading experts in academia and industry. It critically examines the practical capabilities, fundamental limitations, and future prospects of large AI models in hardware design. The paper synthesizes the core arguments surrounding reliability, scalability, and interpretability, framing the debate on whether these models can meaningfully outperform or complement traditional EDA methods. The result is an authoritative overview offering fresh insights into one of today's most contentious and impactful technology trends.

Figures

Figures reproduced from arXiv: 2509.04905 by the authors.

**Figure 2.** Large Language Models for Hardware Design [PITH_FULL_IMAGE:figures/full_fig_p002_2.png] view at source ↗

**Figure 3.** Large Circuit Models for Hardware Design [PITH_FULL_IMAGE:figures/full_fig_p003_3.png] view at source ↗

Figures from the paper (1 more)

**Figure 4.** Figure 4: Applicability of generative models across the EDA workflow [PITH_FULL_IMAGE:figures/full_fig_p005_4.png]

Discussion (0). Sign in to comment.

Reference graph

Works this paper leans on

50 extracted references · 41 canonical work pages

[39]

Is chain-of-thought reasoning of LLMs a mirage? a data distribution lens,

C. Zhao, Z. Tan, P. Ma, D. Li, B. Jiang, Y . Wang, Y . Yang, and H. Liu, “Is chain-of-thought reasoning of LLMs a mirage? a data distribution lens,”arXiv:2508.01191, 2025

arXiv 2025
[43]

Transformers can do arithmetic with the right em- beddings,

S. McLeishet al., “Transformers can do arithmetic with the right em- beddings,”Advances in Neural Information Processing Systems, vol. 37, pp. 108 012–108 041, 2024

work page 2024
[40]

Improving llm-powered eda assistants with raft,

L. Shi, M. Kazda, C. Schmitter, and H. Gupta, “Improving llm-powered eda assistants with raft,” inICLAD, 2025

work page 2025
[41]

Customizing a Large Language Model for VHDL Design of High-Performance Microprocessors

N. Dupuis, R. Nair, S. Ramji, S. McClintock, N. Chauhan, P. Nag- pal, B. Blaner, K. Valk, L. Stok, and R. Puri, “Customizing a large language model for vhdl design of high-performance microprocessors,” arXiv:2505.09610, 2025

work page Pith review arXiv 2025
[1]

Global semiconductor sales in- crease 19.1% in 2024; double-digit growth projected in 2025,

Semiconductor Industry Association, “Global semiconductor sales in- crease 19.1% in 2024; double-digit growth projected in 2025,” https: //www.semiconductors.org/global- semiconductor- sales- increase- 19- 1- in- 2024- double- digit- growth- projected- in- 2025/, February 2025, accessed: 2025-08-02

work page 2024
[2]

The semiconductor decade: A trillion-dollar industry,

O. Burkacky, J. Dragon, and N. Lehmann, “The semiconductor decade: A trillion-dollar industry,” McKinsey & Company, Tech. Rep., April 2022. [Online]. Available: https://www.mckinsey. com/industries/semiconductors/our-insights/the-semiconductor-decade- a-trillion-dollar-industry

work page 2022
[3]

Electronic design automation (eda) global market report 2025,

The Business Research Company, “Electronic design automation (eda) global market report 2025,” Tech. Rep., 2025. [Online]. Available: https://www.thebusinessresearchcompany.com/report/electronic-design- automation-eda-global-market-report

work page 2025
[4]

Machine learning for electronic design automation: A survey,

G. Huang, J. Hu, Y . He, J. Liu, M. Ma, Z. Shen, J. Wu, Y . Xu, H. Zhang, K. Zhonget al., “Machine learning for electronic design automation: A survey,”TODAES, vol. 26, no. 5, pp. 1–46, 2021

work page 2021

Show all 50 references

[5]

A survey of research in large language models for electronic design automation,

J. Pan, G. Zhou, C.-C. Chang, I. Jacobson, J. Hu, and Y . Chen, “A survey of research in large language models for electronic design automation,” TODAES, vol. 30, no. 3, pp. 1–21, 2025

2025
[6]

Chatcpu: An agile cpu design and verification platform with llm,

X. Wang, G.-W. Wan, S.-Z. Wong, L. Zhang, T. Liu, Q. Tian, and J. Ye, “Chatcpu: An agile cpu design and verification platform with llm,” in DAC, 2024, pp. 1–6

2024
[7]

Llm-based processor verification: A case study for neuromorphic processor,

C. Xiao, Y . Deng, Z. Yang, R. Chen, H. Wang, J. Zhao, H. Dai, L. Wang, Y . Tang, and W. Xu, “Llm-based processor verification: A case study for neuromorphic processor,” inDATE. IEEE, 2024, pp. 1–6

2024
[8]

Llm-guided formal verification coupled with mutation testing,

M. Hassan, S. Ahmadi-Pour, K. Qayyum, C. K. Jha, and R. Drechsler, “Llm-guided formal verification coupled with mutation testing,” in DATE. IEEE, 2024, pp. 1–2

2024
[9]

Rtl- coder: Fully open-source and efficient llm-assisted rtl code generation technique,

S. Liu, W. Fang, Y . Lu, J. Wang, Q. Zhang, H. Zhang, and Z. Xie, “Rtl- coder: Fully open-source and efficient llm-assisted rtl code generation technique,”TCAD, 2024

2024
[10]

Verilogcoder: Autonomous Verilog coding agents with graph-based planning and abstract syntax tree (ast)- based waveform tracing tool,

C.-T. Ho, H. Ren, and B. Khailany, “Verilogcoder: Autonomous Verilog coding agents with graph-based planning and abstract syntax tree (ast)- based waveform tracing tool,” inAAAI, vol. 39, no. 1, 2025, pp. 300–307

2025
[11]

Large circuit models: opportunities and challenges,

L. Chen, Y . Chen, Z. Chuet al., “Large circuit models: opportunities and challenges,”Science China Information Sciences, 2024

2024
[12]

Chipgpt: How far are we from natural language hardware design,

K. Chang, Y . Wang, H. Ren, M. Wang, S. Liang, Y . Han, H. Li, and X. Li, “Chipgpt: How far are we from natural language hardware design,”arXiv:2305.14019, 2023

2023
[13]

Revisiting verilogeval: A year of improvements in large-language models for hardware code generation,

N. Pinckneyet al., “Revisiting verilogeval: A year of improvements in large-language models for hardware code generation,”TODAES, 2025

2025
[14]

Comprehensive Verilog design problems: A next-generation benchmark dataset for evaluating large language models and agents on rtl design and verification,

N. Pinckney, C. Deng, C.-T. Ho, Y .-D. Tsai, M. Liu, W. Zhou, B. Khailany, and H. Ren, “Comprehensive Verilog design problems: A next-generation benchmark dataset for evaluating large language models and agents on rtl design and verification,”arXiv:2506.14074, 2025

2025 arXiv
[15]

Betterv: Controlled verilog generation with discriminative guidance,

Z. Pei, H. Zhen, M. Yuan, Y . Huang, and B. Yu, “Betterv: Controlled verilog generation with discriminative guidance,” inICML. PMLR, 2024, pp. 40 145–40 153

2024
[16]

Deeprtl: Bridging verilog understanding and generation with a unified representation model,

Y . Liu, X. Changran, Y . Zhou, Z. Li, and Q. Xu, “Deeprtl: Bridging verilog understanding and generation with a unified representation model,” inICLR, 2025

2025
[17]

Deeprtl2: A versatile model for rtl-related tasks,

Y . Liu, H. Zhang, Y . Zhou, Z. Shi, C. Xu, and Q. Xu, “Deeprtl2: A versatile model for rtl-related tasks,” inACL, 2025

2025
[18]

Synthai: A multi agent gen- erative ai framework for automated modular hls design generation,

S. A. Sheikholeslam and A. Ivanov, “Synthai: A multi agent gen- erative ai framework for automated modular hls design generation,” arXiv:2405.16072, 2024

2024 arXiv
[19]

Assertllm: Generating hardware verification assertions from design specifications via multi-llms,

Z. Yan, W. Fang, M. Li, M. Li, S. Liu, Z. Xie, and H. Zhang, “Assertllm: Generating hardware verification assertions from design specifications via multi-llms,” inASP-DAC, 2025, pp. 614–621

2025
[20]

Assertionbench: A benchmark to evaluate large-language models for assertion generation,

V . Pulavarthi, D. Nandal, S. Dan, and D. Pal, “Assertionbench: A benchmark to evaluate large-language models for assertion generation,” inNAACL, 2025, pp. 8058–8065

2025
[21]

Rtlfixer: Automatically fixing rtl syntax errors with large language model,

Y . Tsai, M. Liu, and H. Ren, “Rtlfixer: Automatically fixing rtl syntax errors with large language model,” inDAC, 2024, pp. 1–6

2024
[22]

Chipnemo: Domain-adapted llms for chip design,

M. Liuet al., “Chipnemo: Domain-adapted llms for chip design,” arXiv:2311.00176, 2023

2023 arXiv
[23]

Customized retrieval augmented generation and benchmarking for eda tool documentation qa,

Y . Pu, Z. He, T. Qiu, H. Wu, and B. Yu, “Customized retrieval augmented generation and benchmarking for eda tool documentation qa,” inICCAD, 2024, pp. 1–9

2024
[24]

Drc-coder: Automated drc checker code generation using llm autonomous agent,

C.-C. Chang, C.-T. Ho, Y . Li, Y . Chen, and H. Ren, “Drc-coder: Automated drc checker code generation using llm autonomous agent,” inISPD, 2025, pp. 143–151

2025
[25]

Rtlrewriter: Methodologies for large models aided rtl code optimization,

X. Yao, Y . Wang, X. Li, Y . Lian, R. Chen, L. Chen, M. Yuan, H. Xu, and B. Yu, “Rtlrewriter: Methodologies for large models aided rtl code optimization,” inICCAD, 2024, pp. 1–7

2024
[26]

Deepgate: Learning neural representations of logic gates,

M. Li, S. Khan, Z. Shi, N. Wang, H. Yu, and Q. Xu, “Deepgate: Learning neural representations of logic gates,” inDAC, 2022, pp. 667–672

2022
[27]

Maskplace: Fast chip placement via reinforced visual representation learning,

Y . Lai, Y . Mu, and P. Luo, “Maskplace: Fast chip placement via reinforced visual representation learning,”NeurIPS, vol. 35, pp. 24 019– 24 030, 2022

2022
[28]

Deepgate3: Towards scalable circuit representation learning,

Z. Shi, Z. Zheng, S. Khan, J. Zhong, M. Li, and Q. Xu, “Deepgate3: Towards scalable circuit representation learning,” inICCAD, 2024

2024
[29]

Deepcell: Self-supervised multiview fusion for circuit representation learning,

Z. Shi, C. Ma, Z. Zheng, L. Zhou, H. Pan, W. Jiang, F. Yang, X. Yang, Z. Chu, and Q. Xu, “Deepcell: Self-supervised multiview fusion for circuit representation learning,”ICCAD, 2025

2025
[30]

Circuitfusion: Multimodal circuit representation learning for agile chip design,

W. Fang, S. Liu, J. Wang, and Z. Xie, “Circuitfusion: Multimodal circuit representation learning for agile chip design,” inICLR, 2025

2025
[31]

Autochip: Automating hdl generation using llm feedback,

S. Thakur, J. Blocklove, H. Pearce, B. Tan, S. Garg, and R. Karri, “Autochip: Automating hdl generation using llm feedback,” arXiv:2311.04887, 2023

2023 arXiv
[32]

Autobench: Automatic testbench generation and evaluation using LLMs for HDL design,

R. Qiu, G. L. Zhang, R. Drechsler, U. Schlichtmann, and B. Li, “Autobench: Automatic testbench generation and evaluation using LLMs for HDL design,” inMLCAD, 2024, pp. 1–10

2024
[33]

Uvllm: An automated universal rtl verification framework using llms,

Y . Hu, J. Ye, K. Xu, J. Sun, S. Zhang, X. Jiao, D. Pan, J. Zhou, N. Wang, W. Shanet al., “Uvllm: An automated universal rtl verification framework using llms,” inDAC, 2025

2025
[34]

Llms for hardware verification: Frameworks, techniques, and future directions,

K. Qayyum, S. Ahmadi-Pour, C. K. Jha, M. Hassan, and R. Drechsler, “Llms for hardware verification: Frameworks, techniques, and future directions,” inATS. IEEE, 2024

2024
[35]

Prompt. verify. repeat. llms in the hardware verification cycle,

M. Hassan, M. Nadeem, K. Qayyum, C. K. Jha, , and R. Drechsler, “Prompt. verify. repeat. llms in the hardware verification cycle,” in COINS. IEEE, 2025

2025
[36]

Chat- model: Automating reference model design and verification with llms,

J. Ye, T. Liu, Q. Tian, S. Su, Z. Jiang, and X. Wang, “Chat- model: Automating reference model design and verification with llms,” arXiv:2506.15066, 2025

2025 arXiv
[37]

Meic: Re-thinking rtl debug automation using llms,

K. Xu, J. Sun, Y . Hu, X. Fang, W. Shan, X. Wang, and Z. Jiang, “Meic: Re-thinking rtl debug automation using llms,” inICCAD, 2024, pp. 1–9

2024
[38]

Veridebug: A unified llm for Verilog debugging via contrastive embed- ding and guided correction,

N. Wang, B. Yao, J. Zhou, Y . Hu, X. Wang, N. Guan, and Z. Jiang, “Veridebug: A unified llm for Verilog debugging via contrastive embed- ding and guided correction,”arXiv:2504.19099, 2025

2025 arXiv
[42]

Accurate predictions on small data with a tabular foundation model,

N. Hollmannet al., “Accurate predictions on small data with a tabular foundation model,”Nature, vol. 637, no. 8045, pp. 319–326, 2025

2025
[44]

The illusion of thinking: Understanding the strengths and limitations of reasoning models via the lens of problem complexity,

P. Shojaeeet al., “The illusion of thinking: Understanding the strengths and limitations of reasoning models via the lens of problem complexity,” arXiv:2506.06941, 2025

2025 arXiv
[45]

Measuring the impact of early-2025 AI on experienced open-source developer productivity,

J. Becker, N. Rush, E. Barnes, and D. Rein, “Measuring the impact of early-2025 AI on experienced open-source developer productivity,” McKinsey & Company, Tech. Rep., July 2025. [Online]. Available: https://metr.org/blog/2025-07-10-early-2025-ai-experienced-os-dev- study/

2025
[46]

Correctbench: Automatic testbench generation with functional self- correction using LLMs for HDL design,

R. Qiu, G. L. Zhang, R. Drechsler, U. Schlichtmann, and B. Li, “Correctbench: Automatic testbench generation with functional self- correction using LLMs for HDL design,” inDATE, 2025, pp. 1–7

2025
[47]

Genben: A generative benchmark for LLM-aided design,

G.-W. Wan, Y . Wang, S.-Z. Wong, J. Xiong, Q. Chen, J. Zhang, M. Zhang, T. Ni, M. Xing, Y . Huaet al., “Genben: A generative benchmark for LLM-aided design,” inArxiv, 2025

2025
[48]

Fixme: Towards end-to-end bench- marking of llm-aided design verification,

G.-W. Wan, S. Su, R. Wang, Q. Chen, S.-Z. Wong, M. Xing, H. Feng, Y . Wang, Y . Zhu, J. Zhanget al., “Fixme: Towards end-to-end bench- marking of llm-aided design verification,”arXiv:2507.04276, 2025

2025 arXiv
[49]

Deepcircuitx: A comprehensive repository-level dataset for rtl code understanding, generation, and ppa analysis,

Z. Li, C. Xu, Z. Shi, Z. Peng, Y . Liu, Y . Zhouet al., “Deepcircuitx: A comprehensive repository-level dataset for rtl code understanding, generation, and ppa analysis,” inICLAD, 2025

2025
[50]

Forgeeda: A comprehensive multimodal dataset for advancing eda,

Z. Shi, Z. Li, C. Ma, Y . Zhou, Z. Zheng, J. Liu, H. Pan, L. Zhou, K. Li, J. Zhuet al., “Forgeeda: A comprehensive multimodal dataset for advancing eda,” inISEDA, 2025

2025

Pith tools

Reviewed August 5, 2026 · model on record in the stance chip above.

[1] [39]

Is chain-of-thought reasoning of LLMs a mirage? a data distribution lens,

C. Zhao, Z. Tan, P. Ma, D. Li, B. Jiang, Y . Wang, Y . Yang, and H. Liu, “Is chain-of-thought reasoning of LLMs a mirage? a data distribution lens,”arXiv:2508.01191, 2025

arXiv 2025

[2] [43]

Transformers can do arithmetic with the right em- beddings,

S. McLeishet al., “Transformers can do arithmetic with the right em- beddings,”Advances in Neural Information Processing Systems, vol. 37, pp. 108 012–108 041, 2024

work page 2024

[3] [40]

Improving llm-powered eda assistants with raft,

L. Shi, M. Kazda, C. Schmitter, and H. Gupta, “Improving llm-powered eda assistants with raft,” inICLAD, 2025

work page 2025

[4] [41]

Customizing a Large Language Model for VHDL Design of High-Performance Microprocessors

N. Dupuis, R. Nair, S. Ramji, S. McClintock, N. Chauhan, P. Nag- pal, B. Blaner, K. Valk, L. Stok, and R. Puri, “Customizing a large language model for vhdl design of high-performance microprocessors,” arXiv:2505.09610, 2025

work page Pith review arXiv 2025

[5] [1]

Global semiconductor sales in- crease 19.1% in 2024; double-digit growth projected in 2025,

Semiconductor Industry Association, “Global semiconductor sales in- crease 19.1% in 2024; double-digit growth projected in 2025,” https: //www.semiconductors.org/global- semiconductor- sales- increase- 19- 1- in- 2024- double- digit- growth- projected- in- 2025/, February 2025, accessed: 2025-08-02

work page 2024

[6] [2]

The semiconductor decade: A trillion-dollar industry,

O. Burkacky, J. Dragon, and N. Lehmann, “The semiconductor decade: A trillion-dollar industry,” McKinsey & Company, Tech. Rep., April 2022. [Online]. Available: https://www.mckinsey. com/industries/semiconductors/our-insights/the-semiconductor-decade- a-trillion-dollar-industry

work page 2022

[7] [3]

Electronic design automation (eda) global market report 2025,

The Business Research Company, “Electronic design automation (eda) global market report 2025,” Tech. Rep., 2025. [Online]. Available: https://www.thebusinessresearchcompany.com/report/electronic-design- automation-eda-global-market-report

work page 2025

[8] [4]

Machine learning for electronic design automation: A survey,

G. Huang, J. Hu, Y . He, J. Liu, M. Ma, Z. Shen, J. Wu, Y . Xu, H. Zhang, K. Zhonget al., “Machine learning for electronic design automation: A survey,”TODAES, vol. 26, no. 5, pp. 1–46, 2021

work page 2021