pith. sign in

arxiv: 1907.01442 · v1 · pith:EE754GZUnew · submitted 2019-06-30 · 📡 eess.SP · cs.IT· cs.NI· math.IT

Improved Circuit Design of Analog Joint Source Channel Coding for Low-power and Low-complexity Wireless Sensors

Xueyuan Zhao , Vidyasagar Sadhu , Anthony Yang , Dario Pompili This is my paper

Pith reviewed 2026-05-25 13:01 UTC · model grok-4.3

classification 📡 eess.SP cs.ITcs.NImath.IT
keywords analog joint source channel codingcircuit designlow powerwireless sensorsanalog divider blocksVCVSLTSpice
0
0 comments X

The pith

An analog divider block design for joint source-channel coding uses less power and fewer parts than parallel voltage sources when there are 16 or more levels.

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The paper introduces a circuit for analog joint source channel coding that relies on analog divider blocks to create tunable spacing between coding levels. These blocks switch between two kinds of voltage-controlled voltage sources. LTSpice simulations compare this approach to an earlier parallel voltage-controlled voltage source design. The new method shows better performance in power use and simplicity starting at 16 levels, which supports sensors that last longer while providing finer data resolution.

Core claim

The improved circuit design based on Analog Divider Blocks (ADB) with tunable spacing outperforms the parallel-VCVS design for AJSCC levels of 16 or more, both in power consumption and circuit complexity, according to LTSpice simulations.

What carries the argument

Analog Divider Blocks (ADB) that control switching between two types of Voltage Controlled Voltage Sources (VCVS) to achieve tunable AJSCC level spacing.

If this is right

  • Reduced power consumption enables longer operation of wireless sensors on limited battery power.
  • Lower circuit complexity simplifies manufacturing and reduces cost for sensor nodes.
  • Support for higher numbers of AJSCC levels allows finer quantization without proportional increase in power.
  • Persistent monitoring becomes feasible for environmental sensing applications requiring high temporal or spatial resolution.

Where Pith is reading between the lines

These are editorial extensions of the paper, not claims the author makes directly.

  • Real-world testing on fabricated chips would be needed to confirm if the simulation advantages persist under noise and variation.
  • Integration with energy-harvesting sources could further extend the operational lifetime of such sensors.
  • The tunable spacing might allow optimization for specific signal statistics in different sensing environments.

Load-bearing premise

The LTSpice simulations provide accurate predictions of power consumption and circuit complexity in actual fabricated circuits without accounting for component variations, noise, or manufacturing effects.

What would settle it

Building and measuring a physical ADB-based AJSCC circuit and a parallel-VCVS circuit at 16 or more levels to check if power consumption and complexity are indeed lower in the ADB version.

Figures

Figures reproduced from arXiv: 1907.01442 by Anthony Yang, Dario Pompili, Vidyasagar Sadhu, Xueyuan Zhao.

Figure 1
Figure 1. Figure 1: Shannon’s Rectangular Mapping [13]. The sensed point is mapped to the point closest on the rectangular curve, and the curve accumulated length from the origin to the mapped point (in bold) is transmitted instead of the two values identifying the 2D sensed point. Here the numbers are the voltages used in our Spice simulations. • We compare the proposal with previous design to show the lower power and circui… view at source ↗
Figure 2
Figure 2. Figure 2: Original analog circuit of parallel-VCVS design for Shannon’s rectan [PITH_FULL_IMAGE:figures/full_fig_p003_2.png] view at source ↗
Figure 3
Figure 3. Figure 3: (a) AJSCC output of the second stage—notice the four different regions: off, linear (Type-1 VCVS), linear (Type-2 VCVS), and saturation; (b) Measured SDR-vs-CSNR performance for one, two, and three Tier-1 all-analog sensors communicating with a Tier-2 digital Cluster Head (CH).; (c) Mean Square Error (MSE) vs. number of levels (n=L) for SNR=-20 dB, with optimum n=73; similar trends are observed for SNR=-10… view at source ↗
Figure 5
Figure 5. Figure 5: High-level overview of Design 2, where Voltage Divider and Odd/Even [PITH_FULL_IMAGE:figures/full_fig_p004_5.png] view at source ↗
Figure 6
Figure 6. Figure 6: LTSpice schematic of the proposed circuit with parameter [PITH_FULL_IMAGE:figures/full_fig_p005_6.png] view at source ↗
Figure 7
Figure 7. Figure 7: (a) High level view of a single stage analog divider with one analog divider block (ADB), which performs modulo by [PITH_FULL_IMAGE:figures/full_fig_p006_7.png] view at source ↗
Figure 8
Figure 8. Figure 8: (a) AJSCC encoded output of 16-level analog divider circuit with varying [PITH_FULL_IMAGE:figures/full_fig_p007_8.png] view at source ↗
read the original abstract

To enable low-power and low-complexity wireless monitoring, an improved circuit design of Analog Joint Source Channel Coding (AJSCC) is proposed for wireless sensor nodes. This innovative design is based on Analog Divider Blocks (ADB) with tunable spacing between AJSCC levels. The ADB controls the switching between two types of Voltage Controlled Voltage Sources (VCVS). LTSpice simulations were performed to evaluate the performance of the circuit, and the power consumption and circuit complexity of this new ADB-based design were compared with our previous parallel-VCVS design. It is found that this improved circuit design based on ADB outperforms the design based on parallel VCVS for a large number of AJSCC levels (>= 16), both in terms of power consumption as well as circuit complexity, thus enabling persistent and higher temporal/spatial resolution environmental sensing.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit. Tearing a paper down is the easy half of reading it; the pith above is the substance, this is the friction.

Referee Report

3 major / 2 minor

Summary. The manuscript proposes an improved analog circuit implementation of Joint Source Channel Coding (AJSCC) for low-power wireless sensors. The design replaces a prior parallel-VCVS architecture with Analog Divider Blocks (ADB) that provide tunable level spacing and control switching between two VCVS types. LTSpice simulations are used to compare power consumption and circuit complexity against the authors' earlier parallel-VCVS design, with the claim that the ADB version is superior for 16 or more AJSCC levels.

Significance. If the reported simulation advantages hold under realistic conditions, the work could support higher-resolution, lower-power environmental sensing nodes. The use of a standard simulator (LTSpice) and direct comparison to a previously published design by the same group aids reproducibility of the reported metrics. However, the absence of any hardware measurements or robustness analysis substantially reduces the immediate engineering impact.

major comments (3)
  1. [Abstract and simulation results] Abstract and simulation description: the headline claim that the ADB design outperforms the parallel-VCVS design for N >= 16 in both power and complexity rests entirely on LTSpice transient and power simulations; no numerical power values, complexity counts, error bars, or Monte-Carlo statistics are supplied, preventing quantitative assessment of the improvement magnitude.
  2. [Circuit evaluation] Circuit evaluation section: no corner-case, mismatch, noise, or parasitic-extraction analysis is performed on the ADB or VCVS blocks, even though device variation and finite GBW routinely alter both power draw and the number of distinguishable levels in analog divider circuits; this directly undermines the load-bearing performance comparison.
  3. [Comparison to previous design] Comparison methodology: the evaluation is limited to the authors' own prior parallel-VCVS design; without reference to independent AJSCC implementations or theoretical power/complexity bounds, it is unclear whether the reported gains are absolute or merely relative to one specific baseline.
minor comments (2)
  1. [Abstract] The abstract would be strengthened by stating at least one concrete power-consumption or transistor-count figure rather than the qualitative statement that the ADB design 'outperforms' the prior version.
  2. [Introduction / circuit description] Notation for AJSCC level count (N) and ADB spacing parameters should be defined explicitly on first use to avoid ambiguity when readers compare the two architectures.

Simulated Author's Rebuttal

3 responses · 1 unresolved

We thank the referee for the constructive comments on our manuscript. We address each major comment below and indicate planned revisions where appropriate.

read point-by-point responses

  1. Referee: [Abstract and simulation results] Abstract and simulation description: the headline claim that the ADB design outperforms the parallel-VCVS design for N >= 16 in both power and complexity rests entirely on LTSpice transient and power simulations; no numerical power values, complexity counts, error bars, or Monte-Carlo statistics are supplied, preventing quantitative assessment of the improvement magnitude.

    Authors: We agree that tabulating explicit numerical values would improve quantitative assessment. The LTSpice results contain specific power and component-count data supporting the N >= 16 claim. In the revision we will add a table reporting these values for multiple N, along with a clarification that the simulations are deterministic transient analyses under nominal conditions and therefore do not include Monte-Carlo statistics or error bars. revision: yes

  2. Referee: [Circuit evaluation] Circuit evaluation section: no corner-case, mismatch, noise, or parasitic-extraction analysis is performed on the ADB or VCVS blocks, even though device variation and finite GBW routinely alter both power draw and the number of distinguishable levels in analog divider circuits; this directly undermines the load-bearing performance comparison.

    Authors: The observation is correct: the presented simulations are nominal and do not incorporate mismatch, noise, or extracted parasitics. This is a genuine limitation of the current simulation study, which focuses on architectural comparison under ideal conditions. We will revise the manuscript to state these assumptions explicitly and note non-ideality analysis as future work; a full corner/mismatch study is outside the scope of this work. revision: partial

  3. Referee: [Comparison to previous design] Comparison methodology: the evaluation is limited to the authors' own prior parallel-VCVS design; without reference to independent AJSCC implementations or theoretical power/complexity bounds, it is unclear whether the reported gains are absolute or merely relative to one specific baseline.

    Authors: The direct comparison is intentional because the contribution is an improvement upon our previously published parallel-VCVS architecture. We will expand the discussion to reference general scaling trends for analog circuit power and complexity with increasing resolution, thereby placing the observed gains in a broader context. Direct numerical comparison to unrelated published AJSCC circuits is difficult owing to differing process nodes and specifications. revision: yes

standing simulated objections not resolved
  • Hardware prototype measurements and full robustness analysis under real device variation, which would require chip fabrication and laboratory testing beyond the simulation-based scope of the manuscript.

Circularity Check

0 steps flagged

No circularity; claims rest on external LTSpice simulation results.

full rationale

The paper introduces an ADB-based AJSCC circuit and compares its simulated power and complexity (via LTSpice) against a prior parallel-VCVS design. No equations, fitted parameters, or uniqueness theorems are present; the performance claims are generated by running an independent simulator on explicit circuit topologies. The reference to 'our previous' design is a simple citation for context and does not substitute for or reduce the simulation evidence. The derivation chain is therefore self-contained against external benchmarks.

Axiom & Free-Parameter Ledger

1 free parameters · 1 axioms · 0 invented entities

The design relies on standard analog circuit assumptions and simulation fidelity; no new physical entities are introduced.

free parameters (1)
  • AJSCC level spacing
    Tunable spacing is a design parameter whose specific values are not detailed in the abstract but affect the claimed performance advantage.
axioms (1)
  • domain assumption LTSpice simulation accurately captures circuit power and complexity
    Evaluation depends entirely on simulation results without hardware confirmation mentioned.

pith-pipeline@v0.9.0 · 5688 in / 1125 out tokens · 119294 ms · 2026-05-25T13:01:03.060656+00:00 · methodology

discussion (0)

Sign in with ORCID, Apple, or X to comment. Anyone can read and Pith papers without signing in.

Reference graph

Works this paper leans on

21 extracted references · 21 canonical work pages

  1. [1]

    Low-power all-analog circuit for rectangular-type analog joint source channel coding,

    X. Zhao, V . Sadhu, and D. Pompili, “Low-power all-analog circuit for rectangular-type analog joint source channel coding,” in IEEE Interna- tional Symposium on Circuits and Systems (ISCAS) , Montreal, Canada, May 2016

    work page 2016

  2. [2]

    Energy-efficient analog sensing for large-scale, high-density persistent wireless monitoring,

    V . Sadhu, X. Zhao, and D. Pompili, “Energy-efficient analog sensing for large-scale, high-density persistent wireless monitoring,” in 13th An- nual Conference on Wireless On-demand Network Systems and Services (WONS), Feb 2017, pp. 61–68

    work page 2017

  3. [3]

    Urban street lighting infrastructure monitoring using a mobile sensor platform,

    S. Kumar, A. Deshpande, S. S. Ho, J. S. Ku, and S. E. Sarma, “Urban street lighting infrastructure monitoring using a mobile sensor platform,” IEEE Sensors Journal, vol. 16, no. 12, pp. 4981–4994, June 2016

    work page 2016

  4. [4]

    A novel wireless sensor network frame for urban transportation,

    X. Hu, L. Yang, and W. Xiong, “A novel wireless sensor network frame for urban transportation,” IEEE Internet of Things Journal , vol. 2, no. 6, pp. 586–595, Dec 2015

    work page 2015

  5. [5]

    Towards low- power wearable wireless sensors for molecular biomarker and physiologi- cal signal monitoring,

    X. Zhao, V . Sadhu, T. Le, D. Pompili, and M. Javanmard, “Towards low- power wearable wireless sensors for molecular biomarker and physiologi- cal signal monitoring,” in IEEE International Symposium on Circuits and Systems (ISCAS), May 2017, pp. 1–4

    work page 2017

  6. [6]

    Self-organizing sensing infrastructure for autonomic management of green datacenters,

    H. Viswanathan, E. K. Lee, and D. Pompili, “Self-organizing sensing infrastructure for autonomic management of green datacenters,” IEEE Network, vol. 25, no. 4, pp. 34–40, July 2011

    work page 2011

  7. [7]

    Underwater acoustic carrier aggrega- tion: Achievable rate and energy-efficiency evaluation,

    X. Zhao, D. Pompili, and J. Alves, “Underwater acoustic carrier aggrega- tion: Achievable rate and energy-efficiency evaluation,” IEEE Journal of Oceanic Engineering, vol. PP, no. 99, pp. 1–14, 2017

    work page 2017

  8. [8]

    Design, implementation, and performance evaluation of a flexible low- latency nanowatt wake-up radio receiver,

    M. Magno, V . Jelicic, B. Srbinovski, V . Bilas, E. Popovici, and L. Benini, “Design, implementation, and performance evaluation of a flexible low- latency nanowatt wake-up radio receiver,” IEEE Transactions on Indus- trial Informatics, vol. 12, no. 2, pp. 633–644, April 2016

    work page 2016

  9. [9]

    Novel adaptive transmission protocol for mobile sensors that improves energy efficiency and removes the limitation of state based adaptive power control protocol (SAPC),

    G. M. D. Basu, G. S. Gupta and X. Gui, “Novel adaptive transmission protocol for mobile sensors that improves energy efficiency and removes the limitation of state based adaptive power control protocol (SAPC),” Journal of Sensor and Actuator Networks , vol. 6, no. 1, 2017

    work page 2017

  10. [10]

    Event driven persistent sensing: Overcoming the energy and lifetime limitations in unattended wireless sensors,

    R. H. Olsson, R. B. Bogoslovov, and C. Gordon, “Event driven persistent sensing: Overcoming the energy and lifetime limitations in unattended wireless sensors,” in IEEE SENSORS, Oct 2016, pp. 1–3

    work page 2016

  11. [11]

    Low-power gas sensing using single walled carbon nano tubes in wearable devices,

    M. Magno, V . Jelicic, K. Chikkadi, C. Roman, C. Hierold, V . Bilas, and L. Benini, “Low-power gas sensing using single walled carbon nano tubes in wearable devices,” IEEE Sensors Journal , vol. 16, no. 23, pp. 8329– 8337, Dec 2016

    work page 2016

  12. [12]

    A 190 nA bias current 10 mV input multistage boost regulator with intermediate-node control to supply RF blocks in self-powered wireless sensors,

    K. Z. Ahmed and S. Mukhopadhyay, “A 190 nA bias current 10 mV input multistage boost regulator with intermediate-node control to supply RF blocks in self-powered wireless sensors,” IEEE Transactions on Power Electronics, vol. 31, no. 2, pp. 1322–1333, Feb 2016

    work page 2016

  13. [13]

    Communication in the presence of noise,

    C. Shannon, “Communication in the presence of noise,” Proceedings of the IRE, 1949

    work page 1949

  14. [14]

    Analog signal compression and multiplexing techniques for healthcare internet of things,

    X. Zhao, V . Sadhu, and D. Pompili, “Analog signal compression and multiplexing techniques for healthcare internet of things,” in 14th Inter- national Conference on Mobile Ad Hoc and Sensor Systems (MASS) , Oct 2017

    work page 2017

  15. [15]

    Using 2:1 Shannon mapping for joint source-channel coding,

    F. Hekland, G. Oien, and T. Ramstad, “Using 2:1 Shannon mapping for joint source-channel coding,” in Data Compression Conference (DCC) , March 2005, pp. 223–232

    work page 2005

  16. [16]

    Evaluation of analog joint source-channel coding systems for mul- tiple access channels,

    O. Fresnedo, J. Gonzalez-Coma, M. Hassanin, L. Castedo, and J. Garcia- Frias, “Evaluation of analog joint source-channel coding systems for mul- tiple access channels,” IEEE Transactions on Communications , vol. 63, no. 6, pp. 2312–2324, June 2015

    work page 2015

  17. [17]

    Spatial diversity using analog joint source channel coding in wireless channels,

    G. Brante, R. Souza, and J. Garcia-Frias, “Spatial diversity using analog joint source channel coding in wireless channels,” IEEE Transactions on Communications, vol. 61, no. 1, pp. 301–311, January 2013

    work page 2013

  18. [18]

    Experimental evaluation of analog joint source-channel coding in indoor environments,

    J. Garcia-Naya, O. Fresnedo, F. Vazquez-Araujo, M. Gonzalez-Lopez, L. Castedo, and J. Garcia-Frias, “Experimental evaluation of analog joint source-channel coding in indoor environments,” in IEEE International Conference on Communications (ICC), June 2011, pp. 1–5

    work page 2011

  19. [19]

    Analog joint source channel coding for wireless optical communications and image transmission,

    S. Romero, M. Hassanin, J. Garcia-Frias, and G. Arce, “Analog joint source channel coding for wireless optical communications and image transmission,” Journal of Lightwave Technology, vol. 32, no. 9, pp. 1654– 1662, May 2014

    work page 2014

  20. [20]

    Device method and system for communicating data,

    D. Stopler, “Device method and system for communicating data,” Jan 2014, US Patent 8,625,709

    work page 2014

  21. [21]

    MT-025 Tutorial,

    Analog Devices, “MT-025 Tutorial,” http://www.analog.com/media/en/ training-seminars/tutorials/MT-025.pdf

    work page