Systolic Sparse Tensor Slices: FPGA Building Blocks for Sparse and Dense AI Acceleration | Paper Citation Record

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This paper cites ASAP7 PDK and Cell Libraries.

Systolic Sparse Tensor Slices: FPGA Building Blocks for Sparse and Dense AI Acceleration ASAP7 PDK and Cell Libraries

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This paper cites Clark, Vinay Vashishtha, Lucian Shifren, Aditya Gujja, Saurabh Sinha, Brian Cline, Chandarasekaran Ramamurthy, and Greg Yeric.

Systolic Sparse Tensor Slices: FPGA Building Blocks for Sparse and Dense AI Acceleration Clark, Vinay Vashishtha, Lucian Shifren, Aditya Gujja, Saurabh Sinha, Brian Cline, Chandarasekaran Ramamurthy, and Greg Yeric

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Systolic Sparse Tensor Slices: FPGA Building Blocks for Sparse and Dense AI Acceleration Unresolved cited work

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This paper cites An Image is Worth 16x16 Words: Transformers for Image Recognition at Scale.

Systolic Sparse Tensor Slices: FPGA Building Blocks for Sparse and Dense AI Acceleration An Image is Worth 16x16 Words: Transformers for Image Recognition at Scale

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Systolic Sparse Tensor Slices: FPGA Building Blocks for Sparse and Dense AI Acceleration Chung, and Greg Stitt

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Systolic Sparse Tensor Slices: FPGA Building Blocks for Sparse and Dense AI Acceleration Horowitz, and William J

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Systolic Sparse Tensor Slices: FPGA Building Blocks for Sparse and Dense AI Acceleration Hughes, Sreenivas Subramoney, Hyesoon Kim, and Tushar Krishna

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Systolic Sparse Tensor Slices: FPGA Building Blocks for Sparse and Dense AI Acceleration Jouppi, Doe Hyun Yoon, Matthew Ashcraft, Mark Gottscho, Thomas B

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Systolic Sparse Tensor Slices: FPGA Building Blocks for Sparse and Dense AI Acceleration In 2021 IEEE High Performance Extreme Computing Conference (HPEC)

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Systolic Sparse Tensor Slices: FPGA Building Blocks for Sparse and Dense AI Acceleration Unresolved cited work

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Systolic Sparse Tensor Slices: FPGA Building Blocks for Sparse and Dense AI Acceleration Sparse Systolic Tensor Array for Efficient CNN Hardware Acceleration

Reference 55

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Systolic Sparse Tensor Slices: FPGA Building Blocks for Sparse and Dense AI Acceleration Whatmough, and Matthew Mattina

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Systolic Sparse Tensor Slices: FPGA Building Blocks for Sparse and Dense AI Acceleration Whatmough, Yuhao Zhu, and Matthew Mattina

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Systolic Sparse Tensor Slices: FPGA Building Blocks for Sparse and Dense AI Acceleration Accelerating Sparse Deep Neural Networks

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Systolic Sparse Tensor Slices: FPGA Building Blocks for Sparse and Dense AI Acceleration Murray, Oleg Petelin, Sheng Zhong, Jia Min Wang, Mohamed Eldafrawy, Jean-Philippe Legault, Eugene Sha, Aaron G

Reference 61

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Reference 66

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Systolic Sparse Tensor Slices: FPGA Building Blocks for Sparse and Dense AI Acceleration Stillmaker and B

Reference 69

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Reference 70

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Reference 71

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Reference 72

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This paper cites Titopoulos, K.

Systolic Sparse Tensor Slices: FPGA Building Blocks for Sparse and Dense AI Acceleration Titopoulos, K

Reference 73

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This paper cites In 2019 IEEE 27th Annual International Symposium on Field- Programmable Custom Computing Machines (FCCM).

Systolic Sparse Tensor Slices: FPGA Building Blocks for Sparse and Dense AI Acceleration In 2019 IEEE 27th Annual International Symposium on Field- Programmable Custom Computing Machines (FCCM)

Reference 74

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Reference 75

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Systolic Sparse Tensor Slices: FPGA Building Blocks for Sparse and Dense AI Acceleration Unresolved cited work

Reference 76

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Observation dfe0659e-8af7-4ac9-a5de-37df108e2f6c · outbound

This paper cites Gomez, Łukasz Kaiser, and Illia Polosukhin.

Systolic Sparse Tensor Slices: FPGA Building Blocks for Sparse and Dense AI Acceleration Gomez, Łukasz Kaiser, and Illia Polosukhin

Reference 77

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Reference 78

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Reference 79

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Reference 81

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Reference 82

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Reference 83

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Reference 84

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Reference 85

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Reference 87

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Reference 88

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Reference 89

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Systolic Sparse Tensor Slices: FPGA Building Blocks for Sparse and Dense AI Acceleration Learning N:M Fine-grained Structured Sparse Neural Networks From Scratch

Reference 90

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Reference 91

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Reference 92

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Reference 98

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Reference 1586

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Systolic Sparse Tensor Slices: FPGA Building Blocks for Sparse and Dense AI Acceleration In 2016 IEEE International Symposium on Workload Characterization (IISWC)

Reference 2016

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Reference 2021

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This paper cites ACM Trans.

Systolic Sparse Tensor Slices: FPGA Building Blocks for Sparse and Dense AI Acceleration ACM Trans

Reference 2022

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This paper cites In2023 IEEE International Symposium on High-Performance Computer Architecture (HPCA).

Systolic Sparse Tensor Slices: FPGA Building Blocks for Sparse and Dense AI Acceleration In2023 IEEE International Symposium on High-Performance Computer Architecture (HPCA)

Reference 2023

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Observation aef1c78c-14d1-4c81-8fb6-8a9385188287 · outbound

This paper cites In 2024 Design, Automation & Test in Europe Con- ference & Exhibition (DATE).

Systolic Sparse Tensor Slices: FPGA Building Blocks for Sparse and Dense AI Acceleration In 2024 Design, Automation & Test in Europe Con- ference & Exhibition (DATE)

Reference 2024

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Outbound references

Pith citing papers