REVIEW 5 major objections 5 minor 38 references
ORACLE: A Multi-Objective Reinforcement Learning-Based Analog Circuit Design Optimizer with Large Language Models-Guided Exploration
T0 review · 5 major / 5 minor · reviewed 2026-08-06 · deepseek-v4-flash
Pith's one-line read ORACLE claims a single preference-conditioned RL agent can size analog circuits to 99.9% of 2,000 target specs with 20-104x less runtime than prior methods.
desk verdict Plausible framework, but the headline pass-rate, FoM, and speedup numbers don't survive contact with the paper's own tables. read the letter →
The pith
A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.
The reading
What carries the argument
The machinery is a preference-conditioned deep double Q-network with vector outputs. The state is (z_t, z*, d_t), the reward is the normalized per-objective deviation of Eq. (4) rather than a scalar combination, and the network predicts Q_theta(s,a,w) in $R^{{|A| x 4}}$. Action selection uses either the cosine score Q_cos = cos(Q, w) * ||Q||_2 (directional alignment times magnitude) or the normalized weighted score Q_NW = w^T Q. Both feed the same DDQN update with target network and replay buffer. The LLM-guided mask of Eq. (10) restricts the action set to A' before simulation, using a local Llama model prompted with the discretized spec gap. The vector reward is the key design choice: it preserves per-objective information through training, so one policy can express many trade-offs.
What would settle it
Train ORACLE on the stated 50 specs, then test on 1,000 held-out specs drawn from the same ranges but with preference vectors sampled randomly instead of the fixed 10. If pass-rate drops well below 99% or average FoM becomes comparable to single-objective AutoCkt, the preference-conditioning generalization claim fails. Separately, run the cosine variant with the LLM mask disabled: if pass-rate and runtime barely change, the LLM component is not carrying the reported 91x FoM gain.
Extended reading notes
Core claim
ORACLE's central claim is that preference-conditioned, vector-valued Q-learning can replace scalar-reward RL for analog sizing. The agent learns Q-values in $R^{4}$, one component per objective (gain, unity-gain bandwidth, phase margin, bias current), trained on 50 target specifications with 10 fixed preference vectors each. At inference, changing the preference vector re-targets the same network to a different trade-off region, producing 10 candidate designs per target spec without retraining. Two scalarization strategies are compared, cosine alignment and normalized weighted sum, and an LLM-based action mask filters actions before simulation. Across 2,000 test problems on a two-stage OPAMP and a three-stage OTA, the authors report 99.9% specification pass, higher Pareto hypervolume than AutoCkt, MODEBI, and ABCMOBO, and runtime reductions of 20.4x to 104.4x.
Load-bearing premise
The method assumes that a policy trained on only 50 target specifications with a fixed set of 10 preference vectors per target will generalize to 1,000 unseen target specifications per topology without retraining, and that the normalized reward makes gain, bandwidth, phase margin, and bias current commensurable so preference-weighted scores reflect real design priorities.
Editorial extensions
If this is right
- A single ORACLE model replaces one-solution-per-retraining workflows: after training, the same network generates ten trade-off designs per target spec by enumerating ten preference vectors.
- On the two benchmark topologies, average optimization runtime drops to 2.4 to 11.6 minutes versus 59.9 to 338 minutes for the compared baselines, enabling design-space exploration at interactive speed.
- The recovered Pareto fronts for each target have higher mean hypervolume than AutoCkt, MODEBI, and ABCMOBO, meaning the method returns a spread of non-dominated designs rather than a single compromise.
- LLM-guided action masking improves both reliability and speed by removing likely-useless actions before simulation, with the cosine+LLM variant raising average FoM from 1.45 to 132.3 on the two-stage OPAMP benchmark.
- Because the implementation is released as open source, the same vector-valued training loop and masking module can be applied to other analog topologies by swapping the simulation environment.
Reading between the lines
- A natural stress test is to hold out entire topologies rather than just target specs: if the Q-function trained on the two-stage OPAMP can seed learning on the three-stage OTA without full retraining, the method would show genuine transfer of analog-sizing knowledge.
- Sampling preference vectors continuously from the simplex, rather than a fixed set of ten, would reveal whether the cosine and NW scalarizations remain well-behaved outside the training distribution of weights.
- The FoM of Eq. (12) is not normalized the same way as the reward of Eq. (4), so the reported 5.1x-318.6x FoM ratios partly depend on how close targets are to the boundary of the spec ranges; recomputing FoM on raw specifications would show how much of the gain is metric-driven.
- The LLM mask's contribution could be isolated with a 2x2 ablation (mask on/off crossed with cosine/NW scalarization); the current tables vary both at once, so the 91x FoM jump attributed to the LLM may be confounded with the scalarization change.
Editorial analysis
A structured set of objections, weighed in public.
Referee Report
Summary. The manuscript presents ORACLE, a multi-objective reinforcement learning framework for analog circuit sizing. The method uses a vector-valued reward and a preference-conditioned double DQN, with two action-selection scalarizations (normalized-weight and cosine-aligned) and an LLM-based action-masking module. The authors report experiments on two topologies with 1,000 target specifications each, claiming a 99.9% pass-rate, 20.4x-104.4x runtime reductions, and 5.1x-318.6x FoM improvements over AutoCKT, MODEBI, and ABCMOBO.
Significance. If the empirical claims held, ORACLE would be a worthwhile contribution to analog design automation: it addresses a real limitation of scalar-reward RL, provides preference-conditioned inference without retraining, and open-sources the framework. The vector-valued Q-learning formulation and the attempt to combine LLM-based design knowledge with RL exploration are timely. The evaluation, however, is currently too inconsistent and asymmetric to support the headline numbers, so the significance of the results is not yet established.
major comments (5)
- [Section IV, Tables I and III] Table I reports ORACLE (Cosine) average FoM as 1.45 on the 1,000 two-stage targets, while Table III reports the same method's average FoM as 107.38 over all 10,000 generated solutions (10 per target). Since Section IV defines the reported FoM for a target as the highest-FoM successful solution among the 10, the per-target maximum cannot be lower than the average over all 10 solutions for the same targets. Unless the two tables use different FoM definitions, one of these numbers is wrong; no explanation is given. This internal inconsistency directly undermines the FoM improvement claims, including the 318.6x figure in the abstract.
- [Abstract and Section IV] The abstract's 99.9% pass-rate over 2,000 specifications is not supported by the tables: Table I gives 100% for ORACLE (Cosine/Cos+LLM/NW) on the two-stage OPAMP and Table V gives 98.4% for ORACLE (Cos+LLM) on the three-stage OTA, so the weighted average is (1000x100% + 1000x98.4%)/2000 = 99.2%. Table III, which reports pass-rates across all 10,000 generated solutions, gives 99.19%-99.80%. The manuscript should state exactly which pass-rate statistic is being reported and correct the 99.9% claim.
- [Section IV, Tables I, IV, V, VIII] The comparison is asymmetric: ORACLE produces 10 solutions per target and is credited with a pass if any of the 10 meets all constraints, while AutoCKT returns exactly one solution. The hypervolume comparison in Tables IV and VIII is therefore between a 10-point front and a single point, which biases the comparison in ORACLE's favor. To support the claimed 5.1x-318.6x FoM improvements, the authors must give AutoCKT (or any single-solution baseline) the same number of attempts, or compare per-solution statistics such as best-of-k with matched k or the distribution of per-solution pass-rates.
- [Section IV-A, Tables II and VII] The runtime comparison is not clearly defined: it is unclear whether the reported runtimes include training, how many runs or seeds were averaged, and whether all methods use the same simulation environment and action space. ORACLE is trained once on 50 target specifications, while the Bayesian baselines and AutoCKT are run per target; if training time is excluded, the comparison is not apples-to-apples. Please specify the measurement protocol and report variance.
- [Section III-D and Section IV-A] The LLM-guided masking module is a central contribution, but the paper does not provide the prompt template, the numerical thresholds for the gap discretization in Eq. (9), or the exact masking rules. Table I attributes a 91x FoM improvement to the LLM integration, yet the reader cannot reproduce or audit this result without these details. Please include them in an appendix or supplement.
minor comments (5)
- [Section III-B, Eq. (4)] The value of the constant epsilon in Eq. (4) is not specified; please provide the actual value used in the experiments.
- [Section III-C] The Q-network output dimension is stated as |A|x4, while the general formulation uses N objectives; please clarify whether N=4 for all experiments or whether the network output is generalized to arbitrary N.
- [Section IV-A] The sentence 'ORACLE meets 100% of the target specifications, representing a 1,011% - 6.6% improvement over the SOTA' is confusing because the range mixes relative improvements from different baselines; please rephrase with explicit per-baseline comparisons.
- [Section IV-A] The sentence 'ORACLE (NW) achieves 302x - 1.17x better top-20 FoM compared to ORACLE (Cosine) and ORACLE (Cosine + LLM), respectively' is grammatically ambiguous; please rewrite to make clear which baseline corresponds to which factor.
- [Figures 3 and 5] The legends and axis labels in Figures 3 and 5 are small and difficult to read; please increase the font size for publication.
Circularity Check
No circular derivation; reported pass-rate, FoM, and runtime are external benchmark outcomes, with only non-load-bearing background self-citations.
full rationale
ORACLE's central claims are empirical measurements on a simulator benchmark (two-stage OPAMP and three-stage OTA) under the paper's own success and FoM definitions. Eq. (4) normalizes per-step rewards by target specifications, and Eq. (12) defines FoM as a sum of target-normalized margins; this is a metric definition, not a fitted parameter renamed as a prediction. Pass-rates and FoMs are computed from simulated output specifications for ORACLE and for the external baselines AutoCKT, MODEBI, and ABCMOBO under the same definitions, so the headline numbers do not reduce to the method's inputs by construction. The preference-conditioned DDQN, cosine scalarization, and DDQN update are attributed to external sources ([14], [23], [34], [35]); the LLM masking module uses an external Llama 3.2 model prompted by specification-gap summaries. Self-citations ([1], [3], [5], [19], [32]) appear only in background or related-work contexts and are not used to justify a uniqueness claim or to supply a load-bearing premise, so they do not constitute circularity. The claim that a policy trained on 50 targets generalizes to 1,000 unseen targets is an empirical assertion, not an equation-level tautology. Separate evaluation concerns, such as the apparent FoM inconsistency between Tables I and III (1.45 vs 107.38 for the same ORACLE Cosine method), the 99.9% headline versus Table I/V pass-rates (100% and 98.4%), and the asymmetric one-solution versus ten-solution comparison with AutoCKT, are correctness or fairness issues, not circularity. No circular step is exhibited, so the circularity score is 0.
Assumptions & free parameters
free parameters (4)
- Reward normalization epsilon =
not specified (> 0)
- Preference vector set =
fixed set of 10 per target
- LLM gap discretization thresholds =
not specified
- Action step sizes =
decrease by 1, no change, increase by 2 (for two-stage); [start, end, increment] arrays
assumptions (4)
- domain assumption The normalized reward in Eq. (4) makes objectives with different scales comparable.
- domain assumption A policy trained on 50 target specifications generalizes to 1,000 unseen target specifications.
- domain assumption The LLM masks only globally harmful actions and never removes beneficial ones.
- standard math The cosine guidance from PD-MORL [14] and DDQN [35] work correctly in the circuit-sizing MDP.
Cite this review
Pith. "Pith review of ORACLE: A Multi-Objective Reinforcement Learning-Based Analog Circuit Design Optimizer with Large Language Models-Guided Exploration." pith.science (2026). https://pith.science/paper/F35G5SYV
@misc{pith2026260804999,
author = {Pith},
title = {Pith review of: ORACLE: A Multi-Objective Reinforcement Learning-Based Analog Circuit Design Optimizer with Large Language Models-Guided Exploration},
year = {2026},
howpublished = {\url{https://pith.science/paper/F35G5SYV}},
note = {Machine review of arXiv:2608.04999}
}
read the original abstract
Analog circuit design automation using reinforcement learning (RL) has emerged as a promising approach for reducing manual effort. However, many existing RL-based methods focus on single-objective optimization. Even methods designed for multi-objective (MO) problems often reduce multiple design specifications to a single scalar reward. This simplification limits the ability to capture the true Pareto trade-off among competing objectives and often leads to suboptimal designs. Moreover, requiring the model to be retrained from scratch whenever the desired MO specifications change remains a key limitation. To address these challenges, we present ORACLE, an open-source RL-based framework for MO analog circuit design optimization that replaces scalar reward optimization with vector-valued learning and preference-aware conditioning. ORACLE represents a true MO analog circuit design optimizer that uses a preference vector to specify the relative weights of multiple objectives, enabling a single trained model to generate designs across diverse trade-off settings without retraining. We further propose two preference-guidance strategies, namely normalized-weight guidance and cosine-aligned guidance, to improve convergence. In addition, we incorporate a large language model (LLM)-guided action selection mechanism to filter actions that are likely to lead to suboptimal designs or increased runtime. Our results show that, on multiple circuit topologies with 2,000 test cases, ORACLE reduces runtime by 20.4x - 104.4x compared to state-of-the-art approaches. It also meets 99.9% of the 2,000 target specifications, and achieves 5.1x - 318.6x better figure of merit in the resulting output specs.
Figures
Figures from the paper (3 more)
Reference graph
Works this paper leans on
-
[1]
M. Fayazi, Z. Colter, E. Afshari, and R. Dreslinski, “Applications of Artificial Intelligence on the Modeling and Optimization for Analog and Mixed-Signal Circuits: A Review,”IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 68, no. 6, pp. 2418–2431, 2021
work page 2021
-
[2]
Analog Design and Machine Learning: A Review,
K. G. Liakos and F. Plessas, “Analog Design and Machine Learning: A Review,”Electronics, vol. 14, no. 17, p. 3541, 2025
work page 2025
-
[3]
M. Fayazi, M. T. Taba, E. Afshari, and R. Dreslinski, “AnGeL: Fully- Automated Analog Circuit Generator Using a Neural Network Assisted Semi-Supervised Learning Approach,”IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 70, no. 11, pp. 4516–4529, 2023
work page 2023
-
[4]
Analog Circuit Sizing Based on Evolutionary Algo- rithms and Deep Learning,
A. Lberniet al., “Analog Circuit Sizing Based on Evolutionary Algo- rithms and Deep Learning,”Expert Systems with Applications, vol. 237, p. 121480, 2024
work page 2024
-
[5]
FASCINET: A Fully Automated Single-Board Computer Generator Using Neural Networks,
M. Fayazi, Z. Colter, Z. Benameur-El Youbi, J. Bagherzadeh, T. Ajayi, and R. Dreslinski, “FASCINET: A Fully Automated Single-Board Computer Generator Using Neural Networks,”IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 41, no. 12, pp. 5435–5448, 2022
work page 2022
-
[6]
Y . Uhlmann, M. Essich, L. Bramlage, J. Scheible, and C. Curio, “Deep Reinforcement Learning for Analog Circuit Sizing with an Electrical De- sign Space and Sparse Rewards,” inProceedings of the 2022 ACM/IEEE Workshop on Machine Learning for CAD, 2022, pp. 21–26
work page 2022
-
[7]
W. Cao, J. Gao, T. Ma, R. Ma, M. Benosman, and X. Zhang, “RoSE- Opt: Robust and Efficient Analog Circuit Parameter Optimization With Knowledge-Infused Reinforcement Learning,”IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 44, no. 2, pp. 627–640, 2024
work page 2024
-
[8]
M. Ahmadzadeh and G. G. Gielen, “Using Probabilistic Model Rollouts to Boost the Sample Efficiency of Reinforcement Learning for Auto- mated Analog Circuit Sizing,” inProceedings of the 61st ACM/IEEE Design Automation Conference, 2024, pp. 1–6
work page 2024
Show all 38 references
-
[9]
PPAAS: PVT and Pareto Aware Analog Sizing via Goal-conditioned Reinforcement Learning,
S. Kim, Z. Wang, S. Lee, Y . Oh, H. Zhu, D. Kim, and D. Z. Pan, “PPAAS: PVT and Pareto Aware Analog Sizing via Goal-conditioned Reinforcement Learning,”arXiv preprint arXiv:2507.17003, 2025
2025 arXiv
-
[10]
A practical Guide to Multi-objective Reinforcement Learning and Planning,
C. F. Hayes, R. R ˘adulescu, E. Bargiacchi, J. K ¨allstr¨om, M. Macfarlane, M. Reymond, T. Verstraeten, L. M. Zintgraf, R. Dazeley, F. Heintz, E. Howley, A. A. Irissappane, P. Mannion, A. Now ´e, G. Ramos, M. Restelli, P. Vamplew, and D. M. Roijers, “A practical Guide to Multi...
2022
-
[11]
Somayaji NS and P
K. Somayaji NS and P. Li, ‘Pareto Optimization of Analog Circuits Us- ing Reinforcement Learning,”ACM Transactions on Design Automation of Electronic Systems, vol. 29, no. 2, p. Article 37, 2024
2024
-
[12]
AutoCkt: Deep Reinforcement Learning of Analog Circuit Designs ,
K. Settaluri, A. Haj-Ali, Q. Huang, K. Hakhamaneshi, and B. Nikolic, “AutoCkt: Deep Reinforcement Learning of Analog Circuit Designs ,” inProceedings of the Design, Automation & Test in Europe Conference (DATE), 2020
2020
-
[13]
A Brief Guide to Multi-Objective Reinforcement Learning and Planning,
C. F. Hayes, R. R ˘adulescu, E. Bargiacchi, J. Kallstrom, M. Macfarlane, M. Reymond, T. Verstraeten, L. M. Zintgraf, R. Dazeley, F. Heintz et al., “A Brief Guide to Multi-Objective Reinforcement Learning and Planning,” inProceedings of the 2023 International Conference on Auto...
2023
-
[14]
PD-MORL: Preference- Driven Multi-Objective Reinforcement Learning Algorithm,
T. Basaklar, S. Gumussoy, and U. Y . Ogras, “PD-MORL: Preference- Driven Multi-Objective Reinforcement Learning Algorithm,” inThe Eleventh International Conference on Learning Representations (ICLR), 2023
2023
-
[15]
K. S. NS and P. Li, ‘Pareto Optimization of Analog Circuits Using Reinforcement Learning ,”ACM Transactions on Design Automation of Electronic Systems, vol. 29, no. 2, pp. 1–14, 2024
2024
-
[16]
RoSE- Opt: Robust and Efficient Analog Circuit Parameter Optimization With Knowledge-Infused Reinforcement Learning,
W. Cao, J. Gao, T. Ma, R. Ma, M. Benosman, and X. Zhang, “RoSE- Opt: Robust and Efficient Analog Circuit Parameter Optimization With Knowledge-Infused Reinforcement Learning,”IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 44, no. 2, pp. 627...
2025
-
[17]
Learning State-Specific Action Masks for Reinforcement Learning,
Z. Wang, X. Li, L. Sun, H. Zhang, H. Liu, and J. Wang, “Learning State-Specific Action Masks for Reinforcement Learning,”Algorithms, vol. 17, no. 2, p. 60, 2024
2024
-
[18]
Robust Circuit Optimization under PVT Variations Via Weight Optimization Problem Reformulation,
J. Li, Y . Li, and Y . Zeng, “Robust Circuit Optimization under PVT Variations Via Weight Optimization Problem Reformulation,”Expert Systems with Applications, vol. 248, p. 123301, 2024
2024
-
[19]
FuNToM: Functional Modeling of RF Circuits Using a Neural Network Assisted Two-Port Analysis Method,
M. Fayazi, M. T. Taba, A. Tabatabavakili, E. Afshari, and R. Dreslinski, “FuNToM: Functional Modeling of RF Circuits Using a Neural Network Assisted Two-Port Analysis Method,” in2023 IEEE/ACM International Conference on Computer Aided Design (ICCAD), 2023, pp. 1–8
2023
-
[20]
Analog Circuits Optimization Based on Evolutionary Computation Techniques,
M. Barros, J. Guilherme, and N. Horta, “Analog Circuits Optimization Based on Evolutionary Computation Techniques,”Integration, the VLSI Journal, vol. 43, no. 1, pp. 136–155, 2010
2010
-
[21]
An Efficient Optimization– Based Technique to Generate Posynomial Performance Models for Analog Integrated Circuits,
W. Daems, G. Gielen, and W. Sansen, “An Efficient Optimization– Based Technique to Generate Posynomial Performance Models for Analog Integrated Circuits,” inProceedings of the 39th annual Design Automation Conference, 2002, pp. 431–436
2002
-
[22]
Genetic Algorithm Software System for Analog Circuit Design,
M. W. Cohen, M. Aga, and T. Weinberg, “Genetic Algorithm Software System for Analog Circuit Design,”Procedia CIRP, vol. 36, pp. 17–22, 2015
2015
-
[23]
Deep Reinforcement Learning with Double Q-Learning,
H. van Hasselt, A. Guez, and D. Silver, “Deep Reinforcement Learning with Double Q-Learning,” inProceedings of the AAAI Conference on Artificial Intelligence, vol. 30, no. 1, 2016
2016
-
[24]
Dynamic Weights in Multi-Objective Deep Reinforcement Learning,
A. Abels, D. M. Roijers, T. Lenaerts, A. Now ´e, and D. Steckelmacher, “Dynamic Weights in Multi-Objective Deep Reinforcement Learning,” in Proceedings of the 36th International Conference on Machine Learning, ser. Proceedings of Machine Learning Research, vol. 97, 2019, pp. 11– 20
2019
-
[25]
A Generalized Al- gorithm for Multi-Objective Reinforcement Learning and Policy Adap- tation,
R. Yang, X. Wang, M. Sun, X. Fang, K. Narasimhan, S. S. Du, M. Hashemi, R. S. Sutton, and D. Schuurmans, “A Generalized Al- gorithm for Multi-Objective Reinforcement Learning and Policy Adap- tation,” inAdvances in Neural Information Processing Systems 32, 2019
2019
-
[26]
Multi-Objective Reinforcement Learning Based on Decomposition: A Taxonomy and Framework,
F. Felten, E.-G. Talbi, and G. Danoy, “Multi-Objective Reinforcement Learning Based on Decomposition: A Taxonomy and Framework,” Journal of Artificial Intelligence Research, vol. 79, pp. 679–723, 2024
2024
-
[27]
Pareto Set Learning for Multi-Objective Reinforcement Learning,
E. Liu, Y .-C. Wu, X. Huang, C. Gao, R.-J. Wang, K. Xue, and C. Qian, “Pareto Set Learning for Multi-Objective Reinforcement Learning,” in Proceedings of the AAAI Conference on Artificial Intelligence, vol. 39, no. 18, 2025, pp. 18 789–18 797
2025
-
[28]
PA2D-MORL: Pareto Ascent Directional Decom- position Based Multi-Objective Reinforcement Learning,
T. Hu and B. Luo, “PA2D-MORL: Pareto Ascent Directional Decom- position Based Multi-Objective Reinforcement Learning,”Proceedings of the AAAI Conference on Artificial Intelligence, vol. 38, no. 11, pp. 12 547–12 555, 2024
2024
-
[29]
Atelier: An Automated Analog Circuit Design Framework via Multiple Large Language Model-Based Agents,
J. Shenet al., “Atelier: An Automated Analog Circuit Design Framework via Multiple Large Language Model-Based Agents,”IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2025
2025
-
[30]
AnalogCoder: Analog Circuit Design via Training-Free Code Generation,
Y . Laiet al., “AnalogCoder: Analog Circuit Design via Training-Free Code Generation,” inProceedings of the AAAI Conference on Artificial Intelligence, vol. 39, no. 1, 2025, pp. 379–387
2025
-
[31]
MuaLLM: A Multimodal Large Language Model Agent for Circuit Design Assistance with Hybrid Contextual Retrieval- Augmented Generation,
P. Abbineniet al., “MuaLLM: A Multimodal Large Language Model Agent for Circuit Design Assistance with Hybrid Contextual Retrieval- Augmented Generation,” in2026 31st Asia and South Pacific Design Automation Conference (ASP-DAC). IEEE, 2026, pp. 646–652
2026
-
[32]
SINA: A Circuit Schematic Image-to-Netlist Generator Using Artificial Intelligence,
S. Aldowaish, Y . Karumanchi, K.-C. Chiang, S. Noorzad, and M. Fayazi, “SINA: A Circuit Schematic Image-to-Netlist Generator Using Artificial Intelligence,”Design, Automation and Test in Europe Conference and Exhibition (DATE), 2026
2026
-
[33]
A taxonomy of Literature Reviews and Experimental Study of Deep Reinforcement Learning in Portfolio Management,
M. Rezaei and H. Nezamabadi-Pour, “A taxonomy of Literature Reviews and Experimental Study of Deep Reinforcement Learning in Portfolio Management,”Artificial Intelligence Review, vol. 58, p. 94, 2025
2025
-
[34]
Human-level control through deep reinforcement learn- ing,
V . Mnihet al., “Human-level control through deep reinforcement learn- ing,”Nature, vol. 518, no. 7540, pp. 529–533, 2015
2015
-
[35]
Deep Reinforcement Learning with Double Q-Learning,
H. van Hasselt, A. Guez, and D. Silver, “Deep Reinforcement Learning with Double Q-Learning,” inProceedings of the AAAI Conference on Artificial Intelligence, vol. 30, no. 1, 2016, pp. 2094–2100
2016
-
[36]
Mastering Diverse Control Tasks through World Models,
D. Hafner, J. Pasukonis, J. Ba, and T. Lillicrap, “Mastering Diverse Control Tasks through World Models,”Nature, vol. 640, pp. 604–610, 2025
2025
-
[37]
Automated Circuit Sizing with Multi-Objective Op- timization Based on Differential Evolution and Bayesian Inference,
C. Vis ¸anet al., “Automated Circuit Sizing with Multi-Objective Op- timization Based on Differential Evolution and Bayesian Inference,” Knowledge-Based Systems, vol. 258, p. 109987, 2022
2022
-
[38]
Asynchronous Batch Constrained Multi-Objective Bayesian Optimization for Analog Circuit Sizing,
X. Zhaoet al., “Asynchronous Batch Constrained Multi-Objective Bayesian Optimization for Analog Circuit Sizing,” in29th Asia and South Pacific Design Automation Conference (ASP-DAC). IEEE, 2024
2024
Reviewed August 6, 2026 · model on record in the stance chip above.
Discussion (0). Continue with ORCID to comment.