Pith. sign in

REVIEW

Not yet reviewed by Pith; the record is open.

This paper has not been read by Pith yet. Machine review is queued; the pith claim, tier, and objections will appear here once it completes.

SPECIMEN: schema-true, not a live event

T0 review · schema-true

One-sentence machine reading of the paper's core claim.

pith:XXXXXXXX · record.json · timestamp

arxiv 2503.21853 v1 pith:FCK6564R submitted 2025-03-27 physics.ins-det hep-ex

Impact of the circuit layout on the charge collection in a monolithic pixel sensor

classification physics.ins-det hep-ex
keywords efficiencyasymmetricchargecircuitcollectionlayoutmonolithicpixel
verification ladder T0 review T1 audit T2 compute T3 formal T4 reserved
0 comments
read the original abstract

CERN's strategic R&D programme on technologies for future experiments recently started investigating the TPSCo 65nm ISC CMOS imaging process for monolithic active pixels sensors for application in high energy physics. In collaboration with the ALICE experiment and other institutes, several prototypes demonstrated excellent performance, qualifying the technology. The Hybrid-to-Monolithic (H2M), a new test-chip produced in the same process but with a larger pixel pitch than previous prototypes, exhibits an unexpected asymmetric efficiency pattern. This contribution describes a simulation procedure combining TCAD, Monte Carlo and circuit simulations to model and understand this effect. It proved able to reproduce measurement results and attribute the asymmetric efficiency drop to a slow charge collection due to low amplitude potential wells created by the circuitry layout and impacting efficiency via ballistic deficit.

discussion (0)

Sign in with ORCID, Apple, or X to comment. Anyone can read and Pith papers without signing in.