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REVIEW 3 major objections 4 minor 17 references

CCAT: Multi-Rate DSP for Sub-mm Astronomy: Polyphase Synthesis Filter Bank on FPGA for Enhanced MKID Readout

T0 review · 3 major / 4 minor · reviewed 2026-08-09 · deepseek-v4-flash

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Pith's one-line read A polyphase synthesis filter bank in FPGA fabric can replace memory look-up tables for MKID bias-tone generation and lift readout bandwidth limits.

desk verdict A real hardware proof-of-concept for polyphase-synthesis-based MKID tone generation, but the paper's claim to meet its own 100 dB SNR spec is contradicted by its measurements. read the letter →

arxiv 2502.00231 v1 pith:FJFPQ4JR submitted 2025-02-01 astro-ph.IM

Ruixuan (Matt) Xie , Adrian K. Sinclair , James Burgoyne , Scott Chapman , Anthony Huber This is my paper · ORCID
classification astro-ph.IM
keywords MKIDreadoutpolyphasesynthesisfilterbankFPGARFSoCfrequencysynthesizersubmillimeterastronomyfrequency-domainmultiplexingtonetracking
verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

This paper demonstrates that a wideband, multi-tone frequency comb for biasing microwave kinetic inductance detectors (MKIDs) can be synthesized inside an FPGA by an overlap-channel polyphase synthesis filter bank (OC-PSB), rather than by reading precomputed waveforms from memory. The authors build this synthesizer on a radio-frequency system-on-chip and measure 2048 simultaneous tones with frequency error below 10 Hz, minimum resolvable spacing of 4 Hz, and single-tone signal-to-noise ratio (SNR) of 92.36 dB at 1 MHz offset on a 256 MHz clock. They argue that the OC-PSB shifts the bandwidth bottleneck from external memory to FPGA resources and, with a factor-of-four parallel datapath, can reach the 1.024 GHz bandwidth that the next-generation 850 GHz camera module requires. If this is correct, warm-side readout electronics no longer limit detector count, and the bias comb can be edited in real time to track drifting detector resonances.

What carries the argument

The load-bearing object is the overlap-channel polyphase synthesis filter bank (OC-PSB), a synthesis filter bank with twice the number of channels and IFFT length of a critically sampled PSB, whose odd-indexed channels are shifted by half a channel spacing through a sign-alternating rotation at the IFFT input. That overlap lets every output frequency be synthesized near a channel center rather than near a channel edge, which keeps image power below -100 dB and relaxes the prototype filter length requirement. The hardware chain is a CORDIC (coordinate-rotation digital computer) in vector-rotation mode generating baseband channel tones in time-division multiplex, a streaming 2048-point IFFT, a reordering buffer that performs periodic extension, and an area-optimized 1024-path polyphase FIR with an overlap-add accumulator. All of this runs at a 256 MHz clock, and the design claims scalability by increasing the parallel factor within the fabric.

What would settle it

Run a loop-back test with the real 850-GHz MKID array at its optimal bias power and measure the on-resonance noise; if the probe tone's contribution exceeds a 5 K equivalent noise temperature, the OC-PSB readout is not detector-limited.

Watch

Extended reading notes

Core claim

The central claim is that an overlap-channel polyphase synthesis filter bank (OC-PSB) can serve as the frequency synthesizer for MKID readout. The OC-PSB uses two interleaved sets of channels, with odd-indexed channels shifted by half a channel spacing, so a probe tone that would land near the steep edge of one channel can instead be synthesized at the center of an adjacent overlapping channel. That placement keeps spectral images below -100 dB while using a prototype filter only a quarter as long as a critically sampled design would need. Implemented with CORDIC baseband generators, a 2048-point IFFT, and a 1024-path polyphase FIR stage, the synthesizer produces 2048 tones across 256 MHz and is claimed to scale by parallelization to the 1.024 GHz, 2048-tone target.

Load-bearing premise

The feasibility claim rests on the assumption that MKID optimal bias tone power is about -90 dBm/Hz and the readout noise floor is about 5 K, so the measured 92.36 dB SNR is enough; if the actual detectors need a stronger bias tone or have a quieter noise floor, the synthesizer would not be detector-noise limited.

Editorial extensions

If this is right

  • The 256 MHz implementation can be scaled to the 1.024 GHz target by running four parallel copies of the same datapath, with no change to the sequence of operations.
  • Real-time tone editing faster than 20 microseconds lets the readout track MKID resonant frequencies that drift due to biasing or atmospheric loading.
  • Because tones placed in the overlapped channels keep spectral images below -100 dB, the prototype filter can be kept short, reducing FPGA resource use.
  • The measured single-tone SNR of 92.36 dB sits near the 16-bit DAC ceiling, so the synthesis scheme itself adds little noise beyond the digital-to-analog conversion.
  • All 2048 channels can be driven simultaneously with equal-spaced tones, giving a full frequency comb with 125 kHz channel spacing at 256 MHz.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

  • If the real 850-GHz detectors need a bias-tone SNR above the measured 92.36 dB, the design would need a higher-resolution DAC or a quieter synthesis path; the paper's 100 dB target is not yet demonstrated end to end.
  • The same overlapping-channel synthesizer could be paired with an analysis filter bank on the same radio-frequency system-on-chip to form a complete transmit-receive readout system, a step the paper leaves for future loop-back testing.
  • The one-tone-per-channel constraint implies detector resonances must be spaced at least one channel spacing apart; arrays with arbitrarily close resonances would need a longer prototype filter or a different synthesis scheme.
  • Because the tone comb is produced by an IFFT, the architecture generalizes naturally to other wideband multi-tone generation tasks beyond MKID readout, such as dense comb generation for communications or quantum-device control.
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Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Referee Report

3 major / 4 minor

Summary. The paper describes the design, FPGA implementation, and laboratory verification of an overlap-channel polyphase synthesis filter bank (OC-PSB) intended to generate the multi-tone AC bias signals for MKID readout in the CCAT/Prime-Cam 850 GHz instrument. The authors derive performance requirements from a noise-stack model, explain the OC-PSB signal-processing structure as an extension of a critically sampled PSB, implement the design on a Xilinx ZCU111 RFSoC using fixed-point 16-bit arithmetic, and report measurements from a spectrum analyzer: 2048 simultaneously generated tones, frequency error below 10 Hz, minimum resolvable frequency spacing of 4 Hz, real-time tone editing, and a single-tone SNR of 92.36 dB at 1 MHz offset on a 256 MHz clock implementation. The paper concludes that the synthesizer meets essential readout requirements and that a parallel-by-4 expansion can reach the 1.024 GHz target bandwidth.

Significance. If the claims are validated, the work is a useful proof of concept: it demonstrates that a polyphase synthesis filter bank, rather than a memory-based look-up table, can generate a wideband frequency comb in FPGA fabric for MKID readout, with real-time reconfigurability and a resource-efficient structure. The strengths of the paper include the concrete, independently measured frequency accuracy and resolution figures, the direct comparison of OC-PSB against critically sampled PSB in simulation, the detailed description of the FPGA dataflow, and the measured 2048-tone comb. The OC-PSB architecture is a standard DSP construction, so the main contribution is the engineering demonstration and the claimed scalability toward 1.024 GHz. That scalability claim and the SNR requirement compliance are, however, not fully supported by the data presented, as detailed below.

major comments (3)
  1. [Section 6; Section 5.1; Section 3, Eqs. (2)-(3)] The conclusion that the synthesizer "meets essential readout requirements such as ... SNR" is internally inconsistent with the measurements and the paper's own specification. Section 5.1 reports a single-tone SNR of 92.36 dB at 1 MHz offset (and 55.23 dB at 10 kHz offset), while Table 1 and Eq. (2) set the SNR requirement at 100 dB. Furthermore, Eq. (3) gives the theoretical maximum SNR of a 16-bit DAC as 98.08 dB, so a 100 dB specification cannot be achieved with the described hardware under any OC-PSB implementation. The authors should either revise the SNR requirement with explicit justification (for example, using a higher noise floor or different bias-power assumption), present a hardware path that can reach the specification, or explicitly acknowledge that the measured SNR falls short and explain why this does not invalidate the feasibility claim. As written, the central claim that the readout SNR requirement is met is contradicted by the paper's own numbers.
  2. [Section 5.1; Section 1; Section 6] The claim that the OC-PSB "successfully lifts the bandwidth limitations of previous LUT-based approaches" is not supported by the demonstrated implementation. The measured bandwidth is 256 MHz, which is half of the 512 MHz baseline quoted for the LUT-based approach in Section 1 and a quarter of the 1.024 GHz target for the 850 GHz module. The parallel-by-4 path to 1.024 GHz is described as an engineering extension, but no resource estimates, timing-closure evidence, or post-place-and-route utilization figures for that configuration are provided. The 1.024 GHz capability should be presented as a projection or design goal, not as a result demonstrated in this work.
  3. [Section 3, Eq. (2); Section 2] The 100 dB SNR requirement is derived from the assumed optimal bias tone power of -90 dBm/Hz and a 5 K noise floor taken from the BLAST-TNG-based noise stack in [6]. These parameters are acknowledged in Section 2 as preliminary and dependent on MKID material and fabrication choices. Because the measured SNR (92.36 dB) is close to the theoretical 16-bit DAC limit, the margin against the 100 dB requirement is small and assumption-dependent. The paper should state over what range of bias powers and noise temperatures the synthesizer would still provide detector-limited readout, or justify why the chosen values are conservative. Without this analysis, a reader cannot determine whether the 7.64 dB shortfall is a fatal specification violation or merely a consequence of a conservative requirement.
minor comments (4)
  1. [Section 2; Section 5] The paper names the Vitis Model Composer version as 2021.1 in Section 2 and as 2020.1 in Section 5; please reconcile this inconsistency.
  2. [Section 5] The phrase "implemented with a bit brasher" appears to be a typographical error for "bit basher" or a similar term; the description of the block shifter would benefit from clarification.
  3. [Section 5.1, Eq. (4)] Equation (4) defines the output frequency, but the symbols are not fully defined in the surrounding text (for example, the factors 1024, 256, and the 500 MHz NCLO shift); a short explanation of the formula would improve readability.
  4. [Section 5.1, Figure 22] The phrase "reduced equal magnitudes" in the caption of Figure 22 is ambiguous; please clarify whether the comb tones have equal magnitudes or intentionally reduced/randomized magnitudes to manage crest factor.

Circularity Check

0 steps flagged · score 0.0 of 10

No significant circularity: OC-PSB is validated against independent spectrum-analyzer measurements and standard PSB theory; the SNR shortfall is an internal consistency issue, not a circular derivation.

full rationale

The derivation is self-contained. The OC-PSB algorithm is constructed as the dual graph of the standard critically sampled polyphase filter bank (Section 4.1, Figs. 6-9) and is validated in Python floating-point simulations, then independently verified on hardware with a Rohde & Schwarz spectrum analyzer (Fig. 19). The measured frequency error (<10 Hz), resolution (4 Hz), and SNR (92.36 dB at 1 MHz) are compared against the requirements in Table 1, not fitted from those same measurements. The only author-overlapping citation is the noise-stack model in [6], used to set the 100 dB SNR target via Eq. (2); that model is a design input based on external BLAST-TNG in-flight values, not a quantity fitted to or derived from the OC-PSB output, so it does not make the central claim circular. One non-circular concern should be explicitly flagged: Section 5.1 reports a single-tone SNR of 92.36 dB, 7.64 dB below the 100 dB requirement, and Eq. (3) caps the ideal 16-bit DAC SNR at 98.08 dB, yet Section 6 concludes that the synthesizer 'meets essential readout requirements such as ... SNR.' This is an internal consistency and correctness issue, not a circularity, and it does not affect the independence of the measured performance validation.

Assumptions & free parameters 4 free parameters · 5 assumptions · 0 invented entities

The OC-PSB design itself is standard DSP, so the ledger is mostly requirements and domain assumptions. The free parameters are the inputs that set the SNR target (-90 dBm/Hz bias power, 5 K noise temperature, 500 Hz resolution) and the chosen filter length; none of these are fitted to the measured output. The key axioms are textbook PSB theory, the MKID resonant-frequency-shift model, the 16-bit DAC SNR bound, the calibratable RFSoC clock offset, and the external noise-stack model. No new physical entities are introduced.

free parameters (4)
  • Optimal bias tone power = -90 dBm/Hz
    Stated in Section 3 as 'a typical optimal bias tone power from previous telescopes.' It sets the SNR requirement via Eq. 2, so the measured SNR of ~92 dB is judged against a target derived from this assumed input, not measured on Prime-Cam detectors.
  • Desired equivalent noise temperature = 5 K
    Used in Eq. 1 to set the noise floor target (-191.6 dBm/Hz) and thus the 100 dB SNR requirement; taken from the noise stack in the authors' prior work [6] based on BLAST-TNG parameters.
  • Minimum frequency resolution requirement = 500 Hz
    Derived from an assumed 0.3 fractional linewidth around resonance; this is a requirement input, not fitted, but it drives the design validation.
  • OC-PSB prototype filter length = 16 x 1024 taps
    Chosen as a trade-off between transition bandwidth and hardware utilization; the overlap design relaxes the filter length relative to the critically sampled case (64 x 1024). It is a design parameter, not fitted to data.
assumptions (5)
  • standard math The M-path polyphase filter bank and its dual synthesis structure are correct and can be extended by doubling channels and IFFT length to form the OC-PSB.
    Sections 4 and 4.1 rely on Crochiere-Rabiner and Harris for PFB/PSB theory; the overlap variant is derived from the even/odd bin-center channelizers in Harris [16].
  • domain assumption An MKID biased near resonance can be modeled as a resonant-frequency shift in S21, and reading out tone power, frequency, and phase encodes sky power.
    Sections 1 and 3 use this model to set the SNR and resolution requirements.
  • standard math A 16-bit DAC gives a best-case SNR of about 98 dB from SNR = 6.02N + 1.76 dB.
    Equation 3 in Section 5 sets the expected noise floor for the measured SNR.
  • domain assumption The RFSoC clock frequency offset is constant during operation and can be calibrated.
    Section 5.1 states the offset is 'likely temperature-related' but treats frequency error as a calibratable constant; no calibration or stability data is presented.
  • domain assumption The noise stack in Fig. 4, based on BLAST-TNG parameters from Sinclair et al. [6], represents the Prime-Cam 850 GHz readout noise floor.
    Section 3 derives the 100 dB SNR requirement from this external model without Prime-Cam detector data.

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Cite this review

Pith. "Pith review of CCAT: Multi-Rate DSP for Sub-mm Astronomy: Polyphase Synthesis Filter Bank on FPGA for Enhanced MKID Readout." pith.science (2026). https://pith.science/paper/FJFPQ4JR

@misc{pith2026250200231,
  author       = {Pith},
  title        = {Pith review of: CCAT: Multi-Rate DSP for Sub-mm Astronomy: Polyphase Synthesis Filter Bank on FPGA for Enhanced MKID Readout},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/FJFPQ4JR}},
  note         = {Machine review of arXiv:2502.00231}
}
read the original abstract

The next-generation mm/sub-mm/far-IR astronomy will in part be enabled by advanced digital signal processing (DSP) techniques. The Prime-Cam instrument of the Fred Young Submillimeter Telescope (FYST), featuring the largest array of submillimeter detectors to date, utilizes a novel overlap-channel polyphase synthesis filter bank (OC-PSB) for the AC biasing of detectors, implemented on a cutting-edge Xilinx Radio Frequency System on Chip (RFSoC). This design departs from traditional waveform look-up-table(LUT) in memory, allowing real-time, dynamic signal generation, enhancing usable bandwidth and dynamic range, and enabling microwave kinetic inductance detector (MKID) tracking for future readout systems. Results show that the OC-PSB upholds critical performance metrics such as signal-to-noise ratio (SNR) while offering additional benefits such as scalability. This paper will discuss DSP design, RFSoC implementation, and laboratory performance, demonstrating OC-PSB's potential in submillimeter-wave astronomy MKID readout systems.

Figures

Figures reproduced from arXiv: 2502.00231 by the authors.

Figure 1
Figure 1. Detector type and count vs. year2 (annotated with the updated anticipated count of Prime-Cam detectors) highest frequency 850-GHz instrument module4 aboard Prime-Cam will have the most demanding detector count and bandwidth which are addressed by the overlap-channel polyphase synthesis filter bank (OC-PSB) synthesizer designed and implemented in this study. MKIDs can be configured as microwave resonators with unique… view at source ↗
Figure 2
Figure 2. MKID transmission with probe/bias tone annotation5 [PITH_FULL_IMAGE:figures/full_fig_p002_2.png] view at source ↗
Figure 4
Figure 4. The effective noise temperature of an MKID in both quadratures, LNA and D/A noise, plotted against the [PITH_FULL_IMAGE:figures/full_fig_p004_4.png] view at source ↗
Figures from the paper (15 more)
Figure 5
Figure 5. Figure 5: OC-PSB Channel frequency response and bias tone placement [PITH_FULL_IMAGE:figures/full_fig_p005_5.png]
Figure 7
Figure 7. Figure 7: Graphical representation of a critically sam [PITH_FULL_IMAGE:figures/full_fig_p006_7.png]
Figure 9
Figure 9. Figure 9: Alternating signs at the odd-indexed IDFT [PITH_FULL_IMAGE:figures/full_fig_p007_9.png]
Figure 11
Figure 11. Figure 11: Output spectrum of the same probe tone synthe [PITH_FULL_IMAGE:figures/full_fig_p007_11.png]
Figure 12
Figure 12. Figure 12: Blue: Channel shape of the critically sam [PITH_FULL_IMAGE:figures/full_fig_p008_12.png]
Figure 14
Figure 14. Figure 14: CORDIC illustra￾tion with unit circle [PITH_FULL_IMAGE:figures/full_fig_p009_14.png]
Figure 16
Figure 16. Figure 16: Standard 3-tap FIR structure(left), area-optimized (right) [PITH_FULL_IMAGE:figures/full_fig_p010_16.png]
Figure 17
Figure 17. Figure 17: 1024-path polyphase filtering stage implementation in Simulink [PITH_FULL_IMAGE:figures/full_fig_p010_17.png]
Figure 18
Figure 18. Figure 18: Result measurement set up, control computer (left), spectrum analyzer (top right), Xilinx ZCU111 development [PITH_FULL_IMAGE:figures/full_fig_p011_18.png]
Figure 19
Figure 19. Figure 19: Python simulation (left) and spectrum analyzer measurement (right) for channel 80, input [PITH_FULL_IMAGE:figures/full_fig_p011_19.png]
Figure 20
Figure 20. Figure 20: Two tones with 256 output bin, or 62.5 kHz spacing measured at RWB = 1Hz a constant offset during operation that can be calibrated. Nonetheless, the synthesizer accuracy (evaluated by measuring the frequency error, defined as the difference between the intended freque…
Figure 21
Figure 21. Figure 21: Measured frequency resolution of the synthesizer [PITH_FULL_IMAGE:figures/full_fig_p012_21.png]
Figure 22
Figure 22. Figure 22: All 2048 channels turned on with equal spaced tones, zoomed in on the right [PITH_FULL_IMAGE:figures/full_fig_p013_22.png]
Figure 23
Figure 23. Figure 23: Left: utilization table; right: utilization graph [PITH_FULL_IMAGE:figures/full_fig_p013_23.png]
Figure 24
Figure 24. Figure 24: Area utilization of key synthesizer components in device logic cell view [PITH_FULL_IMAGE:figures/full_fig_p014_24.png]

Discussion (0). Continue with ORCID to comment.

Reference graph

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