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arxiv: 1907.09631 · v1 · pith:GGTOPSB2new · submitted 2019-07-13 · 🪐 quant-ph · cs.ET

Analysis of Quantum Approximate Optimization Algorithm under Realistic Noise in Superconducting Qubits

Mahabubul Alam , Abdullah Ash-Saki , Swaroop Ghosh This is my paper

Pith reviewed 2026-05-24 21:43 UTC · model grok-4.3

classification 🪐 quant-ph cs.ET
keywords QAOAquantum approximate optimizationsuperconducting qubitsquantum noisegate errorscoherence timeIBM quantum hardwarevariational quantum algorithms
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The pith

Noise from real superconducting qubits limits the useful number of QAOA stages to a hardware-dependent optimum instead of allowing gains from deeper circuits.

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The paper examines how gate errors and finite coherence times affect QAOA performance when the circuit depth parameter p is increased. In ideal theory, larger p is expected to produce better approximation ratios for combinatorial problems. Simulations and runs on an IBM superconducting device show that beyond a modest p, additional stages add more errors than benefit, so solution quality stops improving or declines. The result is that the best p for any given instance is set by the device's error rates and coherence times rather than by the mathematical properties of the problem alone.

Core claim

Analyses in both simulation and on IBM hardware establish that the optimal QAOA depth p is bounded by the noise characteristics of the target device, so that higher-depth circuits do not deliver the monotonic improvement predicted under noiseless conditions.

What carries the argument

Parameterized quantum circuit with p alternating layers of problem and mixer Hamiltonians, whose performance is tracked under realistic gate-error and decoherence models extracted from the IBM device.

If this is right

  • Shallow QAOA circuits can outperform deeper ones on current superconducting hardware.
  • Hardware-specific calibration of p becomes necessary for each device and problem instance.
  • Improvements in coherence time or gate fidelity directly raise the achievable optimal p.
  • Noise-aware compilation or parameter setting must be part of practical QAOA deployment.

Where Pith is reading between the lines

These are editorial extensions of the paper, not claims the author makes directly.

  • Algorithm designers may need to treat p as a tunable resource that trades off against measured hardware error rates rather than a free parameter to maximize.
  • The same noise-limited scaling could apply to other variational algorithms that increase circuit depth to improve expressivity.
  • Device characterization routines could include a quick sweep of QAOA p to identify the hardware's practical depth ceiling before running larger instances.

Load-bearing premise

The noise models fitted from the IBM device capture the main mechanisms that actually limit QAOA scaling with depth.

What would settle it

On hardware with substantially longer coherence times or lower gate errors, QAOA approximation ratio should continue to rise with p beyond the values observed here.

Figures

Figures reproduced from arXiv: 1907.09631 by Abdullah Ash-Saki, Mahabubul Alam, Swaroop Ghosh.

Figure 1
Figure 1. Figure 1: (a) Target Hamiltonian and a variational quantum circuit (Ansatz) [PITH_FULL_IMAGE:figures/full_fig_p001_1.png] view at source ↗
Figure 3
Figure 3. Figure 3: (a) Steps of QAOA for solving combinatorial optimization problems; [PITH_FULL_IMAGE:figures/full_fig_p002_3.png] view at source ↗
Figure 4
Figure 4. Figure 4: (a) Components of QAOA-MaxCut cost and mixing Hamiltonians and their circuit decompositions; (b) MaxCut problem formulation of a two-node, [PITH_FULL_IMAGE:figures/full_fig_p003_4.png] view at source ↗
Figure 5
Figure 5. Figure 5: Infidelity in evolving the system with the cost Hamiltonian due to gate errors. [PITH_FULL_IMAGE:figures/full_fig_p004_5.png] view at source ↗
Figure 7
Figure 7. Figure 7: QAOA solution space for the 4-node 3-regular yutsis graph (a) [PITH_FULL_IMAGE:figures/full_fig_p004_7.png] view at source ↗
Figure 6
Figure 6. Figure 6: Impact of the circuit delay (or depth) on the fidelity of the cost [PITH_FULL_IMAGE:figures/full_fig_p004_6.png] view at source ↗
Figure 8
Figure 8. Figure 8: FOM (1 − r) values of the global optimization procedure with and without noise sources for (a) 4-node random irregular graph, (b) 4-node yutsis, (c) 6-node yutsis, (d) 6-node prism unweighted 3-regular (u3R) graphs; Optimal p-value dependency on the ratio of the cost Hamiltonian execution time and the (e) T1 coherence time, and (f) T2 coherence time for the 6-node yutsis graph. gate-errors are also modeled… view at source ↗
Figure 9
Figure 9. Figure 9: FOM (1 − r) values of the global optimization procedure for the 6-node yutsis graph with (a) two-qubit gate (CNOT) error, (b) single-qubit gate (U2/U3) error, (c) T1, and (d) T2 variations; (e) Optimal p-value dependency on the approximate fidelity of the cost Hamiltonian for the 6-node yutsis graph; (f) approximate fidelity of the cost Hamiltonians with varied number of edges of the problem graphs and two… view at source ↗
Figure 10
Figure 10. Figure 10: FOM (1 − r) values for different problem graphs and p-values on IBMQX4. The coupling graph of IBMQX4 is shown in (a). Optimal p-value was found to be 1 for the graph instances in (c), (d), and (e). For the smallest graph instance, optimal-p value was found to be 2 in (b). larger p-values is most likely dependent on the fidelity of the cost Hamiltonian operation. The approximate fidelity of the cost Hamilt… view at source ↗
read the original abstract

The quantum approximate optimization algorithm (QAOA) is a promising quantum-classical hybrid technique to solve combinatorial optimization problems in near-term gate-based noisy quantum devices. In QAOA, the objective is a function of the quantum state, which itself is a function of the gate parameters of a multi-level parameterized quantum circuit (PQC). A classical optimizer varies the continuous gate parameters to generate distributions (quantum state) with significant support to the optimal solution. Even at the lowest circuit depth, QAOA offers non-trivial provable performance guarantee which is expected to increase with the circuit depth. However, the existing analysis fails to consider non-idealities in the qubit quality i.e., short lifetime and imperfect gate operations in realistic quantum hardware. In this article, we investigate the impact of various noise sources on the performance of QAOA both in simulation and on a real quantum computer from IBM. Our analyses indicate that the optimal number of stages (p-value) for any QAOA instance is limited by the noise characteristics (gate error, coherence time, etc.) of the target hardware as opposed to the current perception that higher-depth QAOA will provide monotonically better performance for a given problem compared to the low-depth implementations.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit. Tearing a paper down is the easy half of reading it; the pith above is the substance, this is the friction.

Referee Report

1 major / 1 minor

Summary. The manuscript analyzes the performance of QAOA on combinatorial optimization problems under realistic noise in superconducting qubits. Using both noisy simulations and runs on IBM hardware, it concludes that the optimal QAOA depth p is bounded by hardware noise parameters (gate errors, coherence times) rather than increasing monotonically with p as often assumed.

Significance. If supported by validated noise modeling, the result would be significant for NISQ-era algorithm design, as it supplies a concrete hardware-dependent limit on useful QAOA depth and explains why deeper circuits can degrade. The dual simulation-plus-hardware approach is a strength when the models are shown to capture the dominant error channels.

major comments (1)
  1. [Abstract and experimental/simulation sections] Abstract and experimental/simulation sections: the central claim attributes the observed non-monotonic p-dependence to hardware noise (gate error, T1/T2) rather than other mechanisms. However, no quantitative match between simulated and measured error rates for the specific QAOA circuits, no error-source decomposition, and no ablation of unmodeled effects (crosstalk, measurement error, or optimizer failure at higher p) are described. This validation gap is load-bearing for the attribution of the finite optimal p to noise characteristics.
minor comments (1)
  1. Specify the exact IBM device, qubit mapping, and the precise noise-parameter values used in the simulations so that the hardware runs can be reproduced.

Simulated Author's Rebuttal

1 responses · 0 unresolved

We thank the referee for the detailed review and the recommendation for major revision. The primary concern is the strength of evidence linking the non-monotonic QAOA performance specifically to the modeled hardware noise parameters. We address this below and outline revisions that will be incorporated.

read point-by-point responses

  1. Referee: [Abstract and experimental/simulation sections] Abstract and experimental/simulation sections: the central claim attributes the observed non-monotonic p-dependence to hardware noise (gate error, T1/T2) rather than other mechanisms. However, no quantitative match between simulated and measured error rates for the specific QAOA circuits, no error-source decomposition, and no ablation of unmodeled effects (crosstalk, measurement error, or optimizer failure at higher p) are described. This validation gap is load-bearing for the attribution of the finite optimal p to noise characteristics.

    Authors: We agree that the manuscript would be strengthened by a more explicit validation of the noise model. The simulations employ the gate-error rates and T1/T2 times reported by the IBM backend for the qubits used in the hardware runs; the non-monotonic p-dependence is reproduced under these parameters and matches the experimental trend. However, the original text does not include a direct quantitative comparison of effective circuit error rates, an error-source decomposition, or an ablation study ruling out crosstalk, measurement error, or classical optimizer degradation at large p. In the revised version we will add (i) a table comparing the input noise parameters to the observed deviation from ideal QAOA performance on hardware, (ii) a brief discussion of dominant channels based on the reported backend metrics, and (iii) an explicit statement of the unmodeled effects that remain possible. These additions will make the attribution more robust while acknowledging the limitations of the current data set. revision: yes

Circularity Check

0 steps flagged

Empirical analysis of QAOA noise effects contains no derivation chain or self-referential steps

full rationale

The paper reports simulation and hardware experiments on IBM devices to observe that QAOA performance does not improve monotonically with circuit depth p due to noise. No equations, fitted parameters, ansatzes, or uniqueness theorems are invoked in the abstract or described claims. The central result is an empirical finding from direct measurement rather than a derivation that reduces to its inputs by construction. Self-citations, if present, are not load-bearing for any mathematical step. This is a standard non-circular empirical study.

Axiom & Free-Parameter Ledger

0 free parameters · 1 axioms · 0 invented entities

The central claim rests on the domain assumption that standard noise models for superconducting qubits are sufficient to predict QAOA scaling behavior; no free parameters or invented entities are mentioned in the abstract.

axioms (1)
  • domain assumption Standard quantum noise models (gate error, decoherence) apply to the superconducting qubits used in the IBM device and simulations.
    The analysis of noise impact presupposes that these models capture the relevant error sources limiting QAOA performance.

pith-pipeline@v0.9.0 · 5747 in / 1238 out tokens · 24719 ms · 2026-05-24T21:43:17.596149+00:00 · methodology

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Reference graph

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