Typed states for the displayed outbound observations.
Source: paper_references, paper_reference_links
Paper Citation Record · LEDGER
RTLRewriter: Methodologies for Large Models aided RTL Code Optimization
As of 7 August 2026, this Paper Citation Record lists 0 of 0 outbound references and 5 inbound Pith citation observations for arXiv:2409.11414.
A citation records a reference. It does not transfer a finding from one paper to another.
Coverage vector
One-hop event checks from named stored sources.
Source: scholarly_work_events, retraction_status_cache, observed 2026-08-07T06:34:17.273281+00:00
Pith citing papers itemized under the disclosed page cap.
Source: paper_references, paper_reference_links, observed 2026-08-07T05:43:46.257689Z
A source-named dated measurement, never combined with another source.
Source: arxiv_reference, observed 2026-05-19T14:42:37.300033Z
Reference resolution
0 of 0 outbound references displayed
- verified exact0
- verified fuzzy0
- unresolved0
- parse uncertain0
- malformed identifier0
- metadata mismatch0
External citation measurements
No source-named external measurement is stored.
Outbound references
No outbound reference observations are available for this paper version.
Pith citing papers
Observation 8db082dd-76ef-4d61-a987-ff36c8bf4fee · inbound
VeriLoC: Line-of-Code Level Prediction of Hardware Design Quality from Verilog Code cites this paper.
VeriLoC: Line-of-Code Level Prediction of Hardware Design Quality from Verilog Code RTLRewriter: Methodologies for Large Models aided RTL Code Optimization
Reference 53
- Resolution
- unresolved
- no resolver link, observed 2026-08-07T05:43:46.257689Z
Source-reported events for the cited work
Unavailable: canonical work link unavailable.
Observation 01bb3927-ee07-4999-b435-5411213d6122 · inbound
DecoRTL: A Run-time Decoding Framework for RTL Code Generation with LLMs cites this paper.
DecoRTL: A Run-time Decoding Framework for RTL Code Generation with LLMs RTLRewriter: Methodologies for Large Models aided RTL Code Optimization
Reference 18
- Resolution
- unresolved
- no resolver link, observed 2026-08-06T20:40:17.127598Z
Source-reported events for the cited work
Unavailable: canonical work link unavailable.
Observation 76c0da57-48eb-4fa2-a721-8012c0959822 · inbound
ChipSeek: Optimizing Verilog Generation via EDA-Integrated Reinforcement Learning cites this paper.
ChipSeek: Optimizing Verilog Generation via EDA-Integrated Reinforcement Learning RTLRewriter: Methodologies for Large Models aided RTL Code Optimization
Reference 32
- Resolution
- verified exact
- arxiv_id, observed 2026-05-19T06:52:08.261925Z
Source-reported events for the cited work
No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.
Observation ad6362d0-0e6e-438e-baef-b3c23f524025 · inbound
RealBench: Benchmarking Verilog Generation Models with Real-World IP Designs cites this paper.
RealBench: Benchmarking Verilog Generation Models with Real-World IP Designs RTLRewriter: Methodologies for Large Models aided RTL Code Optimization
Reference 14
- Resolution
- unresolved
- no resolver link, observed 2026-08-06T15:19:53.025192Z
Source-reported events for the cited work
Unavailable: canonical work link unavailable.
Observation 9886c5b5-a343-445f-ae03-58635c91d9c5 · inbound
RTL-BenchMT: Dynamic Maintenance of RTL Generation Benchmark Through Agent-Assisted Analysis and Revision cites this paper.
RTL-BenchMT: Dynamic Maintenance of RTL Generation Benchmark Through Agent-Assisted Analysis and Revision RTLRewriter: Methodologies for Large Models aided RTL Code Optimization
Reference 17
- Resolution
- verified exact
- arxiv_id, observed 2026-05-19T14:42:37.303419Z
Source-reported events for the cited work
No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.