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arxiv: 2606.21192 · v1 · pith:H3MYRRYKnew · submitted 2026-06-19 · 🪐 quant-ph

Bounded-depth spacetime lattice surgery for resource-efficient fault-tolerant quantum computation

Kou Hamada , Hiroki Hamaguchi , Yosuke Ueno , Yasunari Suzuki , Teruo Tanimoto , Nobuyuki Yoshioka This is my paper

Pith reviewed 2026-06-26 14:33 UTC · model grok-4.3

classification 🪐 quant-ph
keywords lattice surgeryspacetime routingfault-tolerant quantum computingcompilation optimizationquantum error correctionHamiltonian simulationmapping optimization
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The pith

Double-slice routing reduces lattice-surgery compilation cost by up to a factor of 2.4 over single-slice baselines.

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The paper presents double-slice routing as a constant-depth method for spacetime routing in lattice-surgery-based fault-tolerant quantum computation. It employs two consecutive time slices and includes a kink-parity correction that is asserted to terminate under both planar and stacked architectures. This approach addresses the tension between spatial allocation and time-direction exploitation while remaining compatible with inner factory layouts. Benchmarks on Hamiltonian-simulation workloads demonstrate up to 2.4-fold cost reduction versus single-slice routing and smaller circuit volume than projective routing with only marginal time penalty. When paired with cultivation-compatible mapping optimization the total gain reaches 7.5-fold over a naive single-slice baseline.

Core claim

Double-slice routing is a constant-depth spacetime-routing method that uses two consecutive time slices with a guarantee that its kink-parity correction terminates under both planar and stacked architectures. Numerical benchmarks on Hamiltonian-simulation workloads show that double-slice routing reduces compilation cost by up to a factor of 2.4 over a single-slice baseline. Compared to projective routing, an existing method that allows an unbounded number of time slices per path, double-slice routing achieves smaller circuit volume with only a marginal execution-time penalty. Combined with a cultivation-compatible mapping optimization, the overall improvement reaches up to 7.5-fold over a na

What carries the argument

double-slice routing, a bounded-depth spacetime routing technique that employs two consecutive time slices together with kink-parity correction to resolve path conflicts

Load-bearing premise

The kink-parity correction is guaranteed to terminate under both planar and stacked architectures.

What would settle it

A concrete counterexample in which kink-parity correction fails to terminate for a valid path definition under either planar or stacked lattice-surgery architecture would falsify the termination guarantee.

Figures

Figures reproduced from arXiv: 2606.21192 by Hiroki Hamaguchi, Kou Hamada, Nobuyuki Yoshioka, Teruo Tanimoto, Yasunari Suzuki, Yosuke Ueno.

Figure 1
Figure 1. Figure 1: FIG. 1: Schematic diagram of this paper. Double-slice routing is proposed as a spacetime routing method that [PITH_FULL_IMAGE:figures/full_fig_p002_1.png] view at source ↗
Figure 2
Figure 2. Figure 2: FIG. 2: Examples of layouts. In the 2D layout, the data chip consists of a single qubit plane structured as an [PITH_FULL_IMAGE:figures/full_fig_p004_2.png] view at source ↗
Figure 3
Figure 3. Figure 3: FIG. 3: Heatmap of [PITH_FULL_IMAGE:figures/full_fig_p006_3.png] view at source ↗
Figure 4
Figure 4. Figure 4: FIG. 4: Total execution time [PITH_FULL_IMAGE:figures/full_fig_p007_4.png] view at source ↗
Figure 5
Figure 5. Figure 5: FIG. 5: Valid and invalid 3D paths regarding the kink [PITH_FULL_IMAGE:figures/full_fig_p008_5.png] view at source ↗
Figure 6
Figure 6. Figure 6: FIG. 6: Spacetime visualization of three algorithms’ example outputs. [PITH_FULL_IMAGE:figures/full_fig_p010_6.png] view at source ↗
Figure 7
Figure 7. Figure 7: FIG. 7: Illustration of the kink parity correction technique for double-slice routing. Kinks are represented by dark [PITH_FULL_IMAGE:figures/full_fig_p012_7.png] view at source ↗
Figure 8
Figure 8. Figure 8: FIG. 8: Benchmarks of the three routing methods for the SELECT-5 circuit with an outer architecture, evaluated [PITH_FULL_IMAGE:figures/full_fig_p012_8.png] view at source ↗
Figure 9
Figure 9. Figure 9: FIG. 9: Histograms of path volumes for the three [PITH_FULL_IMAGE:figures/full_fig_p013_9.png] view at source ↗
Figure 11
Figure 11. Figure 11: FIG. 11: Scheduling performance of each method evaluated on the circuits simulating the 2D Heisenberg model. [PITH_FULL_IMAGE:figures/full_fig_p015_11.png] view at source ↗
Figure 12
Figure 12. Figure 12: FIG. 12: The floorplans for the surface-code-based architectures. The dark and light patches represent the data [PITH_FULL_IMAGE:figures/full_fig_p021_12.png] view at source ↗
Figure 13
Figure 13. Figure 13: FIG. 13: Influence of magic state preparation time [PITH_FULL_IMAGE:figures/full_fig_p022_13.png] view at source ↗
Figure 14
Figure 14. Figure 14: FIG. 14: Comparison of layouts when SA-based mapping and double-slice routing are applied to the SELECT-6 [PITH_FULL_IMAGE:figures/full_fig_p023_14.png] view at source ↗
Figure 15
Figure 15. Figure 15: FIG. 15: Performance comparison of the four architectures on the Trotter circuit for the 2D Heisenberg model [PITH_FULL_IMAGE:figures/full_fig_p023_15.png] view at source ↗
Figure 16
Figure 16. Figure 16: FIG. 16: Example of omissible voxels in 2.5D layouts. [PITH_FULL_IMAGE:figures/full_fig_p026_16.png] view at source ↗
Figure 17
Figure 17. Figure 17: FIG. 17: Performance breakdown of the three routing algorithms under different factory layouts and [PITH_FULL_IMAGE:figures/full_fig_p029_17.png] view at source ↗
Figure 18
Figure 18. Figure 18: FIG. 18: Mapping evaluation results for Hamiltonians for the part of SELECT circuits in Table [PITH_FULL_IMAGE:figures/full_fig_p030_18.png] view at source ↗
Figure 19
Figure 19. Figure 19: FIG. 19: Visualization of compilation results obtained using the projective and double routing algorithms. We [PITH_FULL_IMAGE:figures/full_fig_p031_19.png] view at source ↗
read the original abstract

Fault-tolerant quantum computing based on lattice surgery requires place-and-route compilation with low spacetime overhead. Routing, in particular, faces a basic tension between suppressing path conflicts through greater spatial allocation and exploiting the time direction to realize ancilla-efficient spacetime routing. Existing approaches do not fully resolve this trade-off while retaining compatibility with inner factory layouts and termination guarantees. Here we introduce double-slice routing, a constant-depth spacetime-routing method that uses two consecutive time slices with a guarantee that its kink-parity correction terminates under both planar and stacked architectures. We numerically benchmark the resulting compiler on Hamiltonian-simulation workloads to show that double-slice routing reduces compilation cost by up to a factor of 2.4 over a single-slice baseline. Compared to projective routing, an existing method that allows an unbounded number of time slices per path, double-slice routing achieves smaller circuit volume with only a marginal execution-time penalty. Combined with a cultivation-compatible mapping optimization, the overall improvement reaches up to 7.5-fold over a naive single-slice compilation baseline. These results identify double-slice routing as a practically useful operating point in lattice-surgery compilation and show the substantial benefit in joint optimization of mapping and routing.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit. Tearing a paper down is the easy half of reading it; the pith above is the substance, this is the friction.

Referee Report

2 major / 1 minor

Summary. The paper introduces double-slice routing, a bounded-depth spacetime lattice-surgery routing method for fault-tolerant quantum computation. It asserts a termination guarantee for the associated kink-parity correction under both planar and stacked architectures, and reports numerical benchmarks on Hamiltonian-simulation workloads showing up to 2.4× reduction in compilation cost versus a single-slice baseline and up to 7.5× overall improvement when combined with cultivation-compatible mapping optimization, while achieving smaller circuit volume than projective routing at modest execution-time cost.

Significance. If the termination guarantee is established with explicit path and primitive conditions and the benchmarks are fully reproducible, the work supplies a concrete, practically useful point in the spatial-temporal trade-off for ancilla-efficient lattice-surgery compilation, with measurable resource savings on relevant workloads.

major comments (2)
  1. [Method definition and termination argument] The termination guarantee for kink-parity correction (asserted in the abstract and the method definition) is load-bearing for the constant-depth claim and all subsequent performance numbers, yet the manuscript supplies no lemmas, explicit path definitions, or conditions on the lattice-surgery primitives that would ensure termination for admissible configurations under planar and stacked architectures.
  2. [Numerical benchmark section] The headline quantitative claims (2.4× and 7.5× compilation-cost reductions) rest on numerical benchmarks whose support cannot be verified from the provided text: no benchmark parameters, error bars, exclusion criteria, or raw data are supplied, undermining assessment of the cross-method comparisons.
minor comments (1)
  1. [Figures] Figure captions should explicitly state the exact baselines (single-slice, projective, naive) and the metric being plotted (e.g., spacetime volume or compilation cost) for each panel.

Simulated Author's Rebuttal

2 responses · 0 unresolved

We thank the referee for the constructive comments. We address each major comment below and will revise the manuscript to incorporate the requested clarifications and details.

read point-by-point responses

  1. Referee: [Method definition and termination argument] The termination guarantee for kink-parity correction (asserted in the abstract and the method definition) is load-bearing for the constant-depth claim and all subsequent performance numbers, yet the manuscript supplies no lemmas, explicit path definitions, or conditions on the lattice-surgery primitives that would ensure termination for admissible configurations under planar and stacked architectures.

    Authors: We agree that the termination guarantee is central to the constant-depth claim and that the current presentation would benefit from greater formality. Although the manuscript asserts the guarantee for both architectures, we acknowledge the lack of explicit lemmas, path definitions, and primitive conditions. In the revised version we will add a dedicated subsection containing: precise definitions of admissible paths and the kink-parity correction procedure; the conditions required on the lattice-surgery primitives; and a termination lemma (with proof sketch) that holds for both planar and stacked architectures. This will directly support the bounded-depth claim. revision: yes

  2. Referee: [Numerical benchmark section] The headline quantitative claims (2.4× and 7.5× compilation-cost reductions) rest on numerical benchmarks whose support cannot be verified from the provided text: no benchmark parameters, error bars, exclusion criteria, or raw data are supplied, undermining assessment of the cross-method comparisons.

    Authors: We concur that the benchmark section lacks the transparency needed for independent verification. The reported speed-ups derive from concrete Hamiltonian-simulation workloads, yet the manuscript omits the necessary parameters. We will expand the numerical results section to include all benchmark parameters (lattice sizes, workload specifications, number of instances), any statistical measures such as error bars, exclusion criteria, and a pointer to a public repository containing the raw data and compilation scripts so that the 2.4× and 7.5× factors can be fully reproduced. revision: yes

Circularity Check

0 steps flagged

No circularity: new construction with external numerical benchmarks

full rationale

The paper introduces double-slice routing as a novel bounded-depth method with explicit termination guarantee under stated architectures, then reports direct numerical comparisons of compilation cost against single-slice and projective baselines on Hamiltonian-simulation workloads. No derivation step reduces a claimed performance gain to a fitted parameter, self-referential definition, or load-bearing self-citation chain; the reported factors (2.4× and 7.5×) are outputs of the compiler runs rather than inputs. The termination claim is asserted as part of the construction rather than derived from prior results by the same authors. The work is therefore self-contained against external benchmarks.

Axiom & Free-Parameter Ledger

0 free parameters · 1 axioms · 1 invented entities

The work rests on standard domain assumptions of lattice surgery and quantum error correction; no explicit free parameters or invented physical entities are described in the abstract.

axioms (1)
  • domain assumption Lattice surgery supports place-and-route compilation with inner factory layouts and termination guarantees under planar and stacked architectures
    The paper builds its routing method on these properties of lattice surgery without deriving them.
invented entities (1)
  • double-slice routing no independent evidence
    purpose: Provide constant-depth spacetime routing with kink-parity correction termination
    New routing construction introduced to resolve the spatial-temporal trade-off

pith-pipeline@v0.9.1-grok · 5754 in / 1381 out tokens · 27876 ms · 2026-06-26T14:33:08.656807+00:00 · methodology

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    Results for Mapping Evaluation We present the numerical results of the mapping evaluation in Fig. 18, using the method described in Sec. G 1. The evaluation was performed on four types of SELECT circuits: Fermi–Hubbard 2D, Z 2 Lattice Gauge 2D, Schwinger, and Random Local. The specific parameters for each Hamiltonian are written in Table V. As discussed i...