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REVIEW 2 major objections 4 minor 17 references

Ternary circuits: why R=3 is not the Optimal Radix for Computation

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Pith's one-line read The claim that radix 3 beats radix 2 fails when per-digit hardware cost is counted.

desk verdict Useful transistor-count tables for ternary vs binary CNTFET circuits, saddled with an overclaimed theoretical refutation that rests on an unproven cost model. read the letter →

arxiv 1908.06841 v1 pith:HWMQPT5A submitted 2019-08-19 cs.AR

Daniel Etiemble This is my paper · ORCID
classification cs.AR
keywords ternarylogicoptimalradixCNTFETtransistorcountmultiple-valuedcircuitsbinaryarithmeticeconomye-radixargument
verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

This paper attacks the long-standing argument that the number e = 2.718, rounded to 3, is the most economical radix for computation. It first shows that the classical cost model C = k R log N / log R omits how much harder each digit is to build at larger radices; adding the number of threshold levels R - 1 as a cost factor makes R = 2 the optimum. It then compares ternary and binary circuits in the same MOSFET-like carbon-nanotube FET (CNTFET) technology, using transistor count as the yardstick and log(3)/log(2) = 1.58 as the information-advantage ratio. Across inverters, NAND gates, adders, multipliers, flip-flops, and SRAM cells, the ternary transistor count is almost always more than 1.58 times the binary count; the only exception is a basic-gate style that needs an extra power supply and suffers a transistor conflict. The paper concludes that ternary arithmetic circuits are always outperformed by binary ones, so the e-radix argument should be abandoned.

What carries the argument

The load-bearing object is the refined cost equation C = k R(R - 1) log N / log R, where R is the radix, N the range to be represented, and R - 1 the number of threshold levels per digit. In the classical equation without the R - 1 factor, the minimum sits near e = 2.718; with the threshold factor, the curve rises with R and the minimum is at R = 2. The circuit comparisons then use a second quantitative tool: the information ratio log(3)/log(2) = 1.58, the maximum factor by which a ternary circuit's transistor count may exceed a binary circuit's and still be competitive. Every ternary design is checked against that ratio, and the decoder/encoder structure needed to implement arbitrary ternary truth tables is what pushes arithmetic circuits far over it.

What would settle it

A CNTFET ternary full adder with a transistor count at or below 1.58 times a binary full adder (roughly 28 transistors if the binary baseline is 18), built without an additional power supply and without a static dc path, would disprove the claim that ternary arithmetic circuits are always outperformed by binary ones.

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Extended reading notes

Core claim

The paper's central claim is that the traditional proof of radix-3 optimality is invalid because it assumes the hardware cost of a digit is independent of how many voltage levels the digit must distinguish. Replacing the digit capacity R by R(R - 1), where R - 1 counts threshold levels, turns the cost curve from one with a minimum near e into one that rises monotonically, making radix 2 optimal. On the circuit side, the paper counts transistors for ternary designs taken from the CNTFET literature and compares them with binary implementations in the same technology. For half adders the ternary version needs 66 transistors versus 9 to 18 for binary; for full adders 124 versus 8 to 36; for a 5x5 ternary multiplier 6190 versus 2382 for an 8x8 binary one. Since the information ratio is only 1.58, any ratio above that means the ternary circuit uses more wires, area, and power, and the paper judges such circuits not competitive. The single three-transistor ternary inverter has a ratio of 1.5, but it achieves that only with an additional power supply and an always-on transistor creating a dc path, so it does not rescue the general claim.

Load-bearing premise

The argument collapses if hardware cost per digit does not actually grow with the number of threshold levels; the R(R - 1) term is assumed, not derived.

Editorial extensions

If this is right

  • If the paper's cost model is right, there is no information-theoretic reason to prefer radix 3, and the classical e-radix argument should stop being cited as a motivation for ternary logic.
  • For arithmetic building blocks in a MOSFET-like CNTFET technology, ternary circuits cannot compensate their transistor overhead by carrying more information per wire.
  • The only ternary designs that meet the 1.58 bound are inverters, NAND gates, flip-flops, and SRAM cells built from the three-transistor inverter style, and those carry two serious drawbacks: an extra power supply and a static dc path.
  • Ternary remains useful for special functions with three natural states, such as content-addressable memory storing 0, 1, and don't-care, but not as a general-purpose replacement for binary computation.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

  • The same threshold-level argument would apply to radix 4 and higher, so the classical equality C(2) = C(4) should not be read as saying binary and quaternary circuits have equal hardware cost.
  • If a ternary arithmetic circuit style could be built with a transistor ratio below 1.58 without an extra power supply or dc path, the paper's 'always outperformed' conclusion would need qualification; the search for such a style is a natural test of how general the result is.
  • Because the overhead comes from decoder/encoder logic and threshold levels rather than from carbon nanotubes specifically, the same conclusion is likely to hold in any technology where binary and ternary gates are built from the same transistor primitives.
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Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Referee Report

2 major / 4 minor

Summary. The paper challenges the widely cited argument that radix e ≈ 2.718 (rounded to 3) is the optimal radix for computation. After reviewing Hurst's cost model C = k R log N / log R, the paper proposes a revised model C = k R (R-1) log N / log R, which makes R = 2 optimal. The bulk of the paper is an empirical comparison of ternary and binary circuits in MOSFET-like CNTFET technology, using published ternary designs, with transistor counts for inverters, NAND gates, half/full adders, multipliers, D flip-flops, and SRAM cells. The paper finds that only the 3-transistor inverter approach of [8] achieves a transistor-count ratio below the information ratio log(3)/log(2) ≈ 1.58, and only for basic gates and inverter-based circuits; arithmetic circuits are claimed to be always outperformed by binary counterparts.

Significance. The empirical transistor-count comparison is a useful and clearly presented data point that quantifies the circuit-level overhead of several published ternary designs relative to binary ones. The observation that the 1.58 information-ratio bound is rarely met is instructive and may be of interest to the multiple-valued logic community. However, the paper's central theoretical claim—that the e-radix demonstration is 'disproved'—rests on an unverified cost-model assumption rather than on a rigorous refutation. The strength of the stated conclusions therefore exceeds what the evidence supports. If the overclaims are softened and the cost model is presented as one plausible hypothesis, the paper could still be a meaningful contribution, but in its current form the central claim is not established.

major comments (2)
  1. [Section II.C, Eq. (2)] The replacement of Hurst's cost model C = k R log N / log R by C = k R (R-1) log N / log R is introduced by the assertion that hardware complexity is proportional to R-1, the number of threshold levels. No derivation from a concrete circuit model is provided, and the factor R-1 is not shown to hold across different gate types, arithmetic structures, or memories. Because the optimum of Eq. (2) is R=2 by construction, the 'disproof' of the e-radix result is not a refutation of Hurst's derivation but a demonstration that a different cost model yields a different optimum. The abstract and conclusion state that the demonstration 'is disproved'; this overstates what the paper actually shows. The contribution should be reframed as a sensitivity analysis of the cost model, or the disproof claim should be removed.
  2. [Section IV.B and IV.C] The comparison of ternary and binary arithmetic circuits uses a single design style for the ternary adders (the decoder/encoder approach from references [6] and [7]) and a single 1-trit multiplier design. The paper does not survey the broader space of published ternary adder and multiplier implementations, which may include pass-transistor or direct gate-level designs with different transistor counts. Consequently, the strong conclusion in the Abstract and Section V that 'for arithmetic circuits such as adders and multipliers, the ternary circuits are always outperformed by the binary ones' is not justified by the evidence presented. The claim should be restricted to the designs actually considered, or the paper should demonstrate that the selected designs are representative of the best available ternary implementations.
minor comments (4)
  1. [Abstract] The phrase 'e=2.718 rounded to 3' is imprecise: Hurst's demonstration concerns the continuous optimum at e, and the rounding to an integer radix is a separate step. Clarify the relationship between the continuous result and the integer radix.
  2. [Table VII] The row 'Ratio 3/2 1 1/3.67 1/7.3' is difficult to parse; the ratios should be written explicitly as 3.67 and 7.3, or as fractions 66/18 and 66/9, to avoid confusion.
  3. [Reference [5]] The URL 'http://dx.doi.org/10;1016/j.mejo.2015.09;018' uses semicolons instead of periods; this appears to be a typographical error.
  4. [Section II.C] The phrase 'Let's assume' should be replaced by a clear statement that Eq. (2) is presented as a hypothesis or alternative cost model, so that the reader immediately understands the conditional nature of the subsequent argument.

Circularity Check

1 steps flagged · score 6.0 of 10

The theoretical refutation of Hurst's e-radix result is forced by the cost model assumed in Eq. (2); the transistor-count comparison is independent but supports only a narrower claim.

  1. self definitional [Section II.C, Equation (2) and Figure 5]
    "Let's assume that the hardware complexity is proportional to R − 1, i.e. the number of threshold levels. The new equation is: C = kR(R − 1) logN/logR ... C=f(R) is continuously rising and the optimal radix is 2."

    The conclusion that the optimal radix is 2 is not derived from independent evidence; it is a direct algebraic consequence of replacing Hurst's per-digit cost R with R(R−1). The only justification offered is 'Let's assume...' plus the observation that one 4-valued inverter needs more thresholds. That example does not establish the global R(R−1) cost law across gates, adders, multipliers, and memories. The paper then presents this consequence as a 'refutation' of Hurst's e-optimality. Since the cost model is chosen so that R=2 minimizes C, the disproof claim reduces by construction to the assumption.

full rationale

The paper contains one clearly circular step: the theoretical 'refutation' of the e-radix result is not a refutation of Hurst's derivation but a replacement of Hurst's cost model with an unproved assumption. Equation (2) substitutes R(R−1) for R, and the optimum immediately becomes R=2. Because the R−1 factor is assumed rather than derived, the headline claim that Hurst's demonstration 'is disproved' reduces to the paper's own chosen input. The transistor-count comparisons in Sections IV are independent and self-contained against external benchmarks: they count transistors in published ternary and binary CNTFET circuits and compare against the 1.58 information ratio. This portion supports the narrower, credible conclusion that the selected ternary arithmetic circuits are not competitive, but it does not mathematically disprove the e-radix optimum. Thus the central theoretical claim is partially circular, while the empirical comparison provides independent content. The self-citations in the paper are not load-bearing: [9] is used for a general decoder-encoder scheme, and [17] is a concluding reference, but neither forces the main conclusion.

Assumptions & free parameters 0 free parameters · 4 assumptions · 0 invented entities

The central negative claim, that ternary circuits are not competitive, rests on two upstream assumptions: the R-1 cost model for the theoretical refutation, and the representativeness of the selected CNTFET ternary designs for the empirical comparison. No new physical entities or fitted numerical parameters are introduced. The constant k in the cost model cancels and is not a free parameter.

assumptions (4)
  • ad hoc to paper Hardware complexity is proportional to R-1, the number of threshold levels.
    Introduced in Section II.C Eq. (2) with 'Let's assume'; no independent derivation is provided. This assumption directly drives the conclusion that the optimal radix is 2.
  • domain assumption Transistor count is an adequate proxy for chip area, power, and interconnects when ratios are large.
    Section III.A states that transistor count 'gives significant insights' and that more transistors likely mean more area, power, and interconnects; the central comparison depends on this.
  • domain assumption The cited CNTFET ternary circuits are representative of the ternary approach.
    Section IV selects designs from references [5], [6], [7], and [8]; the paper does not survey optimized ternary adders or multipliers beyond these specific designs.
  • standard math Standard calculus and logarithm properties for minimizing cost functions.
    Used in Section II to differentiate C with respect to R when locating the minimum of the cost function.

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Cite this review

Pith. "Pith review of Ternary circuits: why R=3 is not the Optimal Radix for Computation." pith.science (2026). https://pith.science/paper/HWMQPT5A

@misc{pith2026190806841,
  author       = {Pith},
  title        = {Pith review of: Ternary circuits: why R=3 is not the Optimal Radix for Computation},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/HWMQPT5A}},
  note         = {Machine review of arXiv:1908.06841}
}
read the original abstract

A demonstration that e=2.718 rounded to 3 is the best radix for computation is disproved. The MOSFET-like CNTFET technology is used to compare inverters, Nand, adders, multipliers, D Flip-Flops and SRAM cells. The transistor count ratio between ternary and binary circuits is generally greater than the log(3)/log(2) information ratio. The only exceptions concern a circuit approach that combines two circuit drawbacks (an additional power supply and a circuit conflict between transistors) and only when it implements circuits based on the ternary inverter. For arithmetic circuits such as adders and multipliers, the ternary circuits are always outperformed by the binary ones using the same technology.

Figures

Figures reproduced from arXiv: 1908.06841 by the authors.

Figure 1
Figure 1. CMOS technological nodes The interconnection argument raises another question. It is quite evident that ternary operators have less input and output connections than the corresponding binary ones. The reduction factor corresponds to log(3)/log(2) = 1.58, which is the ratio between information transmitted by ternary and binary wires. Typical values are shown in Table I. For 64 bits, there are 36% less wires with tern… view at source ↗
Figure 2
Figure 2. shows that the curve complexity = f(R) for radixes 2 to 16 presents a minimum close to R = 3 [PITH_FULL_IMAGE:figures/full_fig_p002_2.png] view at source ↗
Figure 4
Figure 4. presents a 4-valued CNTFET inverter that has been presented in Microelectronics Journal in 2015 [5]. At that point in the discussion, there is no need to give details on the CNTFET technology as we compare transistor counts in the same technology. A 4-valued inverter carries 2 bits of information. Two binary inverters also carry 2 bits of information and use 2×2 = 4 transistors. The 4-valued inverter has 10 transist… view at source ↗
Figures from the paper (14 more)
Figure 5
Figure 5. Figure 5: New hardware system complexity [PITH_FULL_IMAGE:figures/full_fig_p003_5.png]
Figure 7
Figure 7. Figure 7: 2-input Nand gates proposed in [5] and [6] [PITH_FULL_IMAGE:figures/full_fig_p004_7.png]
Figure 6
Figure 6. Figure 6: Ternary inverters proposed in [5], [8], [6] [PITH_FULL_IMAGE:figures/full_fig_p004_6.png]
Figure 8
Figure 8. Figure 8: General scheme of m-valued circuits. TABLE V TRUTH TABLE FOR TERNARY TO BINARY DECODER A A1 A1 A0 A0 0 2 0 2 0 1 2 0 0 2 2 0 2 0 2 4 [PITH_FULL_IMAGE:figures/full_fig_p004_8.png]
Figure 9
Figure 9. Figure 9: Decoder and encoder circuits [7] [PITH_FULL_IMAGE:figures/full_fig_p005_9.png]
Figure 10
Figure 10. Figure 10: Sum binary parts [PITH_FULL_IMAGE:figures/full_fig_p005_10.png]
Figure 11
Figure 11. Figure 11: Carry generation [PITH_FULL_IMAGE:figures/full_fig_p005_11.png]
Figure 12
Figure 12. Figure 12: Binary half adders. 5 [PITH_FULL_IMAGE:figures/full_fig_p005_12.png]
Figure 13
Figure 13. Figure 13: CNTFET 3T Xor TABLE VII TRANSISTOR COUNTS AND RATIOS FOR TERNARY AND BINARY HALF ADDERS 3-HA 2-HA without Xor 2- HA with Xor Counts 66 18 9 Ratio 3/2 1 1/3.67 1/7.3 transistor counts of the ternary and binary versions are given in Table VII together with the transisto…
Figure 14
Figure 14. Figure 14: Binary full adders [PITH_FULL_IMAGE:figures/full_fig_p007_14.png]
Figure 15
Figure 15. Figure 15: 8T binary full adder Using the same approach as for the adder, the equations are: S2 = A1.B1.B0 + B1.A1.A0 (14) S1 = A1.B1 + B1.B0.A1.A0 (15) Cm = A1.B1 (16) The number of transistors is 4 (decoder)+ 12 (S1) + 12 (S2) + 6 (s encoder) + 4 (cout encoder) = 38. The binar…
Figure 16
Figure 16. Figure 16: Wallace trees for 5x5 ternary (left) and 8x8 binary (right) multipliers [PITH_FULL_IMAGE:figures/full_fig_p007_16.png]
Figure 17
Figure 17. Figure 17: Ternary D-Flip-Flop SRAMs use static cells. There are several possible im￾plementations of the memory cell. We consider the simplest ternary cell derived from the classical 6-T binary cell ( [PITH_FULL_IMAGE:figures/full_fig_p008_17.png]
Figure 18
Figure 18. Figure 18: Ternary Memory Cell from [8] While Flip-Flops and Static Rams are based on the logic gates that are used to implement combinational operators, Dynamic Rams are based on electrical features instead of logical ones. Binary DRAMs use electrical charges to store bits in 1…

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Reference graph

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