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REVIEW 4 major objections 6 minor 27 references

Dryas: A Reprogrammable Engine for High-Speed Interconnect Tracing and Analysis

T0 review · 4 major / 6 minor · reviewed 2026-08-15 · deepseek-v4-flash

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Pith's one-line read Dryas claims that a small, runtime-reprogrammable NFA overlay can trace and filter a 30 GiB/s cache-coherent interconnect at line rate using only a few percent of the FPGA's logic, and can swap filters in under a second without stopping…

desk verdict Dryas is a credible, genuinely useful FPGA tracing engine with a new overlay-NFA design, but its headline claims about line rate and sub-second reconfiguration are supported only by synthesis numbers and untimed assumptions, so the paper should be accepted conditionally after the authors measure what they assert. read the letter →

arxiv 2608.12934 v1 pith:I6EUXVBB submitted 2026-08-13 cs.AR eess.SP

Manuel Bröchin , Tom Kuchler , Michael Giardino , David Cock , Timothy Roscoe This is my paper · ORCID
classification cs.AReess.SP
keywords FPGAtracinginterconnectanalysisNFAfilteringoverlayarchitectureruntimereconfigurationcachecoherenceline-ratestatetransitionelements
verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

This paper presents Dryas, a runtime-reprogrammable filter engine that taps into a 30 GiB/s cache-coherent CPU-FPGA interconnect and extracts specific message sequences at cache-line granularity, at full line rate. The central claim is that an NFA implemented as an overlay of state transition elements can express complex, protocol-level filters while consuming only a few percent of the FPGA's logic, and that the filters can be swapped in under a second without stopping the running application or resynthesizing the design. Such a tool matters because debugging and analyzing modern high-speed interconnects usually means capturing hundreds of gigabytes of traces or using limited hardware debuggers; Dryas aims to provide live, fine-grained visibility into protocol behavior and application memory patterns with negligible overhead. The paper evaluates scalability and shows two case studies: tracing cross-socket latency through the block and virtual-channel layers, and characterizing cache misses by type for a tree-walking workload.

What carries the argument

The central object is the rings-of-cliques (RoC) overlay graph: a static, parameterized network of state transition elements (STEs) defined by clique size, ring length, ring count, and neighbor-ring count, which at synthesis time trades off the number of NFA states against the connectivity available for transitions. Each STE implements one state of a homogeneous NFA and is runtime-configurable through its input-decoding lookup tables, its start/accept registers, and the enabled links to neighboring STEs, so a new filter is loaded by shifting a configuration bitstream through the overlay rather than by rebuilding the FPGA design. The input decoding computes arbitrary logic functions on the small set of predicates extracted from message headers, and a separate integer-program formulation maps NFA states to STEs, with the mapping solved by a standard IP solver.

What would settle it

Measure the end-to-end reconfiguration time on the test platform — from issuing a new filter over PCIe to the moment the new NFA is active — including the integer-program mapping time, for the largest filter described (the 7-state, fan-in-6 cache-miss classifier with 24 or 32 substreams); if that time reaches one second or more, the sub-second reconfiguration claim fails. A complementary test is to toggle filters repeatedly while the interconnect is running at full rate and check that no message is dropped or stalled during the switch.

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Extended reading notes

Core claim

Dryas claims that a non-deterministic finite automaton (NFA) built from runtime-configurable state transition elements (STEs), wired in a static rings-of-cliques overlay graph on an FPGA, can filter a 30 GiB/s cache-coherent interconnect at full line rate while consuming only a few percent of the device's logic. The engine works by reducing each incoming or outgoing message to a small set of predicates over its header (type, virtual channel, opcode, address, direction), feeding those predicates to the NFA, and emitting only messages that trigger an accepting state. Because the STEs' lookup tables, start/accept registers, and inter-STE routing are all runtime-configurable, a new filter can be loaded in under a second by shifting a configuration bitstream through the overlay, with no FPGA re-synthesis and no interruption to the running application. The paper demonstrates this on a real coherent CPU-FPGA system with two uses: measuring cross-socket memory latency at the protocol layer, and classifying cache misses into compulsory, capacity/conflict, and coherence misses per cache line.

Load-bearing premise

The claim that filters can be swapped in under a second rests on the unmeasured assumption that the integer-program mapping from a filter's NFA to the rings-of-cliques overlay completes in well under a second for every practical filter size and connectivity.

Editorial extensions

If this is right

  • Dryas can be deployed alongside a large FPGA application and still trace the interconnect at full rate, since a 600-state configuration uses under 2.2% of the LUTs and 3.7% of the flip-flops of the target device.
  • Filters can be changed in under a second at runtime, without reprogramming the FPGA or stopping the running application, enabling interactive debugging of a live system.
  • The same overlay engine can be specialized to different protocol layers or different interconnects by changing only the synthesis-time predicate extraction, leaving the NFA engine itself protocol-agnostic.
  • In the evaluated scenarios Dryas reduces trace volume by a factor of over 10^5 (1.2 TiB of raw blocks down to a manageable filtered trace), cutting post-processing time correspondingly.
  • Because the overlay can be replicated or de-multiplexed onto substreams, Dryas can track per-cache-line state independently, as used to classify compulsory, capacity/conflict, and coherence misses.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

  • The 'under a second' reconfiguration claim is only as strong as the integer-program solver that maps an NFA onto the overlay; the paper does not report this mapping time, so a full filter-swap time budget for larger filters remains an open measurement (the weakest point of the paper).
  • The predicate-extraction front end is the only protocol-specific part, so the same overlay engine could plausibly filter other high-speed serial links (PCIe, CXL, Ethernet) by changing the header-reduction logic; this is an extension the paper does not itself demonstrate.
  • The engine's ability to observe interleaved substreams suggests a natural next use as a live coherence-protocol verifier, flagging protocol violations or deadlock conditions the moment they occur, rather than only filtering known patterns offline.
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Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Referee Report

4 major / 6 minor

Summary. The paper presents Dryas, an FPGA overlay-based engine for tracing and filtering messages on Enzian's 30 GiB/s cache-coherent ECI interconnect. The engine extracts protocol-specific predicates from message headers, feeds them into a runtime-reconfigurable NFA built from state transition elements (STEs) arranged in a rings-of-cliques overlay graph, and emits only messages that lead to accepting states. The authors claim line-rate filtering on their test system, sub-second filter reconfiguration without stopping the application, and low resource usage. The evaluation reports synthesis-based resource scaling for various overlay sizes, then demonstrates two use cases: cross-socket memory latency analysis at block and VC layers, and cache-miss classification of a binary-tree workload using multiple CL-partitioned substreams.

Significance. If the headline claims hold, Dryas would be a genuinely useful open-source tool for live debugging and analysis of high-speed cache-coherent interconnects, with a rare combination of low hardware overhead, complex pattern matching, and runtime reconfigurability. The paper has several strengths: the rings-of-cliques overlay is a clear and parametrizable design; the mapping problem is honestly formulated as an NP-complete subgraph isomorphism and solved via standard IP solvers without fitted parameters; the two use cases are nontrivial and produce plausible traces; and the claimed resource usage is small enough to coexist with real applications. However, the two most important claims—sustained 30 GiB/s line rate and sub-second end-to-end reconfiguration—are never directly measured. The paper therefore, as written, provides a convincing architecture description but not a convincing experimental validation of its central performance promises.

major comments (4)
  1. [§5.1, Abstract, §1] The claim that Dryas filters data at 30 GiB/s line rate is not supported by direct measurement. Section 5.1 reports only synthesis resource usage (LUTs and FFs) and timing-closure of maximal configurations; Sections 5.2 and 5.3 show traces but report no achieved throughput, no input-versus-output message counts, no dropped-message counters, and no comparison showing that filtering preserves all messages that should be preserved. Please add an explicit line-rate experiment (for example, count blocks/messages at the input and at the filter output over a sustained run, and report equality or loss rates) or weaken the abstract and introduction to claim only that the design is intended for line rate.
  2. [§3.1, Abstract, §1] The sub-second reconfiguration claim rests on the IP-based subgraph mapping completing quickly, but no mapping time is ever reported. Section 3.1 states that 'mapping can easily be performed as a standard IP formulation,' but Section 5 never times the IP solve, the CFGLUT5 configuration shifting, or the register updates for any of the filters used in the evaluation. Since the abstract and introduction promise filter changes 'in less than a second,' please provide end-to-end reconfiguration measurements for realistic filters and overlay sizes, and report the solver used and the observed solve times.
  3. [§5.2] The latency analysis reports averages of 0.135 μs at the VC layer and 5.2 μs at the block layer, and infers a '40x difference' and congestion effects, but no variance, distribution, sample count, or measurement method is given. Averages without spread are insufficient to support the conclusion that most of the latency is due to FPGA VC-layer serialization. Please report the latency distributions (e.g., percentiles or histograms) and the number of request-response pairs used.
  4. [§5.2, §5.3] No false-negative or false-positive rate is reported for the filter engine. For a tool whose purpose is to find rare and transient events, silent message loss would invalidate both use cases. The paper shows that the filter reduces trace volume by over 10^5 in Section 5.2, but that reduction is not evidence that no interesting messages were dropped. Please quantify filter accuracy—for example, by comparing filtered output against a full trace in a short experiment, or by injecting known marker messages and confirming they are always emitted.
minor comments (6)
  1. [§5.1] The sentence 'Dryas has a fixed base cost of Dryas accounts for about 20k LUTs and 29k FFs' is grammatically broken and should be rewritten.
  2. [§5.1, Figure 8] In the text describing Figure 8, the phrases 'increasing' and 'increasing' are missing the RoC parameter symbols (C, L, R, or N) that are being varied; please insert the actual parameter names.
  3. [§3.2] In the final paragraph of Section 3.2, the substream count appears as an empty symbol in phrases like 'activations are received' and 'some of the signals are now -bit buses'; the symbol (likely K) is missing.
  4. [§2.1] There are typos in Section 2.1: 'indentified' should be 'identified', and in Section 1 'gigabyes' should be 'gigabytes'.
  5. [§5.3] The overlay is synthesized to trace 32 substreams, while the stated requirement is 24 substreams for the 24 CLs of the binary search tree; please explain the choice of 32 (e.g., power-of-two alignment) and confirm that the 8 unused substreams are disabled.
  6. [Abstract and §5.2] The paper says Dryas is open source, but no repository URL or artifact availability statement is provided; please add one.

Circularity Check

0 steps flagged · score 0.0 of 10

No circularity found: Dryas reports measured synthesis resource usage and protocol trace examples, with self-citations only as domain grounding.

full rationale

The paper makes no derived numerical predictions or fitted parameters that could be circular. Its central claims are (a) an STE-overlay NFA filter can be mapped and reconfigured at runtime, (b) resource usage scales linearly with overlay parameters, and (c) two example filters extract protocol-level traces. Each claim is supported by either synthesis resource counts (Section 5.1), FPGA trace examples (Sections 5.2 and 5.3), or a standard NFA/hNFA construction (Sections 2.2 and 3.2). The hNFA-to-STE mapping uses the well-known NP-complete subgraph mapping problem; invoking standard IP solvers is an implementation choice, not a prediction derived from its own outputs. The self-citations to prior Enzian/ECI work ([6], [17], [21]) supply the protocol headers and semantics being traced; they are domain grounding rather than load-bearing circular justification, and no uniqueness theorem or ansatz is smuggled in through those citations. The unmeasured end-to-end reconfiguration time and the absence of measured drop-free line-rate throughput are evidentiary gaps, not definitional circularity. Accordingly no circular step rises to the standard of Eq. X = Eq. Y by construction or a fitted parameter renamed as a prediction.

Assumptions & free parameters 0 free parameters · 5 assumptions · 1 invented entities

Dryas is an engineering artifact built on standard automata theory and FPGA primitives. No parameters are fitted to data; the user-chosen values are overlay graph dimensions and substream counts, which are design parameters, not fitted constants. The main assumptions are the NFA-to-hNFA equivalence, the semantics of input validity, the correctness of the CFGLUT primitive, and the ECI protocol specifications from prior self-cited work.

assumptions (5)
  • standard math Any NFA can be converted to a homogeneous NFA by duplicating states
    Section 2.2 uses this to let each STE check a single transition function; it is a standard automata theory result.
  • domain assumption The 'valid input' signal reliably indicates cycles that should affect state, so a state deactivates only when valid input arrives but no transition matches
    Section 3.2 introduces a de-activation rule unique to Dryas; if the valid signal does not align with protocol-level idle, filters will drop or freeze events.
  • domain assumption The CFGLUT5 primitive implements an arbitrary 5-bit lookup and can be reconfigured at runtime as described
    Section 3.2 relies on Xilinx UltraScale+ primitives and assumes the documented behavior and timing closure.
  • domain assumption ECI block and VC header semantics are as defined in prior self-cited work
    Section 2.1 and the use cases in Section 5 rely on message types, VC numbering, and coherency protocol behavior from references [17] and [21].
  • domain assumption Subgraph mapping is solved correctly by an IP solver, and the rings-of-cliques graph can embed the required hNFAs
    Section 3.1 states that expressiveness is limited by overlay connectivity, but no proof is given that all practical filters are embeddable. Mapping success is only shown implicitly through the two use cases.
invented entities (1)
  • Rings-of-cliques (RoC) overlay graph independent evidence
    purpose: Static STE interconnection that trades off number of states against connectivity, configurable at runtime to implement different homogeneous NFAs
    Introduced in Section 3.1 and realized in hardware; synthesis and timing results in Section 5.1 for multiple configurations provide evidence beyond the prose.

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Cite this review

Pith. "Pith review of Dryas: A Reprogrammable Engine for High-Speed Interconnect Tracing and Analysis." pith.science (2026). https://pith.science/paper/I6EUXVBB

@misc{pith2026260812934,
  author       = {Pith},
  title        = {Pith review of: Dryas: A Reprogrammable Engine for High-Speed Interconnect Tracing and Analysis},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/I6EUXVBB}},
  note         = {Machine review of arXiv:2608.12934}
}
read the original abstract

The proliferation of heterogeneous components in modern computing systems has been accompanied by new higher bandwidth and lower latency interconnects. These interfaces and protocols are enormously complex and the process of developing, debugging, and analyzing FPGA-based implementations requires significant engineering work. Moreover, once a functional implementation is completed, optimization of the controller and associated software requires processing potentially hundreds of gigabytes of trace data. In this paper, we present Dryas, an open source tool for analyzing such an interconnect. We developed our tool, using minimal hardware resources, alongside an FPGA implementation of a very high speed, low latency (30~GiB/s, 200~ns) interconnect. With our run-time reprogrammable overlay engine we can inspect this interconnect to find rare, complex, or transient events even at full operation. This filtering engine is based on non-deterministic finite automata (NFAs), efficiently implemented using state transition elements (STEs), allowing us to trace events at a cache-line granularity. Moreover we can change the filters in less than a second, without reprogramming the FPGA or interfering with the running application. This data enables not only debugging the implementation of the interconnect itself, but analyzing the behavior of accelerated applications. We examine the mathematical basis for using NFAs and describe their implementation on a real coherent CPU-FPGA research platform. We then evaluate the scalability of Dryas for various size NFAs, followed by two different use cases: debugging FPGA implementation of the interconnect and analyzing cache behavior.

Figures

Figures reproduced from arXiv: 2608.12934 by the authors.

Figure 1
Figure 1. The four types of block layer headers: sync, [PITH_FULL_IMAGE:figures/full_fig_p002_1.png] view at source ↗
Figure 2
Figure 2. The NFA is graphically depicted on the left. In [PITH_FULL_IMAGE:figures/full_fig_p003_2.png] view at source ↗
Figure 3
Figure 3. Correspondence between general NFA and ho [PITH_FULL_IMAGE:figures/full_fig_p004_3.png] view at source ↗
Figures from the paper (6 more)
Figure 4
Figure 4. Figure 4: Various configurations (C,L,R,N) of the rings-of-cliques overlay graph. [PITH_FULL_IMAGE:figures/full_fig_p006_4.png]
Figure 5
Figure 5. Figure 5: Logic diagram of a single STE with 4 predecessor STEs. message headers are matched depends on the protocol and use case. Moreover, we often want to aggregate the outputs of different CFGLUT5s in order to represent more complex transition functions. We will discuss two …
Figure 6
Figure 6. Figure 6: Data reduction performed at the block layer [PITH_FULL_IMAGE:figures/full_fig_p007_6.png]
Figure 8
Figure 8. Figure 8: Hardware cost of Dryas measured in Look-Up Tables (LUTs) and flip-flops (FFs) when increasing number of [PITH_FULL_IMAGE:figures/full_fig_p009_8.png]
Figure 10
Figure 10. Figure 10: Memory transactions at the FPGA block layer [PITH_FULL_IMAGE:figures/full_fig_p009_10.png]
Figure 12
Figure 12. Figure 12: Top: heatplot of the number of cache misses [PITH_FULL_IMAGE:figures/full_fig_p010_12.png]

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