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REVIEW 4 major objections 5 minor 13 references

OASIS-UROS: Open Acquisition System for IEPE Sensors -- Upgraded, Refined, and Overhauled Software

T0 review · 4 major / 5 minor · reviewed 2026-08-12 · deepseek-v4-flash

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Pith's one-line read Open-source DAQ matches commercial system to 3 kHz

desk verdict Solid open-hardware paper with honest validation; the sampling-clock unknown is a fixable gap, not a fatal flaw. read the letter →

arxiv 2411.18566 v2 pith:IAXUJE2X submitted 2024-11-27 physics.ins-det

Oliver Maximilian Zobel , Johannes Maierhofer , Andreas Köstler , Daniel J. Rixen This is my paper · ORCID
classification physics.ins-det
keywords open-sourcehardwareIEPEsensorsdataacquisitionexperimentalmodalanalysisESP32-S3AD7606C-18frequencyresponsefunctionSDcardcaching
verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

OASIS-UROS is an open-source, eight-channel data acquisition system for IEPE vibration sensors that can be built for roughly $220 (€200). The paper documents the hardware, firmware, and GUI, then validates the system by comparing frequency response functions and modal parameters with a commercial acquisition system on an instrumented aluminum beam. Up to 3 kHz, the FRFs show no significant differences; eigenfrequencies match within 0.27% for modes up to 8 kHz, and mode shapes agree closely (near-unity MAC values), though damping ratios differ more. The authors conclude that while OASIS-UROS cannot match full commercial performance, it is a viable alternative for students, academics, and small companies with constrained budgets or the need for full insight into and adaptability of the hardware and software.

What carries the argument

The load-bearing piece is the synchronous sampling chain: a hardware PWM signal from the ESP32-S3 sets the sampling frequency and triggers the AD7606C-18 ADC; on the ADC's BUSY falling edge a GPIO interrupt reads all eight channels' bits simultaneously through Octal SPI, an SPI variant using eight data lines, into a GPIO register; and the sample bytes are stored in one of two RAM caches while the second core writes the previous cache page to a microSD card. This double-buffered caching is what allows 18-bit, eight-channel acquisition at up to 36 kHz without a FIFO or PC streaming. Voltage reconstruction follows the AD7606C-18 bipolar transfer function, using the MSB as sign bit and dividing the remaining bits by $2^{17}$.

What would settle it

Split the same IEPE accelerometer signal between OASIS-UROS and a reference DAQ, drive the structure with a known 5 kHz tone, and compare the measured frequency and phase over a 10-second record; if OASIS-UROS reports a frequency error above about 0.1% or a progressive phase lag above 3 kHz that the reference does not, the PWM sampling clock is inaccurate and the close-agreement claim fails.

Watch

Extended reading notes

Core claim

The central claim is that a fully open, reproducible acquisition chain—hardware, firmware, and Python GUI—can deliver measurement quality close to a commercial system for experimental modal analysis. On a stiff aluminum beam excited by an automatic impact hammer, the OASIS-UROS system and a commercial reference system produced FRFs with essentially no observable differences up to 3 kHz. Modal eigenfrequencies extracted from 1–8 kHz differed by at most 0.27% (about 7 Hz on a 2.7 kHz mode), and the Cross-MAC values between the identified mode shapes were near unity except for one mode, while damping ratios showed larger absolute differences. The paper therefore positions OASIS-UROS as a low-cost, fully transparent alternative for teaching and small-scale applications, not as a replacement for high-end commercial hardware.

Load-bearing premise

The claim depends on the assumption that the ESP32-S3's PWM-generated sampling clock is accurate enough that the measured eigenfrequencies are not distorted by sampling-time errors; the paper itself notes that the cause of high-frequency phase deviations is currently unknown.

Editorial extensions

If this is right

  • For FRF-based analyses below 3 kHz, OASIS-UROS can stand in for a commercial system in this class of test case, making modal analysis accessible in teaching labs.
  • Up to 8 kHz, identified eigenfrequencies stay within about 0.3% of the commercial reference, so the system is usable for mode tracking in that range.
  • Above roughly 4 kHz, FRF magnitude and phase deviate noticeably, so applications like substructuring that invert FRF matrices should not assume OASIS-UROS accuracy there without separate validation.
  • Because sampling time is limited only by SD card capacity, the system can record long-duration or triggered measurements with pre-trigger data without a live PC connection.
  • Users can adjust voltage ranges, oversampling, and trigger levels per channel, and combine the recorded data with open-source modal analysis software, giving a fully open workflow.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

  • A stricter validation would split one analog IEPE signal into OASIS-UROS and the reference system simultaneously; if the phase and coherence deviations above 3 kHz persist under identical excitation, they come from the acquisition hardware, not from the different impact sets used in the paper.
  • The observed high-frequency phase rise and coherence drop are consistent with a small error in the PWM-derived sampling clock; if that is the cause, a calibrated or temperature-compensated clock could extend the usable bandwidth beyond 3 kHz, a testable firmware change.
  • The double-buffered SD writing implies a trade-off: for a fixed SD card, raising the oversampling factor lowers the sustainable sampling rate, so the quoted 36 kHz figure applies to low oversampling; this is a direct consequence of the caching design.
  • If the hardware and firmware are adopted by the community, reproducibility of the validation could be checked by ordering the same bill of materials and rerunning the beam test; the paper provides the manufacturing files, dataset, and scripts, so this is a concrete next step.
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Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Referee Report

4 major / 5 minor

Summary. The paper presents OASIS-UROS, an open-source data acquisition system for IEPE sensors, building on a previous OASIS design. It documents the hardware (ESP32-S3 microcontroller, AD7606C-18 ADC, IEPE front-end), the firmware, a Python GUI, build instructions, and a bill of materials. The system is validated in an experimental modal analysis test case against a commercial Siemens LMS Scadas system, comparing frequency response functions (FRFs), eigenfrequencies, damping ratios, and mode shapes. The authors claim that OASIS-UROS performs close to the commercial system in some aspects for the utilized test case, with no significant FRF differences up to 3 kHz.

Significance. If the claims hold, the paper provides a valuable low-cost, fully open-source alternative for multi-channel IEPE acquisition, with detailed reproducibility materials (KiCad files, firmware, GUI, validation data, and analysis scripts). The eigenfrequency agreement (within 0.27%) and mode-shape correlation (Cross-MAC near unity for most modes) are encouraging. The paper is honest about several limitations, including the unresolved sampling-clock accuracy and the confounding factors in the comparison. The main risk is that the sampling-clock accuracy is unquantified despite being load-bearing for the FRF comparison; this is fixable with a direct measurement and does not invalidate the archival value of the hardware/software documentation.

major comments (4)
  1. [Section 8.2] The sampling clock accuracy is load-bearing and explicitly unresolved: the authors state 'Whether this can be traced back to inaccuracies of the sampling frequency of OASIS-UROS is currently unknown.' The time base of every OASIS measurement is determined by the ESP32-S3 hardware PWM that generates the ADC CONVST signal. Any frequency offset or jitter in this clock directly scales the frequency axis and adds frequency-dependent phase error. The claim of 'no significant differences up to 3 kHz' is therefore not quantitatively bounded. The authors should measure the actual sampling frequency (e.g., with a frequency counter or by recording a known reference sine wave) and report the deviation and its effect on the FRF phase and eigenfrequency estimates.
  2. [Section 8.2] The FRF comparison simultaneously varies multiple factors: different impacts with different force spectra (Fig. 19), different sample rates (25.6 kHz for OASIS vs 51.2 kHz for LMS), different analysis software (pyFRF vs Simcenter Testlab), and different windows (exponential window applied only to OASIS, with uncorrected energy loss). Consequently, observed differences such as the phase rise above 3 kHz cannot be attributed specifically to the OASIS acquisition hardware. A more controlled comparison—for example, recording the same transducer signals through a splitter or at least using the same excitation data—would be necessary to substantiate the 'close performance' claim quantitatively.
  3. [Section 8.3] The summary statement 'for frequencies up to 3 kHz, no significant differences were observable in the FRFs' is not consistent with the acknowledged reduced amplitudes of the OASIS FRFs due to the uncorrected exponential window (Section 8.2). The magnitude offset is a systematic difference, not a negligible effect. The claim should either be qualified (e.g., 'apart from a scale factor and increased noise') or the window should be corrected (or its effect quantified). Without this, the claim overstates the agreement.
  4. [Section 8.3, Table 7] The eigenfrequency comparison is used to argue against a sampling-clock offset (modes 8-10 show smaller deviations, suggesting no consistent frequency shift), but this heuristic is confounded by the different modal fit algorithms (PolyMAX vs pLSCF/LSFD), different analysis bands, and different windowing applied to OASIS data. A direct measurement of the sampling clock or a comparison using a known-frequency source would provide a far stronger test. Additionally, the damping ratios differ by up to 0.51% absolute (modes 4 and 8), which is likely related in part to the exponential window; this should be discussed quantitatively rather than left as an unexplained discrepancy.
minor comments (5)
  1. [Figures 19-21] The figure legends contain placeholder text 'Draft ... Commit SHA: DUMMY SHA File - RUN COMPILE ON GitLab!' which should be removed or replaced with proper captions before publication.
  2. [Section 3.2] The cache selection logic is described inconsistently: first it says 'If the number is odd ... the data is written to OASISCacheA', then 'If CachePage is odd, then OASISCacheB is used.' The second sentence should presumably read 'If CachePage is even'.
  3. [Section 3.3, Eq. (1)] The voltage conversion uses BitDivider = 2^17; for an 18-bit ADC with a sign bit, the maximum positive code is 2^17-1, so the formula introduces a small gain error at full scale. Clarify the exact code mapping or reference the datasheet to confirm the intended scaling.
  4. [Section 7.3] The statement that a sampling frequency of 36 kHz is achievable 'with x16 oversampling' should be reconciled with the ADC throughput table (Table 5) and the abstract's 'up to 36 kHz' phrasing. Specify the oversampling setting used at 36 kHz and any limitations.
  5. [Appendix A] In the 'Set oversampling factor' command description, the text says 'Sets the voltage range on a per-channel basis'; this appears to be a copy-paste error and should be corrected to 'oversampling factor'.

Circularity Check

0 steps flagged · score 0.0 of 10

No circularity: OASIS-UROS validation is an external comparison against commercial hardware with independent open-source processing, and no predicted result reduces to its inputs.

full rationale

The paper's central claim is that OASIS-UROS performs close to a commercial system in an EMA test case (abstract; Section 8). This is a direct comparison of measured FRF magnitude, phase, and coherence and of estimated modal parameters between OASIS-UROS and the Siemens LMS Scadas system, using raw time data and FRFs published separately at [9] and processing the OASIS data with the external open-source packages pyFRF [8] and pyFBS [2]. No parameter is fitted to the commercial target in order to produce the comparison; the eigenfrequency differences in Table 7 are reported results, not enforced matches. The only self-citations are to the prior OASIS design paper [3] for lineage and to the authors' own dataset [9], and neither supplies a premise needed to derive the validation conclusion. The admitted uncertainty about PWM sampling-clock accuracy (Section 8.2: 'Whether this can be traced back to inaccuracies of the sampling frequency of OASIS-UROS is currently unknown') is a limitation on measurement validity, not a circular reduction: it is an unresolved empirical risk, and the paper explicitly does not use it as evidence. No equation, fitted parameter, ansatz, or uniqueness theorem is imported from the authors' prior work, and no claimed prediction is equivalent by construction to an input. Therefore the derivation chain is self-contained and the circularity score is 0.

Assumptions & free parameters 0 free parameters · 4 assumptions · 0 invented entities

The central claim relies on datasheet specifications, the assumed accuracy of the ESP32 PWM clock, and the validity of the commercial system and modal estimation algorithms as references. No free parameters are fitted to data; the 4 mA IEPE current is a standard setting, not a fitted constant.

assumptions (4)
  • domain assumption AD7606C-18 ADC transfer function (Eq. 1) and timing from datasheet [4]
    The conversion from ADC code to voltage and the sampling timing diagram are taken as given from the manufacturer's datasheet.
  • domain assumption ESP32-S3 PWM provides a sampling clock with acceptable jitter
    The firmware uses a hardware PWM signal to trigger ADC conversions; the paper does not measure jitter and leaves open whether observed high-frequency phase errors come from clock inaccuracy.
  • domain assumption LMS Scadas and Testlab serves as a valid reference
    The commercial system is treated as ground truth for FRFs and modal parameters without independent metrological verification.
  • domain assumption PolyMAX and pyFBS pLSCF/LSFD give comparable modal estimates
    The comparison assumes differences in identified modes reflect the acquisition chain, not the different modal identification algorithms; the paper acknowledges this confound.

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Cite this review

Pith. "Pith review of OASIS-UROS: Open Acquisition System for IEPE Sensors -- Upgraded, Refined, and Overhauled Software." pith.science (2026). https://pith.science/paper/IAXUJE2X

@misc{pith2026241118566,
  author       = {Pith},
  title        = {Pith review of: OASIS-UROS: Open Acquisition System for IEPE Sensors -- Upgraded, Refined, and Overhauled Software},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/IAXUJE2X}},
  note         = {Machine review of arXiv:2411.18566}
}
read the original abstract

OASIS-UROS continues the previously published Open Acquisition System for IEPE Sensors (OASIS). While still building on the ESP32 microcontroller, this version improves the overall performance by switching to an SD card caching system and upgrading the analog-digital converter to an AD7606C-18, which has a higher resolution, provides eight channels, oversampling, and software-adjustable voltage ranges. Also improved is the IEPE front-end and power supply, as well as the firmware of the acquisition system, which can now achieve a sample rate of up to 36 kHz while sampling all eight channels. This paper documents the hardware and software of OASIS-UROS and provides all materials required to reproduce the open acquisition system. Lastly, the system was validated against commercial hardware and software in an experimental modal analysis context. This showed that the system performs close to the commercial one in some aspects with respect to the utilized test case. While OASIS-UROS cannot match the full performance of the commercial system, the developed system can be a viable alternative for students, people in academia, or smaller companies that have a constrained budget or require complete insight as well as adaptability of the hardware and software.

Figures

Figures reproduced from arXiv: 2411.18566 by the authors.

Figure 1
Figure 1. Overview of the OASIS-UROS board 4 [PITH_FULL_IMAGE:figures/full_fig_p004_1.png] view at source ↗
Figure 2
Figure 2. State diagram of the OASIS firmware depicting the standard sample procedure If the system is controlled manually, the user should note that voltage ranges and oversampling values are not set using the OASIS.Sample() command, but have to be configured before with the appropriate commands. During the system initialization, all voltage ranges are set to ±2.5 V and the oversampling factor to x4. Further, the ADC is conf… view at source ↗
Figure 3
Figure 3. Timing diagram of ADC sampling routine depicting logical values of pins over time, based on [ [PITH_FULL_IMAGE:figures/full_fig_p008_3.png] view at source ↗
Figures from the paper (19 more)
Figure 4
Figure 4. Figure 4: Illustration of ADC sample extraction from the GPIO input register [PITH_FULL_IMAGE:figures/full_fig_p009_4.png]
Figure 5
Figure 5. Figure 5: Illustration of ADC sample transfer concept [PITH_FULL_IMAGE:figures/full_fig_p010_5.png]
Figure 6
Figure 6. Figure 6: Illustration of assembling the ADC data sorted by channel ( [PITH_FULL_IMAGE:figures/full_fig_p011_6.png]
Figure 7
Figure 7. Figure 7: Transfer function between the analog input voltage and [PITH_FULL_IMAGE:figures/full_fig_p011_7.png]
Figure 8
Figure 8. Figure 8: Partially assembled PCB using the provided JLCPCB manufacturing file (right) and recommended [PITH_FULL_IMAGE:figures/full_fig_p016_8.png]
Figure 9
Figure 9. Figure 9: Assembly step 1: Soldering the ADC ADC0, pinout shown on the right for quick reference Check of ADC When connecting the board to the PC again, the following output should be displayed. As can be seen, for instance from [OASIS] Successfully written 0x18 to address 0x2, …
Figure 10
Figure 10. Figure 10: Assembly step 2: Soldering the boost converter inductance [PITH_FULL_IMAGE:figures/full_fig_p019_10.png]
Figure 11
Figure 11. Figure 11: Assembly step 3: Soldering the constant current source ICs [PITH_FULL_IMAGE:figures/full_fig_p020_11.png]
Figure 12
Figure 12. Figure 12: Assembly step 4: Soldering the BNC connectors [PITH_FULL_IMAGE:figures/full_fig_p020_12.png]
Figure 13
Figure 13. Figure 13: Recommended setup for calibrating the constant current sources of each channel [PITH_FULL_IMAGE:figures/full_fig_p021_13.png]
Figure 14
Figure 14. Figure 14: OASIS-GUI after opening with an OASIS-UROS board connected Device Selection and Search Besides selecting the active device, i.e., the one used for data acquisition, this section allows to re-scan the connected devices using the Search Devices button. Device Informatio…
Figure 15
Figure 15. Figure 15: OASIS-GUI after data acquisition completed successfully If not already selected as a post-processing option, the user can now manually invoke a plot of the sample with Show Previous Data. This will create a matplotlib plot of all eight channels over time, as depicted …
Figure 16
Figure 16. Figure 16: Plot displayed by OASIS-GUI after the data acquisition is completed [PITH_FULL_IMAGE:figures/full_fig_p026_16.png]
Figure 17
Figure 17. Figure 17: Plot displayed by OASIS-GUI after the triggered data acquisition is completed 26 [PITH_FULL_IMAGE:figures/full_fig_p026_17.png]
Figure 18
Figure 18. Figure 18: Experimental setup of stiff aluminum beam structure fixed to a vibration-isolated table. The system [PITH_FULL_IMAGE:figures/full_fig_p027_18.png]
Figure 19
Figure 19. Figure 19: Excitation signal of the automatic impulse hammer for each impact over time (left) and frequency [PITH_FULL_IMAGE:figures/full_fig_p028_19.png]
Figure 20
Figure 20. Figure 20: Comparison of FRF magnitude, phase, and coherence for sensors 1-4 between commercial and open [PITH_FULL_IMAGE:figures/full_fig_p029_20.png]
Figure 21
Figure 21. Figure 21: Comparison of FRF magnitude, phase, and coherence for sensors 5-7 between commercial and open [PITH_FULL_IMAGE:figures/full_fig_p030_21.png]
Figure 22
Figure 22. Figure 22: Cross-Modal Assurance Criterion between the mode shapes identified by the commercial system [PITH_FULL_IMAGE:figures/full_fig_p031_22.png]

Discussion (0). Continue with ORCID to comment.

Reference graph

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