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arxiv: 1907.00625 · v1 · pith:IK2YJKGAnew · submitted 2019-07-01 · 💻 cs.NE · cs.SY· eess.SY

On-chip learning in a conventional silicon MOSFET based Analog Hardware Neural Network

Nilabjo Dey , Janak Sharda , Utkarsh Saxena , Divya Kaushik , Utkarsh Singh , Debanjan Bhowmik This is my paper

Pith reviewed 2026-05-25 11:49 UTC · model grok-4.3

classification 💻 cs.NE cs.SYeess.SY
keywords analog neural networkon-chip learningMOSFET synapsecrossbar arraySPICE simulationIris datasetfully connected neural networkweight update circuit
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The pith

Conventional MOSFET transistors can act as synapses for on-chip learning in an analog hardware neural network.

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The paper demonstrates on-chip learning in a crossbar-based analog neural network built entirely from standard silicon MOSFETs rather than specialized non-volatile memory devices. It models a single-transistor synapse in SPICE, designs analog circuits for neurons and weight updates, and simulates a fully connected network that reaches high training and test accuracy on the Iris dataset. The work shows that this approach yields speed and energy figures comparable to earlier NVM-based systems while allowing fabrication through ordinary merchant foundries. The central result is that on-chip training becomes feasible without floating-gate or exotic memory technologies.

Core claim

An analog hardware neural network using conventional MOSFETs as synapses, together with analog peripheral circuits for neuron activation and synaptic weight updates, supports on-chip learning; SPICE simulation of the full system produces high training and test accuracy on Fisher's Iris dataset and energy-speed performance comparable to prior NVM-device implementations.

What carries the argument

Single-transistor MOSFET synapse whose current-voltage characteristic is modeled in SPICE and embedded in a crossbar array with analog circuits that compute weight updates during on-chip learning.

If this is right

  • On-chip learning becomes possible using only standard CMOS transistors that can be made in merchant foundries.
  • The system avoids the large voltage pulses required by floating-gate transistors, improving energy efficiency.
  • Training and test accuracy on the Iris dataset reaches levels previously shown with NVM-based analog networks.
  • Speed and energy consumption during on-chip learning remain comparable to earlier RRAM, PCM, and spintronic implementations.

Where Pith is reading between the lines

These are editorial extensions of the paper, not claims the author makes directly.

  • If the MOSFET synapse model holds in silicon, the same crossbar architecture could be scaled to larger networks without requiring new materials or processes.
  • Real-device mismatch or temperature drift could be tested by adding Monte-Carlo variation to the SPICE netlist and checking whether learning still converges.
  • The approach opens a route to integrate analog on-chip learning directly with conventional digital CMOS logic on the same chip.

Load-bearing premise

SPICE models of the MOSFET synapses and analog weight-update circuits accurately represent real-device behavior without being disrupted by noise, mismatch, or fabrication variations.

What would settle it

Fabricate the MOSFET crossbar and peripheral circuits in silicon and measure whether on-chip training on the Iris dataset still reaches the reported training and test accuracies.

Figures

Figures reproduced from arXiv: 1907.00625 by Debanjan Bhowmik, Divya Kaushik, Janak Sharda, Nilabjo Dey, Utkarsh Saxena, Utkarsh Singh.

Figure 1
Figure 1. Figure 1: (a) Schematic of proposed n-MOSFET synapse. Following sub-plots are obtained from [PITH_FULL_IMAGE:figures/full_fig_p004_1.png] view at source ↗
Figure 2
Figure 2. Figure 2: Experimental data obtained from measurement on single n-MOSFET in commercially [PITH_FULL_IMAGE:figures/full_fig_p005_2.png] view at source ↗
Figure 3
Figure 3. Figure 3: Conductance GDS (and hence weight)and corresponding gate voltage (VGS) increase linearly due to programming current pulses which charge the capacitive gate oxide of the MOSFET synapse (blue plot). Conductance and gate voltage decrease linearly due to programming current pulses of opposite polarity which discharge the gate oxide (orange plot) any effect of higher order term of drain voltage VDS on the curre… view at source ↗
Figure 4
Figure 4. Figure 4: Schematic of transistor synapse based cross-bar architecture for weight matrix-input [PITH_FULL_IMAGE:figures/full_fig_p007_4.png] view at source ↗
Figure 5
Figure 5. Figure 5: (a) Neuron circuit present at each output node of the crossbar circuit in Figure 4 shown [PITH_FULL_IMAGE:figures/full_fig_p008_5.png] view at source ↗
Figure 6
Figure 6. Figure 6: (a) Analog peripheral feedback circuit we designed, using conventional silicon transistors [PITH_FULL_IMAGE:figures/full_fig_p010_6.png] view at source ↗
Figure 7
Figure 7. Figure 7: Schematic of crossbar circuit of Fig. 4, neuron circuit of Fig. 5 at each output node of [PITH_FULL_IMAGE:figures/full_fig_p011_7.png] view at source ↗
Figure 8
Figure 8. Figure 8: (a) Accuracy as a function of epochs on 100 train samples of Fisher’s Iris dataset, obtained [PITH_FULL_IMAGE:figures/full_fig_p012_8.png] view at source ↗
Figure 9
Figure 9. Figure 9: Output voltage of neuron circuit at each node of the circuit in Figure 6 , obtained from [PITH_FULL_IMAGE:figures/full_fig_p013_9.png] view at source ↗
Figure 7
Figure 7. Figure 7: For every sample, if the output at each of the three nodes is within 40 percent of the de￾sired output then we consider it a success. For about the first five epochs the accuracy is 0. This is because all three output nodes y1, y2, y3 are at 1,1,1 V for all samples. Hence the output is wrong for all the samples. Output for 2nd epoch for example is shown in [PITH_FULL_IMAGE:figures/full_fig_p013_7.png] view at source ↗
Figure 10
Figure 10. Figure 10: Training accuracy is plotted as function of epoch for the following four cases: without [PITH_FULL_IMAGE:figures/full_fig_p016_10.png] view at source ↗
read the original abstract

On-chip learning in a crossbar array based analog hardware Neural Network (NN) has been shown to have major advantages in terms of speed and energy compared to training NN on a traditional computer. However analog hardware NN proposals and implementations thus far have mostly involved Non Volatile Memory (NVM) devices like Resistive Random Access Memory (RRAM), Phase Change Memory (PCM), spintronic devices or floating gate transistors as synapses. Fabricating systems based on RRAM, PCM or spintronic devices need in-house laboratory facilities and cannot be done through merchant foundries, unlike conventional silicon based CMOS chips. Floating gate transistors need large voltage pulses for weight update, making on-chip learning in such systems energy inefficient. This paper proposes and implements through SPICE simulations on-chip learning in analog hardware NN using only conventional silicon based MOSFETs (without any floating gate) as synapses since they are easy to fabricate. We first model the synaptic characteristic of our single transistor synapse using SPICE circuit simulator and benchmark it against experimentally obtained current-voltage characteristics of a transistor. Next we design a Fully Connected Neural Network (FCNN) crossbar array using such transistor synapses. We also design analog peripheral circuits for neuron and synaptic weight update calculation, needed for on-chip learning, again using conventional transistors. Simulating the entire system on SPICE simulator, we obtain high training and test accuracy on the standard Fisher's Iris dataset, widely used in machine learning. We also compare the speed and energy performance of our transistor based implementation of analog hardware NN with some previous implementations of NN with NVM devices and show comparable performance with respect to on-chip learning.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit. Tearing a paper down is the easy half of reading it; the pith above is the substance, this is the friction.

Referee Report

2 major / 2 minor

Summary. The paper proposes using conventional silicon MOSFETs (without floating gates) as synapses in a crossbar-based analog hardware neural network to enable on-chip learning. A single-transistor synapse is modeled in SPICE and benchmarked against experimental I-V curves; a fully connected NN crossbar and analog peripheral circuits for neurons and weight updates (gradient calculation and pulsing) are then designed using standard transistors. Full-system SPICE simulations are reported to achieve high training and test accuracy on Fisher's Iris dataset, with speed and energy metrics claimed comparable to prior NVM-based analog NN implementations.

Significance. If the idealized SPICE results prove representative of fabricated silicon, the approach would enable on-chip learning in analog hardware using merchant-foundry CMOS processes, sidestepping specialized NVM fabrication and high-voltage requirements of floating-gate devices while retaining potential speed and energy advantages over digital training.

major comments (2)
  1. [full-system SPICE simulation and results] The full-system SPICE simulation results (described after the peripheral-circuit design) rest on ideal device models for the weight-update path without Monte-Carlo mismatch, 1/f noise, or process-variation analysis; only the isolated single-transistor synapse I-V curve is experimentally benchmarked. This directly undermines the central claim that the analog on-chip learning loop converges reliably, as any systematic offset in gradient computation or pulse generation would break the reported Iris accuracy.
  2. [performance comparison] The energy and speed comparison to NVM implementations (final section) is performed under the same idealized SPICE assumptions used for the learning loop; no sensitivity analysis quantifies how analog non-idealities would degrade the claimed accuracy or efficiency, rendering the comparability claim load-bearing yet untested.
minor comments (2)
  1. [simulation results] State the precise network topology (number of layers, hidden neurons, output classes) and the exact training/test split and accuracy numbers for the Iris experiments rather than the qualitative phrase 'high training and test accuracy'.
  2. [analog peripheral circuits] Clarify whether the peripheral circuits for weight update are fully analog or contain any digital control logic, and provide schematic or block-diagram references for the gradient-calculation block.

Simulated Author's Rebuttal

2 responses · 0 unresolved

We thank the referee for the constructive comments on our simulation-based study. We address each major comment below.

read point-by-point responses

  1. Referee: [full-system SPICE simulation and results] The full-system SPICE simulation results (described after the peripheral-circuit design) rest on ideal device models for the weight-update path without Monte-Carlo mismatch, 1/f noise, or process-variation analysis; only the isolated single-transistor synapse I-V curve is experimentally benchmarked. This directly undermines the central claim that the analog on-chip learning loop converges reliably, as any systematic offset in gradient computation or pulse generation would break the reported Iris accuracy.

    Authors: Our manuscript is a SPICE simulation study demonstrating on-chip learning feasibility with conventional MOSFET synapses. The single-transistor synapse is benchmarked against experimental I-V data, while the full crossbar and peripheral circuits use standard transistor models. The reported Iris accuracy shows that the learning loop converges under these modeled conditions. We do not claim experimental validation of the complete system or robustness to mismatch/noise; such analysis would require fabricated silicon and is outside the paper's scope. We can add a brief discussion of these limitations. revision: partial

  2. Referee: [performance comparison] The energy and speed comparison to NVM implementations (final section) is performed under the same idealized SPICE assumptions used for the learning loop; no sensitivity analysis quantifies how analog non-idealities would degrade the claimed accuracy or efficiency, rendering the comparability claim load-bearing yet untested.

    Authors: The comparisons use performance figures extracted directly from our SPICE simulations and the numbers reported in the cited NVM papers. This is consistent with the idealized framework of the study. We agree the claim would benefit from explicit qualification and will revise the final section to state that the metrics are simulation-derived under ideal conditions. revision: yes

Circularity Check

0 steps flagged

No significant circularity; results are direct simulation outputs.

full rationale

The paper derives its reported training/test accuracies and energy/speed metrics solely from end-to-end SPICE simulations of a MOSFET crossbar plus peripheral circuits on the Iris dataset. No equations, fitted parameters, or self-citations are shown that reduce these outputs to inputs by construction (e.g., no synaptic I-V model is defined from the target accuracy, and no uniqueness theorem or ansatz is imported from prior author work). The derivation chain is therefore self-contained against external benchmarks.

Axiom & Free-Parameter Ledger

0 free parameters · 1 axioms · 0 invented entities

The central claim depends on the accuracy of SPICE transistor models for synaptic weight updates and the assumption that analog peripheral circuits can perform the required calculations without additional non-idealities.

axioms (1)
  • domain assumption SPICE models of conventional MOSFETs accurately represent synaptic conductance modulation for on-chip learning
    The paper first models the synaptic characteristic using SPICE and benchmarks against experimental current-voltage characteristics before building the full network.

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Reference graph

Works this paper leans on

54 extracted references · 54 canonical work pages · 3 internal anchors

  1. [1]

    LeCun et al., Nature, vol

    Y. LeCun et al., Nature, vol. 521, pp 436-444, 2015

    work page 2015

  2. [2]

    Misra and I

    J. Misra and I. Saha, Neurocomputing, vol. 74, pp. 239-255, 2010

    work page 2010

  3. [3]

    C. D. Schuman et al. , arxiv. 1705.06963v1

    work page internal anchor Pith review Pith/arXiv arXiv

  4. [4]

    Boahen, Computing in Science & Engi- neering, vol

    K. Boahen, Computing in Science & Engi- neering, vol. 19, no. 2, 2017

    work page 2017

  5. [5]

    Tsai et al

    H. Tsai et al. , J. Phys. D: Appl. Phys. vol. 51, no. 283001, 2018

    work page 2018

  6. [6]

    Sebastian et al

    A. Sebastian et al. , J. Appl. Phys. vol. 124, no. 111101, 2018. 16

    work page 2018

  7. [7]

    Sengupta et al

    A. Sengupta et al. , IEEE Transactions on Circuits and Systems- I, vol. 63, no. 12, 2016

    work page 2016

  8. [8]

    P. A. Merolla et al. , Science vol. 345, no. 6197, pp. 668-697, 2014

    work page 2014

  9. [9]

    Furber et al

    S.B. Furber et al. , Proceedings of the IEEE, vol. 102, no. 5, pp. 652-665, 2014

    work page 2014

  10. [10]

    Davies et al

    M. Davies et al. , IEEE Micro., pp. 82-89, 2018

    work page 2018

  11. [11]

    Diamond et al

    A. Diamond et al. , Frontiers in Neuro- science, vol. 9, pp. 491, 2016

    work page 2016

  12. [12]

    G.W.Burr et al. in Proc. IEEE Interna- tional Electron Devices Meeting (IEDM), pp. 29.5.129.5.4, 2014

    work page 2014

  13. [13]

    Ielmini and H

    D. Ielmini and H. S. Philip Wong, Nature Electronics, vol. 1, no. 111101, pp. 333-343, 2018

    work page 2018

  14. [14]

    Suri ed., Cognitive Systems Mono- graphs, Springer, 2017

    M. Suri ed., Cognitive Systems Mono- graphs, Springer, 2017

    work page 2017

  15. [15]

    Grollier et al

    J. Grollier et al. Proceedings of the IEEE, vol. 104, no. 10, 2016

    work page 2016

  16. [16]

    Boybat et al

    I. Boybat et al. , Nature Communications, vol. 9, no. 2514, 2018

    work page 2018

  17. [17]

    Li et al., J

    Y. Li et al., J. Phys. D: Appl. Phys. vol. 51, no. 50, 2018

    work page 2018

  18. [18]

    Suri et al

    M. Suri et al. , Proc. IEEE International Electron Devices Meeting (IEDM), pp. 4.4.1- 4.4.4, 2011

    work page 2011

  19. [19]

    Hasler et al., in Proc

    P. Hasler et al., in Proc. NIPS, pp. 817-824, 1994

    work page 1994

  20. [20]

    Diorio et al., IEEE Transactions on Elec- tron Devices, vol

    C. Diorio et al., IEEE Transactions on Elec- tron Devices, vol. 43, no. 11, 1996

    work page 1996

  21. [21]

    B. W. Lee et al., IEEE Transactions on Cir- cuits and Systems, vol. 38, no. 6, 1991

    work page 1991

  22. [22]

    Horio et al

    Y. Horio et al. IEEE International Sympo- sium on Circuits and Systems, 1990 (DOI: 10.1109/ISCAS.1990.112638)

    work page doi:10.1109/iscas.1990.112638 1990

  23. [23]

    Nishi ed

    Y. Nishi ed. Advances in non-volatile mem- ory, Elsevier 2014

    work page 2014

  24. [24]

    Choi et al

    H. Choi et al. , IEEE Transactions on Elec- tron Devices, vol. 65, no. 1, 2018

    work page 2018

  25. [25]

    Burr et al

    G. Burr et al. , IEEE Transactions on Elec- tron Devices, vol. 62, no. 11, 2015

    work page 2015

  26. [26]

    Chen et al

    P. Chen et al. IEEE International Electron Device Meeting, 2017 (DOI: 10.1109/IEDM.2017.8268337)

    work page doi:10.1109/iedm.2017.8268337 2017

  27. [27]

    Gokmen and Y

    T. Gokmen and Y. Vlasov, Frontiers in Neu- roscience vol. 10, no. 333, 2016

    work page 2016

  28. [28]

    Hirohata et al

    A. Hirohata et al. , IEEE Transactions on Magnetics, vol. 51, no. 10, 2015

    work page 2015

  29. [29]

    UCI repository of ma- chine learning databases

    D. J. Newman et al., “UCI repository of ma- chine learning databases”, Department of In- formation and Computer Science, University of California Irvine, CA, 1998

    work page 1998

  30. [30]

    Saxena, D

    U. Saxena, D. Kaushik, M. Bansal, U. Sahu and D. Bhowmik, IEEE Transactions on Magnetics, vol. 54, no. 11, 2018

    work page 2018

  31. [31]

    Sengupta et al

    A. Sengupta et al. , Proc. IEEE Biomedical Circuits and Systems Conference (BioCAS), no. 7833852, 2016

    work page 2016

  32. [32]

    C. S. Thakur et al., IEEE Trans. on Circuits and Systems- I, vol. 63, no. 2, 2016

    work page 2016

  33. [33]

    Tripathi et al

    A. Tripathi et al. , Proc.in IEEE Interna- tional Symposium on Circuits and Systems (ISCAS), 2019

    work page 2019

  34. [34]

    P. U. Diehl and M. Cook, Front. Comput. Neurosci. vol. 9, no. 99, 2015

    work page 2015

  35. [35]

    G. Q. Bi and M. M. Poo, J. Neurosci. 18, pp. 1046410472, 1998

    work page 1998

  36. [36]

    Pfeiffer et al

    M. Pfeiffer et al. Frontiers in Neuroscience vol. 12, no. 774, 2018

    work page 2018

  37. [37]

    Narayanan et al

    P. Narayanan et al. IBM Journal of Re- search and Development, vol. 61, no. 4/5, 2017. 17

    work page 2017

  38. [38]

    Sengupta, A

    A. Sengupta, A. Banerjee, and K. Roy, Phys. Rev. Appl. vol. 6, no. 064003, 2016

    work page 2016

  39. [39]

    Bhattacharya et al

    T. Bhattacharya et al. Proc. in IEEE In- ternational Joint Conference on Neural Net- works (IJCNN), no. 18181462 (2018)

    work page 2018

  40. [40]

    MOS Transistor in Modern Semi- conductor Devices for Integrated Circuits

    C. Hu, “MOS Transistor in Modern Semi- conductor Devices for Integrated Circuits”, Pearson, 2010

    work page 2010

  41. [41]

    Neural Networks,

    S. Haykin, “Neural Networks,” Pearson, 1994

    work page 1994

  42. [42]

    B. D. Yammenavar et al. , International Journal of Artificial Intelligence and Appli- cations (IJAIA), vol. 2, no. 3, 2011

    work page 2011

  43. [43]

    Khodabandehloo et al

    G. Khodabandehloo et al. ,IEEE Trans. on VLSI Systems, vol. 20, no. 4, 2012

    work page 2012

  44. [44]

    Neamen et al., Electronic Circuits- Anal- ysis and Design, McGraw Hill, 2006

    D. Neamen et al., Electronic Circuits- Anal- ysis and Design, McGraw Hill, 2006

    work page 2006

  45. [45]

    A Comprehensive Study of the Howland Current Pump

    AN-1515 “A Comprehensive Study of the Howland Current Pump” (PDF) (PDF). Texas Instruments, Inc. 2013

    work page 2013

  46. [46]

    Gokmen et al

    T. Gokmen et al. , Front. Neurosci. vol. 10, no. 333, 2016

    work page 2016

  47. [47]

    Analog CMOS-based Resistive Processing Unit for Deep Neural Network Training

    S. Kim et al. ,arXiv:1706.06620, 2017

    work page internal anchor Pith review Pith/arXiv arXiv 2017

  48. [48]

    A simple and efficient SNN and its performance & robustness evaluation method to enable hardware implementation

    A. Biswas et al. , arXiv:1612.02233, 2016

    work page internal anchor Pith review Pith/arXiv arXiv 2016

  49. [49]

    Bhowmik et al

    D. Bhowmik et al. , J Magn Magn Mater., vol. 489, no. 165434, 2019

    work page 2019

  50. [50]

    Zhang et al

    S. Zhang et al. , Adv. Electron Mater., no. 1800782, 2019

    work page 2019

  51. [51]

    Chen et al

    P. Chen et al. , IEEE Trans. Electron De- vices, vol. 62, no. 12, 2015

    work page 2015

  52. [52]

    Li et al., Nature Comm

    C. Li et al., Nature Comm. vol. 9, no. 2385, 2018

    work page 2018

  53. [53]

    Emori et al., Spin Hall torque magnetom- etry of Dzyaloshinskii do- main walls, Physi- cal Review B, vol

    S. Emori et al., Spin Hall torque magnetom- etry of Dzyaloshinskii do- main walls, Physi- cal Review B, vol. 90, no. 184427, 2014

    work page 2014

  54. [54]

    Emori, U

    S. Emori, U. Bauer, S.M. Ahn, E. Martinez and G. S. D. Beach, Nature Materials, vol.12, pp. 611616, 2013. 18

    work page 2013