Paper Citation Record · LEDGER

Large Language Model for Verilog Generation with Code-Structure-Guided Reinforcement Learning

As of 8 August 2026, this Paper Citation Record lists 0 of 0 outbound references and 4 inbound Pith citation observations for arXiv:2407.18271.

A citation records a reference. It does not transfer a finding from one paper to another.

pith.paper-citation-record.v1
2407.18271 v4

Coverage vector

measured 0 of 0 reference resolution

Typed states for the displayed outbound observations.

Source: paper_references, paper_reference_links

measured 4 of 4 standing notices

One-hop event checks from named stored sources.

Source: scholarly_work_events, retraction_status_cache, observed 2026-08-08T06:32:00.761636+00:00

measured 4 of 4 inbound itemization

Pith citing papers itemized under the disclosed page cap.

Source: paper_references, paper_reference_links, observed 2026-08-06T18:54:07.258005Z

measured 0 of 1 external citation measurements

A source-named dated measurement, never combined with another source.

Source: arxiv_reference, observed 2026-05-19T11:27:16.026707Z

Reference resolution

0 of 0 outbound references displayed

verified exact0
verified fuzzy0
unresolved0
parse uncertain0
malformed identifier0
metadata mismatch0

External citation measurements

No source-named external measurement is stored.

Outbound references

No outbound reference observations are available for this paper version.

Pith citing papers

Observation 53c1373d-f6aa-4acb-8a95-920387858610 · inbound

ORFS-agent: Tool-Using Agents for Chip Design Optimization cites this paper.

ORFS-agent: Tool-Using Agents for Chip Design Optimization Large Language Model for Verilog Generation with Code-Structure-Guided Reinforcement Learning

Reference 36

Resolution: verified exact; arxiv_id, observed 2026-05-19T11:27:16.029260Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-08T06:32:00.761636+00:00.

Observation a2604959-db84-41c8-a217-105bbd8bfcfa · inbound

ChatHLS: Towards Systematic Design Automation and Optimization for High-Level Synthesis cites this paper.

ChatHLS: Towards Systematic Design Automation and Optimization for High-Level Synthesis Large Language Model for Verilog Generation with Code-Structure-Guided Reinforcement Learning

Reference 30

Resolution: verified exact; arxiv_id, observed 2026-05-19T07:02:07.842974Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-08T06:32:00.761636+00:00.

Observation e54a1fef-7684-4dfd-a8f9-c9e708825b15 · inbound

VerilogDB: The Largest, Highest-Quality Dataset with a Preprocessing Framework for LLM-based RTL Generation cites this paper.

VerilogDB: The Largest, Highest-Quality Dataset with a Preprocessing Framework for LLM-based RTL Generation Large Language Model for Verilog Generation with Code-Structure-Guided Reinforcement Learning

Reference 47

Resolution: unresolved; no resolver link, observed 2026-08-06T18:54:07.258005Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 354d0a18-51fc-47d0-9da8-7df04fc66b20 · inbound

MACO: A Multi-Agent LLM Framework for Automated CGRA Hardware/Software Co-Design cites this paper.

MACO: A Multi-Agent LLM Framework for Automated CGRA Hardware/Software Co-Design Large Language Model for Verilog Generation with Code-Structure-Guided Reinforcement Learning

Reference 25

Resolution: unresolved; no resolver link, observed 2026-08-04T16:31:32.488498Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.