Paper Citation Record · LEDGER

Large Language Model for Verilog Generation with Code-Structure-Guided Reinforcement Learning

As of 18 August 2026, this Paper Citation Record lists 0 of 0 outbound references and 11 inbound Pith citation observations for arXiv:2407.18271.

A citation records a reference. It does not transfer a finding from one paper to another.

pith.paper-citation-record.v1
2407.18271 v4

Coverage vector

measured 0 of 0 reference resolution

Typed states for the displayed outbound observations.

Source: paper_references, paper_reference_links

measured 11 of 11 standing notices

One-hop event checks from named stored sources.

Source: scholarly_work_events, retraction_status_cache, observed 2026-08-18T06:34:40.430872+00:00

measured 11 of 11 inbound itemization

Pith citing papers itemized under the disclosed page cap.

Source: paper_references, paper_reference_links, observed 2026-08-16T11:50:20.353248Z

measured 0 of 1 external citation measurements

A source-named dated measurement, never combined with another source.

Source: arxiv_reference, observed 2026-05-19T11:27:16.026707Z

Reference resolution

0 of 0 outbound references displayed

verified exact0
verified fuzzy0
unresolved0
parse uncertain0
malformed identifier0
metadata mismatch0

External citation measurements

No source-named external measurement is stored.

Outbound references

No outbound reference observations are available for this paper version.

Pith citing papers

Observation bda3d89b-a9ea-49c5-9bf0-500d53130b0e · inbound

ReasoningV: Efficient Verilog Code Generation with Adaptive Hybrid Reasoning Model cites this paper.

ReasoningV: Efficient Verilog Code Generation with Adaptive Hybrid Reasoning Model Large Language Model for Verilog Generation with Code-Structure-Guided Reinforcement Learning

Reference 25

Resolution: unresolved; no resolver link, observed 2026-08-16T11:50:20.353248Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 5acca285-beed-434a-974c-78d2a17edf20 · inbound

VeriCoder: Enhancing LLM-Based RTL Code Generation through Functional Correctness Validation cites this paper.

VeriCoder: Enhancing LLM-Based RTL Code Generation through Functional Correctness Validation Large Language Model for Verilog Generation with Code-Structure-Guided Reinforcement Learning

Reference 45

Resolution: unresolved; no resolver link, observed 2026-08-16T11:25:20.286157Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 2565d436-a6bd-4be2-b903-a4817a4b8a59 · inbound

Insights from Verification: Training a Verilog Generation LLM with Reinforcement Learning with Testbench Feedback cites this paper.

Insights from Verification: Training a Verilog Generation LLM with Reinforcement Learning with Testbench Feedback Large Language Model for Verilog Generation with Code-Structure-Guided Reinforcement Learning

Reference 33

Resolution: unresolved; no resolver link, observed 2026-08-16T11:22:02.386711Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 4bf09d87-65d1-46d7-874b-fed84a678d61 · inbound

VeriDebug: A Unified LLM for Verilog Debugging via Contrastive Embedding and Guided Correction cites this paper.

VeriDebug: A Unified LLM for Verilog Debugging via Contrastive Embedding and Guided Correction Large Language Model for Verilog Generation with Code-Structure-Guided Reinforcement Learning

Reference 7

Resolution: unresolved; no resolver link, observed 2026-08-16T06:06:52.163742Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation e689daf8-3357-4ab3-8f78-b9e4b0775f40 · inbound

Free and Fair Hardware: A Pathway to Copyright Infringement-Free Verilog Generation using LLMs cites this paper.

Free and Fair Hardware: A Pathway to Copyright Infringement-Free Verilog Generation using LLMs Large Language Model for Verilog Generation with Code-Structure-Guided Reinforcement Learning

Reference 18

Resolution: unresolved; no resolver link, observed 2026-08-15T22:51:43.716862Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 53c1373d-f6aa-4acb-8a95-920387858610 · inbound

ORFS-agent: Tool-Using Agents for Chip Design Optimization cites this paper.

ORFS-agent: Tool-Using Agents for Chip Design Optimization Large Language Model for Verilog Generation with Code-Structure-Guided Reinforcement Learning

Reference 36

Resolution: verified exact; arxiv_id, observed 2026-05-19T11:27:16.029260Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-18T06:34:40.430872+00:00.

Observation becc77b3-2f9e-4970-9033-2b67cf9f6757 · inbound

Comprehensive Verilog Design Problems: A Next-Generation Benchmark Dataset for Evaluating Large Language Models and Agents on RTL Design and Verification cites this paper.

Comprehensive Verilog Design Problems: A Next-Generation Benchmark Dataset for Evaluating Large Language Models and Agents on RTL Design and Verification Large Language Model for Verilog Generation with Code-Structure-Guided Reinforcement Learning

Reference 2

Resolution: unresolved; no resolver link, observed 2026-08-15T19:59:24.400299Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 20ac1436-9ae1-491b-9450-f5166569fe34 · inbound

ChatModel: Automating Reference Model Design and Verification with LLMs cites this paper.

ChatModel: Automating Reference Model Design and Verification with LLMs Large Language Model for Verilog Generation with Code-Structure-Guided Reinforcement Learning

Reference 79

Resolution: unresolved; no resolver link, observed 2026-08-15T19:48:44.169825Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation a2604959-db84-41c8-a217-105bbd8bfcfa · inbound

ChatHLS: Towards Systematic Design Automation and Optimization for High-Level Synthesis cites this paper.

ChatHLS: Towards Systematic Design Automation and Optimization for High-Level Synthesis Large Language Model for Verilog Generation with Code-Structure-Guided Reinforcement Learning

Reference 30

Resolution: verified exact; arxiv_id, observed 2026-05-19T07:02:07.842974Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-18T06:34:40.430872+00:00.

Observation e54a1fef-7684-4dfd-a8f9-c9e708825b15 · inbound

VerilogDB: The Largest, Highest-Quality Dataset with a Preprocessing Framework for LLM-based RTL Generation cites this paper.

VerilogDB: The Largest, Highest-Quality Dataset with a Preprocessing Framework for LLM-based RTL Generation Large Language Model for Verilog Generation with Code-Structure-Guided Reinforcement Learning

Reference 47

Resolution: unresolved; no resolver link, observed 2026-08-06T18:54:07.258005Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 354d0a18-51fc-47d0-9da8-7df04fc66b20 · inbound

MACO: A Multi-Agent LLM Framework for Automated CGRA Hardware/Software Co-Design cites this paper.

MACO: A Multi-Agent LLM Framework for Automated CGRA Hardware/Software Co-Design Large Language Model for Verilog Generation with Code-Structure-Guided Reinforcement Learning

Reference 25

Resolution: unresolved; no resolver link, observed 2026-08-04T16:31:32.488498Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.