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REVIEW 2 major objections 1 minor 35 references

Controllable Latent Space Augmentation for Digital Pathology

T0 review · 2 major / 1 minor · reviewed 2026-08-05 · deepseek-v4-flash

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Pith's one-line read A generative model applies controllable augmentations directly to pathology slide embeddings, improving weakly supervised diagnosis without relabeling.

desk verdict The posted manuscript is unreadable as HistAug: the abstract describes a pathology augmentation method, but the full text is an unrelated hardware paper (SNAX), so there is no method, data, or ablation to evaluate. read the letter →

arxiv 2508.14588 v1 pith:J54LADDQ submitted 2025-08-20 cs.CV

Sofiène Boutaj , Marin Scalbert , Pierre Marza , Florent Couzinie-Devy , Maria Vakalopoulou , Stergios Christodoulidis This is my paper
classification cs.CV
keywords HistAugmultipleinstancelearningwholeslideimagesdigitalpathologylatentspaceaugmentationcontrollablegenerativemodellow-dataregime
verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

Whole-slide image analysis with multiple instance learning suffers from data scarcity and the expense of patch-level augmentation. HistAug is a generative model that operates in the latent space of patch embeddings, conditioned on explicit transformations such as hue change or erosion, to produce realistic augmented embeddings that preserve diagnostic semantics. This allows many patches to be processed in a single forward pass and yields consistent accuracy gains across slide-level tasks and organs, especially with limited training data. If correct, HistAug makes controllable feature-space augmentation practical for gigapixel pathology workflows, a gap left by both costly raw-patch augmentation and control-free feature noise.

What carries the argument

The central object is a conditional generative model in the embedding space of a MIL backbone. It takes a patch embedding and a transformation-code vector representing a patch-level operation (hue, erosion, etc.) and outputs an augmented embedding. Conditioning provides controllability; the single-pass design gives efficiency; the training objective keeps outputs semantically close to the original embedding while reflecting the transformation.

What would settle it

Train HistAug on a dataset with controlled transformation labels, then probe whether the augmented embeddings separate by transformation direction while slide-level labels remain intact; if replacing the transformation code with a random code preserves all gains, the conditioning is not load-bearing.

Watch

Extended reading notes

Core claim

HistAug establishes that a conditional generative model can turn explicit patch-level transformations into learned embedding-space edits: conditioning on a transformation code (e.g., hue, erosion) yields augmented embeddings that stay on the pathology manifold and keep semantic content, while a shared backbone processes a large patch batch in one pass. Across multiple slide-level tasks and diverse organs, this controlled latent augmentation consistently improves MIL classifier performance, with the largest margins in low-data regimes. Ablations indicate learned transformation embeddings outperform noise-based perturbations, and uniform whole-slide augmentation is important.

Load-bearing premise

A generative model in the embedding space can encode explicit visual transformations as conditioning signals, with the produced embeddings staying on the pathology manifold and preserving diagnostic semantics.

Editorial extensions

If this is right

  • HistAug can replace expensive patch-level augmentation in MIL pipelines for whole-slide images, lowering computational cost dramatically.
  • The learned transformation-conditioned embeddings produce consistent accuracy gains over noise-based feature augmentation, particularly in low-data settings.
  • Uniform WSI-wise augmentation is beneficial, suggesting that augmentation policies should respect slide-level structure rather than patch independence.
  • The method supports multiple slide-level tasks and organ types, pointing to a general-purpose augmentation module for digital pathology.
  • Because augmentation happens in latent space, it can be plugged into existing MIL models without retraining the feature extractor or relabeling.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

  • If conditioning truly encodes visual semantics in the embedding, HistAug could enable counterfactual exploration of which visual features drive slide-level diagnosis, a use beyond data augmentation.
  • The uniform WSI-wise augmentation result hints that correlating augmentations across patches within a slide may preserve slide-level distribution; a testable extension is comparing uniform vs. per-patch policies on additional tasks.
  • The mechanism may transfer to other gigapixel-scale weakly supervised problems (e.g., satellite imagery) where patch embeddings are pooled, as long as a transformation-conditioned generative model can be trained in that embedding space.
  • A natural stress test is to replace the learned transformation codes with random codes; if gains persist, the controllability claim weakens, revealing that diversity rather than semantics drives improvement.
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Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Referee Report

2 major / 1 minor

Summary. The posted abstract describes HistAug, a generative model for controllable feature-space augmentation in MIL-based digital pathology, claiming improved performance across multiple slide-level tasks and organs, especially in low-data regimes, while processing many patches in a single forward pass. However, the full body of the submission is an unrelated hardware/software paper titled "An Open-Source HW-SW Co-Development Framework Enabling Efficient Multi-Accelerator Systems" (SNAX, arXiv:2508.14582) by a different author group. None of the HistAug method, experiments, tables, or ablations appear in the submitted document, so the abstract's claims cannot be audited.

Significance. If HistAug works as claimed, it would be a valuable and inexpensive contribution to weakly supervised digital pathology: controllable latent-space augmentation without raw-patch processing or relabeling, with potential gains in low-data regimes. The claimed single-forward-pass processing of many patches would address a practical bottleneck. The abstract's explicit mention of ablations and a public code link are strengths in principle. However, the significance is entirely conditional: the submission provides no architecture, conditioning mechanism, loss function, or validation to support the claims.

major comments (2)
  1. [Full text (Sections I–VII)] The submitted full text is the SNAX multi-accelerator HW-SW framework paper (arXiv:2508.14582) by Antonio et al.; it has no connection to HistAug. The abstract's claim of "Experiments across multiple slide-level tasks and diverse organs" and "Ablation studies confirm..." is not supported by any section, table, or equation in the document. This mismatch is load-bearing: none of the central claims can be checked, and the manuscript cannot be reviewed in its current form.
  2. [Abstract] Even taking the abstract as the only source, the method is underspecified: no generative model architecture, conditioning mechanism for hue/erosion transformations, training objective, or semantic-preservation criterion is given. The claimed efficiency (single forward pass for many patches) and superiority over noise-based perturbations have no accompanying experimental protocol, datasets, or baselines. These are essential to the central claim, not presentation details.
minor comments (1)
  1. [Abstract (code link)] The code URL is stated, but no documentation or repository contents are provided in the manuscript; the link cannot substitute for a methods/experiments section. Also, the full-text header's arXiv ID (2508.14582) differs from the submission's ID (2508.14588), suggesting a submission-integrity problem that should be corrected.

Circularity Check

0 steps flagged · score 0.0 of 10

No circular derivation can be found because the posted full text is an unrelated hardware paper; the HistAug abstract is unauditable as submitted.

full rationale

The submission consists of an abstract describing HistAug, a latent-space augmentation method for digital pathology, followed by a full text that is actually a hardware/software co-design paper titled 'An Open-Source HW-SW Co-Development Framework Enabling Efficient Multi-Accelerator Systems' (arXiv:2508.14582), by a different author team (Antonio et al., KU Leuven). There is no method section, no generative model, no conditioning mechanism, no loss function, no augmentation equation, and no MIL evaluation in the provided document. Consequently, there is no derivation chain to audit for circularity. In particular, the abstract's key claims—'By conditioning on explicit patch-level transformations (e.g., hue, erosion), HistAug generates realistic augmented embeddings while preserving initial semantic information' and 'consistently improving MIL model performance'—cannot be checked against any equations or experimental procedure. The reviewing rule requires flagging missing support; that is done here. However, the absence of a derivational structure is not itself evidence of circularity. No specific reduction of a prediction to its own input, no fitted parameter renamed as a prediction, and no load-bearing self-citation chain can be quoted from the posted artifact. Under the hard rule that circularity may only be claimed when the paper's own text exhibits the reduction, the appropriate score is 0. This is an unverdict on circularity, not a positive validation of HistAug's substance; the posted artifact is simply the wrong document for the claimed contribution.

Assumptions & free parameters 2 free parameters · 3 assumptions · 1 invented entities

This ledger is provisional and almost certainly incomplete: a full audit requires the actual HistAug manuscript, which the submission does not contain. The entries capture what is inferable from the abstract alone.

free parameters (2)
  • HistAug generative model weights = not stated in abstract
    The method is a trained generative model; its parameters are fit to the patch embedding distribution and are load-bearing for the realism of generated augmentations, but the abstract gives no training details.
  • Transformation conditioning vectors and magnitudes (hue, erosion) = not stated in abstract
    The central mechanism is conditioning on explicit patch-level transformations; how each transform is encoded, scaled, and combined is absent from the abstract.
assumptions (3)
  • domain assumption Latent-space editing can faithfully represent explicit visual transformations while preserving semantics
    Abstract premise: HistAug 'generates realistic augmented embeddings while preserving initial semantic information.' No method text is present to check this.
  • domain assumption Feature-level augmentation transfers to slide-level MIL performance
    The abstract's whole empirical program assumes gains in the embedding space improve the downstream slide-level classifier; this transfer is asserted, not demonstrated in the available text.
  • domain assumption Prior feature-level augmentation methods lack control over transformation semantics
    Motivating gap statement in the abstract; the cited literature that would support it is absent because the body text belongs to another paper.
invented entities (1)
  • Transformation-conditioned latent augmentation operator (HistAug)
    purpose: Generates augmented patch embeddings for MIL training conditioned on explicit transforms
    Internal model component; the abstract offers no falsifiable prediction outside the training and evaluation loop.

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Cite this review

Pith. "Pith review of Controllable Latent Space Augmentation for Digital Pathology." pith.science (2026). https://pith.science/paper/J54LADDQ

@misc{pith2026250814588,
  author       = {Pith},
  title        = {Pith review of: Controllable Latent Space Augmentation for Digital Pathology},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/J54LADDQ}},
  note         = {Machine review of arXiv:2508.14588}
}
read the original abstract

Whole slide image (WSI) analysis in digital pathology presents unique challenges due to the gigapixel resolution of WSIs and the scarcity of dense supervision signals. While Multiple Instance Learning (MIL) is a natural fit for slide-level tasks, training robust models requires large and diverse datasets. Even though image augmentation techniques could be utilized to increase data variability and reduce overfitting, implementing them effectively is not a trivial task. Traditional patch-level augmentation is prohibitively expensive due to the large number of patches extracted from each WSI, and existing feature-level augmentation methods lack control over transformation semantics. We introduce HistAug, a fast and efficient generative model for controllable augmentations in the latent space for digital pathology. By conditioning on explicit patch-level transformations (e.g., hue, erosion), HistAug generates realistic augmented embeddings while preserving initial semantic information. Our method allows the processing of a large number of patches in a single forward pass efficiently, while at the same time consistently improving MIL model performance. Experiments across multiple slide-level tasks and diverse organs show that HistAug outperforms existing methods, particularly in low-data regimes. Ablation studies confirm the benefits of learned transformations over noise-based perturbations and highlight the importance of uniform WSI-wise augmentation. Code is available at https://github.com/MICS-Lab/HistAug.

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Works this paper leans on

35 extracted references · 31 canonical work pages

  1. [1]

    Cpu db: Recording microprocessor history: With this open database, you can mine microprocessor trends over the past 40 years

    A. Danowitz, K. Kelley, J. Mao, J. P. Stevenson, and M. Horowitz, “Cpu db: Recording microprocessor history: With this open database, you can mine microprocessor trends over the past 40 years.” Queue, vol. 10, no. 4, p. 10–27, apr 2012. [Online]. Available: https://doi.org/10.1145/2181796.2181798

    work page arXiv 2012

  2. [2]

    A survey on deep learning hardware accelerators for heterogeneous HPC platforms,

    C. Silvano, D. Ielmini, F. Ferrandi, L. Fiorin, S. Curzel, L. Benini, F. Conti, A. Garofalo, C. Zambelli, E. Calore, S. F. Schifano, M. Palesi, G. Ascia, D. Patti, S. Perri, N. Petra, D. D. Caro, L. Lavagno, T. Urso, V . Cardellini, G. C. Cardarilli, and R. Birke, “A survey on deep learning hardware accelerators for heterogeneous HPC platforms,” CoRR, vol...

    arXiv doi:10.48550/arxiv.2306.15552 2023

  3. [3]

    X-centric: A survey on compute-, memory- and application-centric computer architectures,

    S. Rheindt, T. Sabirov, O. Lenke, T. Wild, and A. Herkersdorf, “X-centric: A survey on compute-, memory- and application-centric computer architectures,” in Proceedings of the International Symposium on Memory Systems , ser. MEMSYS ’20. New York, NY , USA: Association for Computing Machinery, 2021, p. 178–193. [Online]. Available: https://doi.org/10.1145/...

    work page arXiv 2021

  4. [4]

    Agile soc development with open esp,

    P. Mantovani, D. Giri, G. Di Guglielmo, L. Piccolboni, J. Zuckerman, E. G. Cota, M. Petracca, C. Pilato, and L. P. Carloni, “Agile soc development with open esp,” in Proceedings of the 39th International Conference on Computer-Aided Design , ser. ICCAD ’20. New York, NY , USA: Association for Computing Machinery, 2020. [Online]. Available: https://doi.org...

    work page arXiv 2020

  5. [5]

    X-heep: An open-source, configurable and extendible risc-v microcontroller

    P. D. Schiavone, S. Machetti, M. Peon Quiros, J. A. Miranda Calero, B. W. Denkinger, C. T. Müller, R. Rodríguez Álvarez, S. Nasturzio, and D. Atienza Alonso, “X-heep: An open-source, configurable and extendible risc-v microcontroller.” New York, may 2023, p. 379–380. [Online]. Available: https://infoscience.epfl.ch/handle/20.500.14299/197196

    work page 2023

  6. [6]

    Gemmini: Enabling systematic deep-learning architecture evaluation via full-stack integration,

    H. Genc, S. Kim, A. Amid, A. Haj-Ali, V . Iyer, P. Prakash, J. Zhao, D. Grubb, H. Liew, H. Mao, A. Ou, C. Schmidt, S. Steffl, J. Wright, I. Stoica, J. Ragan-Kelley, K. Asanovic, B. Nikolic, and Y . S. Shao, “Gemmini: Enabling systematic deep-learning architecture evaluation via full-stack integration,” in 2021 58th ACM/IEEE Design Automation Conference (D...

    arXiv 2021

  7. [7]

    Aha: An agile approach to the design of coarse-grained reconfigurable accelerators and compilers,

    K. Koul, J. Melchert, K. Sreedhar, L. Truong, G. Nyengele, K. Zhang, Q. Liu, J. Setter, P.-H. Chen, Y . Mei, M. Strange, R. Daly, C. Donovick, A. Carsello, T. Kong, K. Feng, D. Huff, A. Nayak, R. Setaluri, J. Thomas, N. Bhagdikar, D. Durst, Z. Myers, N. Tsiskaridze, S. Richardson, R. Bahr, K. Fatahalian, P. Hanrahan, C. Barrett, M. Horowitz, C. Torng, F. ...

    2023

  8. [8]

    Dory: Automatic end-to-end deployment of real-world dnns on low-cost iot mcus,

    A. Burrello, A. Garofalo, N. Bruschi, G. Tagliavini, D. Rossi, and F. Conti, “Dory: Automatic end-to-end deployment of real-world dnns on low-cost iot mcus,” IEEE Transactions on Computers , vol. 70, no. 8, pp. 1253– 1268, 2021

    work page 2021

Show all 35 references
  1. [9]

    An analysis of accelerator coupling in heterogeneous architectures,

    E. G. Cota, P. Mantovani, G. Di Guglielmo, and L. P. Carloni, “An analysis of accelerator coupling in heterogeneous architectures,” in Proceedings of the 52nd Annual Design Automation Conference , ser. DAC ’15. New York, NY , USA: Association for Computing Machinery,

  2. [10]

    Efficient interaction between os and architecture in heterogeneous platforms,

    S. Srinivasan, L. Zhao, R. Illikkal, and R. Iyer, “Efficient interaction between os and architecture in heterogeneous platforms,” SIGOPS Oper. Syst. Rev. , vol. 45, no. 1, p. 62–72, Feb. 2011. [Online]. Available: https://doi.org/10.1145/1945023.1945032

    2011

  3. [11]

    Xpulpnn: Accelerating quantized neural networks on risc-v processors through isa extensions,

    A. Garofalo, G. Tagliavini, F. Conti, D. Rossi, and L. Benini, “Xpulpnn: Accelerating quantized neural networks on risc-v processors through isa extensions,” in 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE) , 2020, pp. 186–191

    2020

  4. [12]

    Snitch: A tiny pseudo dual-issue processor for area and energy efficient execution of floating- point intensive workloads,

    F. Zaruba, F. Schuiki, T. Hoefler, and L. Benini, “Snitch: A tiny pseudo dual-issue processor for area and energy efficient execution of floating- point intensive workloads,” IEEE Transactions on Computers , 2020

    2020

  5. [13]

    Spatz: A compact vector processing unit for high-performance and energy-efficient shared-l1 clusters,

    M. Cavalcante, D. Wüthrich, M. Perotti, S. Riedel, and L. Benini, “Spatz: A compact vector processing unit for high-performance and energy-efficient shared-l1 clusters,” in Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design , ser. ICCAD ’22. New...

    2022

  6. [14]

    A 45nm 1.3ghz 16.7 double-precision gflops/w risc-v processor with vector accelerators,

    Y . Lee, A. Waterman, R. Avizienis, H. Cook, C. Sun, V . Stojanovi ´c, and K. Asanovi ´c, “A 45nm 1.3ghz 16.7 double-precision gflops/w risc-v processor with vector accelerators,” in ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC) , 2014, pp. 199–202

    2014

  7. [15]

    Tic- sat: Tightly-coupled systolic accelerator for transformers,

    A. Amirshahi, J. A. Harrison Klein, G. Ansaloni, and D. Atienza, “Tic- sat: Tightly-coupled systolic accelerator for transformers,” in 2023 28th Asia and South Pacific Design Automation Conference (ASP-DAC) , 2023, pp. 657–663

    2023

  8. [16]

    Xnor neural engine: A hardware accelerator ip for 21.6-fj/op binary neural network inference,

    F. Conti, P. D. Schiavone, and L. Benini, “Xnor neural engine: A hardware accelerator ip for 21.6-fj/op binary neural network inference,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 37, no. 11, p. 2940–2951, Nov. 2018. [Online]. Availabl...

    2018

  9. [17]

    A 12nm agile-designed soc for swarm-based perception with heterogeneous ip blocks, a reconfigurable memory hierarchy, and an 800mhz multi-plane noc,

    T. Jia, P. Mantovani, M. C. Dos Santos, D. Giri, J. Zuckerman, E. J. Loscalzo, M. Cochet, K. Swaminathan, G. Tombesi, J. J. Zhang, N. Chandramoorthy, J.-D. Wellman, K. Tien, L. Carloni, K. Shepard, D. Brooks, G.-Y . Wei, and P. Bose, “A 12nm agile-designed soc for swarm-based ...

    2022

  10. [18]

    Research on nvidia deep learning accelerator,

    G. Zhou, J. Zhou, and H. Lin, “Research on nvidia deep learning accelerator,” in 2018 12th IEEE International Conference on Anti- counterfeiting, Security, and Identification (ASID) , 2018, pp. 192–195

    2018

  11. [19]

    Decoupled access/execute computer architectures,

    J. E. Smith, “Decoupled access/execute computer architectures,” in Proceedings of the 9th Annual Symposium on Computer Architecture , ser. ISCA ’82. Washington, DC, USA: IEEE Computer Society Press, 1982, p. 112–119

    1982

  12. [20]

    Nvidia a100 tensor core gpu: Performance and innovation,

    J. Choquette, W. Gandhi, O. Giroux, N. Stam, and R. Krashinsky, “Nvidia a100 tensor core gpu: Performance and innovation,” IEEE Micro, vol. 41, no. 2, pp. 29–35, 2021

    2021

  13. [21]

    An analysis of accelerator data-transfer modes in noc-based soc architectures,

    K.-L. Chiu, D. Giri, L. Piccolboni, and L. P. Carloni, “An analysis of accelerator data-transfer modes in noc-based soc architectures,” in 2023 IEEE High Performance Extreme Computing Conference (HPEC) , 2023, pp. 1–7

    2023

  14. [22]

    Channel transfers and transactions,

    ARM, “Channel transfers and transactions,” 2024, accessed: 2024-11-14. [Online]. Available: https://developer.arm.com/documentation/102202/ 0300/Channel-transfers-and-transactions

    2024

  15. [23]

    A fully-synthesizable single-cycle interconnection network for shared-l1 processor clusters,

    A. Rahimi, I. Loi, M. R. Kakoee, and L. Benini, “A fully-synthesizable single-cycle interconnection network for shared-l1 processor clusters,” in 2011 Design, Automation & Test in Europe , 2011, pp. 1–6

    2011

  16. [24]

    Zigzag: Enlarging joint architecture-mapping design space exploration for dnn accelerators,

    L. Mei, P. Houshmand, V . Jain, S. Giraldo, and M. Verhelst, “Zigzag: Enlarging joint architecture-mapping design space exploration for dnn accelerators,” IEEE Transactions on Computers, vol. 70, no. 8, pp. 1160– 1174, 2021

    2021

  17. [25]

    Opengemm: A high-utilization gemm accelerator generator with lightweight risc-v control and tight memory coupling,

    X. Yi, R. Antonio, J. Dumoulin, J. Sun, J. V . Delm, G. Paim, and M. Verhelst, “Opengemm: A high-utilization gemm accelerator generator with lightweight risc-v control and tight memory coupling,” 2024. [Online]. Available: https://arxiv.org/abs/2411.09543

    2024 arXiv

  18. [26]

    Roofline: An insightful visual performance model for multicore architectures,

    S. Williams, A. Waterman, and D. Patterson, “Roofline: An insightful visual performance model for multicore architectures,” Communications of the ACM , vol. 52, no. 4, pp. 65–76, Apr. 2009

    2009

  19. [27]

    14.5 a 12nm linux-smp-capable risc-v soc with 14 accelerator types, distributed hardware power management and flexible noc-based data orchestration,

    M. C. Dos Santos, T. Jia, J. Zuckerman, M. Cochet, D. Giri, E. J. Loscalzo, K. Swaminathan, T. Tambe, J. J. Zhang, A. Buyuktosunoglu, K.-L. Chiu, G. D. Guglielmo, P. Mantovani, L. Piccolboni, G. Tombesi, D. Trilla, J.-D. Wellman, E.-Y . Yang, A. Amarnath, Y . Jing, B. Mishra, ...

    2024

  20. [28]

    A 16mm2 106.1 gops/w heterogeneous risc-v multi-core multi-accelerator soc in low-power 22nm finfet,

    A. Gonzalez, J. Zhao, B. Korpan, H. Genc, C. Schmidt, J. Wright, A. Biswas, A. Amid, F. Sheikh, A. Sorokin, S. Kale, M. Yalamanchi, R. Yarlagadda, M. Flannigan, L. Abramowitz, E. Alon, Y . S. Shao, K. Asanovi ´c, and B. Nikoli ´c, “A 16mm2 106.1 gops/w heterogeneous risc-v mul...

    2021

  21. [29]

    Siracusa: A low-power on-sensor risc-v soc for extended reality visual processing in 16nm cmos,

    M. Scherer, M. Eggimann, A. D. Mauro, A. S. Prasad, F. Conti, D. Rossi, J. T. Gómez, Z. Li, S. S. Sarwar, Z. Wang, B. D. Salvo, and L. Benini, “Siracusa: A low-power on-sensor risc-v soc for extended reality visual processing in 16nm cmos,” in ESSCIRC 2023- IEEE 49th European ...

    2023

  22. [30]

    Ultra-low-power with fpu arm cortex-m4 mcu 120 mhz with 2048 kbytes of flash memory, usb otg, dfsdm, chrom-art,

    S. Microelectronics, “Ultra-low-power with fpu arm cortex-m4 mcu 120 mhz with 2048 kbytes of flash memory, usb otg, dfsdm, chrom-art,” 2024, accessed: 2024-11-14. [Online]. Available: https: //www.st.com/en/microcontrollers-microprocessors/stm32l4r5zi.html

  23. [31]

    Mlperf tiny benchmark results v1.0,

    TinyML, “Mlperf tiny benchmark results v1.0,” 2024, accessed: 2024-11-14. [Online]. Available: https://mlcommons.org/benchmarks/ inference-tiny/

    2024

  24. [32]

    Gap-9 processor,

    Greenwaves, “Gap-9 processor,” 2024, accessed: 2024-11-14. [Online]. Available: https://greenwaves-technologies.com/gap9_processor/

    2024

  25. [33]

    Diana: An end-to-end hybrid digital and analog neural network soc for the edge,

    P. Houshmand, G. M. Sarda, V . Jain, K. Ueyoshi, I. A. Papistas, M. Shi, Q. Zheng, D. Bhattacharjee, A. Mallik, P. Debacker, D. Verkest, and M. Verhelst, “Diana: An end-to-end hybrid digital and analog neural network soc for the edge,” IEEE Journal of Solid-State Circuits , vo...

    2023

  26. [34]

    Htvm: Efficient neural network deployment on heterogeneous tinyml platforms,

    J. Van Delm, M. Vandersteegen, A. Burrello, G. M. Sarda, F. Conti, D. J. Pagliari, L. Benini, and M. Verhelst, “Htvm: Efficient neural network deployment on heterogeneous tinyml platforms,” in 2023 60th ACM/IEEE Design Automation Conference (DAC) . IEEE, Jul. 2023, p. 1–6. [On...

    2023

  27. [2015]

    Available: https://doi.org/10.1145/2744769.2744794

    [Online]. Available: https://doi.org/10.1145/2744769.2744794

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Reviewed August 5, 2026 · model on record in the stance chip above.