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arxiv: 2605.19405 · v3 · pith:J57STKHOnew · submitted 2026-05-19 · 💻 cs.AR

A complete discussion on fully reconfigurable, digital, scalable, graph and sparsity-aware near-memory accelerator for graph neural networks

Siddhartha Raman Sundara Raman , Lizy John , Jaydeep P. Kulkarni This is my paper

Pith reviewed 2026-06-30 17:53 UTC · model grok-4.3

classification 💻 cs.AR
keywords graph neural networksprocessing-in-memorynear-memory acceleratorsparsity-aware architecturereconfigurable computingGNN accelerationenergy-efficient hardware
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The pith

NEM-GNN uses a DAC/ADC-less near-memory design to accelerate graph neural networks with early termination and sparsity-aware aggregation.

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The paper presents NEM-GNN as a processing-in-memory architecture tailored for the combination and aggregation stages of graph neural networks. Conventional processors incur high energy costs from moving irregular sparse graph data, while prior accelerators face limits from analog components and fixed structures. NEM-GNN avoids DACs and ADCs entirely, adds early compute termination, reconfigurable pre-computation, and a compute-as-soon-as-ready broadcast model to perform aggregation near memory. A sympathetic reader would see this as a route to running larger GNN workloads on specialized hardware with far lower power draw.

Core claim

NEM-GNN is a scalable processing-in-memory architecture that eliminates DACs and ADCs, applies early compute termination and reconfigurable system-on-chip pre-computation, and uses a compute-as-soon-as-ready broadcast model for graph- and sparsity-aware near-memory aggregation, yielding 80-230x higher performance, 80-300x higher throughput, 850-1134x better energy efficiency, and 7-8x higher compute density than prior state-of-the-art approaches.

What carries the argument

The compute-as-soon-as-ready (CAR) and broadcast-based execution model for graph- and sparsity-aware near-memory aggregation.

If this is right

  • GNN workloads can execute with orders-of-magnitude lower energy than on CPUs, GPUs, or prior accelerators.
  • The absence of DAC/ADC circuits allows higher compute density and better scaling to larger graphs.
  • Early termination and CAR execution reduce wasted work on irregular sparse data.
  • Reconfigurable pre-computation supports both dense convolution and sparse aggregation in one fabric.

Where Pith is reading between the lines

These are editorial extensions of the paper, not claims the author makes directly.

  • The reconfigurable elements may support adaptation to new GNN variants without full hardware respins.
  • The near-memory approach could extend to other sparse workloads such as recommendation systems or scientific simulations.
  • Integration of the CAR model with existing memory hierarchies might reduce the need for custom silicon in future chips.

Load-bearing premise

The reported performance and energy numbers reflect complete comparisons that include all reconfiguration, control, and data-movement overheads.

What would settle it

A side-by-side measurement of NEM-GNN against a prior accelerator on the same platform that accounts for every overhead and yields speedups below 10x would disprove the performance claims.

Figures

Figures reproduced from arXiv: 2605.19405 by Jaydeep P. Kulkarni, Lizy John, Siddhartha Raman Sundara Raman.

Figure 1
Figure 1. Figure 1: Undirected, unweighted graph with 5 nodes and 6 edges passing through 1-layer GCN. Combination showing MAC between dense feature and weight matrices, aggregation showing MAC between sparse D-1, adjacency matrices to generate final MAC before ReLU, softmax function Attention Networks (GAT), and GraphSage [32], [33], are being extensively researched. These explorations are geared towards unraveling specific … view at source ↗
Figure 2
Figure 2. Figure 2: Landscape of Graph neural network based acceleration. The prior works are predominantly dedicated accelerators requiring periodic host-accelerator interaction. These are further classified into Von-Neumann, ReRAM based PIM, DRAM/HBM based PIM. The proposed accelerator is not dedicated and reuses cache in CPUs to perform GCNs. The bitcells for PIM designs are also shown the BL to half of the operating volta… view at source ↗
Figure 3
Figure 3. Figure 3: a) ReRAM approaches (i) use DAC for incoming H conversion to an equivalent analog value (ii) store weights of GNN in binary scaled fashion (iii) utilize current buffer+reductor to perform current-based summation and ADC to generate H*W b) Qualitative comparison between ReRAM approaches and NEM-GNN c) A summary of the identified issues and the proposed solutions execution between combination and aggregation… view at source ↗
Figure 4
Figure 4. Figure 4: a) NEM-GNN is realized by repurposing the L1 cache for in-memory compute, with minimal near-memory peripheral logic added to each CPU core. b) In an L1 cache, consisting of 2 banks, shift and add are present at a granularity of 1 per every 8 columns per bank, with 1 adder reduc￾tion/multiplier per bank, and other dedicated logic shared across the entire cache. c) DRAM is accessed to transfer weights/ featu… view at source ↗
Figure 5
Figure 5. Figure 5: a) Compute array organization for NEM-C1: 2 tiles with 4 banks in each tile, with bit-serial PIM performed between H mapped onto RWL and W replicated across both tiles is shown for illustration. 2-bit 8-element H and 1-bit 8*3 weight matrix is shown with Hji n indicating nth bit of j th element for ith node. b) W is stored in 8T SRAM bitcell in L1 cache, and H is mapped onto RWL. RBL discharge is used as a… view at source ↗
Figure 6
Figure 6. Figure 6: NEM-C2: Early compute termination (ECT) occurs once one of the bit-serial H element bits is found to be 1, without data replication requirement. ECT data path checks for non-zero H bit in step 1 and writes the non-zero dot product into ECT register in step 2. In parallel, PIM datapath computes partial dot products in step 1 and subsequently stores them in the ECT register in step 2. This value is broadcast… view at source ↗
Figure 7
Figure 7. Figure 7: Incoming graphs are mapped onto different engines based on graph-connectivity (graph-aware) and read-out of adjacency matrix (stored in Compressed Sparse Row Format) to eliminate unnecessary compute (sparsity-aware). UWC engine: Aggregation of unweighted graphs by reading the adjacency matrix and NodeProc register (indicating the node being processed by combination) to fill the update index register in ste… view at source ↗
Figure 8
Figure 8. Figure 8: a) UWC engine: Aggregation for an unweighted, directed graph begins with reading the adjacency vector corresponding to Node Proc in Step 1, identifying outgoing nodes in step 2, and storing in Update Index register, using adders to aggregate the incoming combination vector onto the nodes in Update Index register in step 3. Each adjacency matrix element is of the form (i,j), where i/j represents the neighbo… view at source ↗
Figure 9
Figure 9. Figure 9: a) Weighted, directed aggregation, with adjacency matrix storing the weights of graphs and the direction in the case of directed graphs. The direction is read out in step 1 to check for outgoing nodes in step 2 and aggregation with the incoming combination vector is achieved using near-memory multipliers and adders in step 3 b) Weighted, undirected aggregation follows the same datapath as the directed one,… view at source ↗
Figure 10
Figure 10. Figure 10: D-generator and control logic: Degree matrix generator for generating D-1 using a sparsity-aware approach that (i) performs element-by-vector (instead of vector-by-vector) mul￾tiplication for every row, and (ii) reduces the number of computations/area by a factor of 2n/n. Auxiliary control for ReLU and softmax is shown in the right-most figure. undergoes immediate updates. This update involves the accumul… view at source ↗
Figure 11
Figure 11. Figure 11: Benchmarks: Datasets for GNNs, the number of nodes/edges/features in each of them, and the network used for GCN/GAT/GraphSage networks. Micro-architecture of NEM-GNN with the additional near-memory logic requiring 2% of AMD’s Zen3 CPU per-core area 6.2 Graph and sparsity-aware WC engine for Weighted graphs For weighted graphs, the adjacency matrix (A) is re-purposed to store the weight of interaction betw… view at source ↗
Figure 12
Figure 12. Figure 12: Performance comparison normalized to NEM-C3 for GCN, GAT and GraphSage. UWC engine is used for aggregation, NEM-C1, NEM-C2, and NEM-C3 are used for combination [PITH_FULL_IMAGE:figures/full_fig_p019_12.png] view at source ↗
Figure 13
Figure 13. Figure 13: Throughput comparison measured in GOPS for GCN, GAT, and GraphSage. UWC engine is used for aggregation, NEM-C1, NEM-C2, and NEM-C3 are used for combination. Tesla v100, with 64 CUDA cores per streaming multiprocessor (SM) and an operating frequency of 1.5GHz, with 96KB L1 cache per SM, 6MB L2 cache and 16GB HBM2. AWB-GCN’s performance is obtained from its implementation on Intel D5005 FPGA with DRAM capac… view at source ↗
Figure 14
Figure 14. Figure 14: Energy comparison for GCN, GAT and GraphSage. UWC engine is used for aggregation, NEM-C1, NEM-C2, and NEM-C3 are used for combination [PITH_FULL_IMAGE:figures/full_fig_p021_14.png] view at source ↗
Figure 15
Figure 15. Figure 15: Energy efficiency comparison for GCN, GAT and GraphSage. UWC engine is used for aggregation, NEM-C1, NEM-C2, and NEM-C3 are used for combination. the lower power. In comparison to ReFLIP, NEM-GNN has the following advantages: (i) No power￾hungry DAC/ADC requirements (ii) Lower write/read voltages for SRAM than ReRAM (iii) No additional write required to store back into the compute array post combination r… view at source ↗
Figure 16
Figure 16. Figure 16: a) Compute density comparison across PIM designs b) NEM-C2 performance variation with number of Hs c) NEM-C2 energy variation with bit resolution, average bit-position for first ’1’ d) Compute density, area for CS1, CS2 and CS3 e) Energy, efficiency for CS1, CS2, and CS3 [PITH_FULL_IMAGE:figures/full_fig_p022_16.png] view at source ↗
Figure 17
Figure 17. Figure 17: a) Performance/b) energy improvement of NEM-C3 relative to PIM-GCN, c) Speedup/energy improvement relative to Challapalle et.al, d) Speedup, e) Energy of NEM-C3 relative to PEDAL to NEM-C1 based design. The compute density is ∼7-8x that of ReFLIP, due to the elimination of bulky DACs/ADCs, no data replication, and sparsity-aware compute. Design space exploration: The performance of NEM-C2 varies roughly l… view at source ↗
Figure 18
Figure 18. Figure 18: a) Execution time/energy requirement/energy inefficiency of designs relative to NEM-C3 for a) Reddit dataset, b) Twitter dataset. UA means unavailable mainly because PIM-GCN faces challenges in hiding additional latency for performing CAM to identify neighbors in the scheduling policy, whereas it performs better for larger datasets. This results in speedups of ∼ 76x-105x, as depicted in Fig. 17a). Similar… view at source ↗
read the original abstract

Graph neural networks (GNNs) have gained significant interest for applications such as citation network analysis and drug discovery due to their ability to apply machine learning techniques on graph-structured data. GNNs typically employ a two-stage execution pipeline consisting of combination and aggregation kernels. The combination stage performs data-intensive convolution operations with relatively regular memory access patterns, whereas the aggregation stage operates on sparse graph data with highly irregular accesses. These heterogeneous memory behaviors make conventional CPU- and GPU-based execution energy inefficient due to substantial data movement overheads. Existing accelerators attempt to mitigate these challenges using specialized architectures and processing-in-memory (PIM) techniques. However, prior approaches often suffer from scalability limitations, area overheads, restricted parallelism, and energy inefficiencies associated with analog compute and dedicated accelerator structures. This paper presents NEM-GNN, a scalable DAC/ADC-less processing-in-memory architecture for graph neural network acceleration. The proposed design introduces early compute termination mechanisms, pre-computation using reconfigurable system-on-chip components, and graph- and sparsity-aware near-memory aggregation using a compute-as-soon-as-ready (CAR) and broadcast-based execution model. Experimental results demonstrate that NEM-GNN achieves approximately 80--230x higher performance, 80--300x higher throughput, 850--1134x better energy efficiency, and 7--8x higher compute density compared to prior state-of-the-art approaches.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit. Tearing a paper down is the easy half of reading it; the pith above is the substance, this is the friction.

Referee Report

2 major / 2 minor

Summary. The manuscript proposes NEM-GNN, a fully reconfigurable, digital, scalable, graph- and sparsity-aware near-memory accelerator for GNNs. It introduces early compute termination mechanisms, pre-computation using reconfigurable SoC components, and graph/sparsity-aware near-memory aggregation via a compute-as-soon-as-ready (CAR) and broadcast-based execution model in a DAC/ADC-less PIM fabric. The central claim, supported by experimental results, is that NEM-GNN delivers approximately 80--230x higher performance, 80--300x higher throughput, 850--1134x better energy efficiency, and 7--8x higher compute density versus prior state-of-the-art approaches.

Significance. If the reported speedups and efficiency gains are shown to incorporate the full costs of the proposed mechanisms, the work would constitute a meaningful contribution to digital PIM architectures for irregular workloads, offering a scalable alternative to analog and fixed-structure accelerators while addressing data-movement bottlenecks in GNN combination and aggregation stages.

major comments (2)
  1. [Experimental Results] Experimental Results section: the headline quantitative claims (80--230x performance, 850--1134x energy efficiency) rest on the assumption that all reconfiguration, control, and data-movement overheads of the CAR execution model, reconfigurable SoC pre-computation, and broadcast mechanisms are included in the cycle-accurate or analytical models; the section provides no explicit validation or breakdown demonstrating this, which directly undermines the apples-to-apples comparison with baselines.
  2. [§4] §4 (or equivalent evaluation subsection): no description is given of the benchmark selection, input graph characteristics, error bars, or the precise modeling of PIM fabric control logic costs; without these, the 7--8x compute-density claim cannot be assessed as load-bearing evidence.
minor comments (2)
  1. [Abstract] Abstract: the performance numbers are stated without any reference to methodology, benchmarks, or validation approach, reducing immediate clarity.
  2. [Introduction / Architecture] Notation for CAR and broadcast model: the description in the introduction and architecture sections would benefit from a small diagram or pseudocode to clarify the timing of 'as-soon-as-ready' decisions relative to sparsity patterns.

Simulated Author's Rebuttal

2 responses · 0 unresolved

We appreciate the referee's detailed review and constructive feedback on our manuscript. We address the major comments below and will revise the paper to incorporate additional details and clarifications as requested.

read point-by-point responses

  1. Referee: [Experimental Results] Experimental Results section: the headline quantitative claims (80--230x performance, 850--1134x energy efficiency) rest on the assumption that all reconfiguration, control, and data-movement overheads of the CAR execution model, reconfigurable SoC pre-computation, and broadcast mechanisms are included in the cycle-accurate or analytical models; the section provides no explicit validation or breakdown demonstrating this, which directly undermines the apples-to-apples comparison with baselines.

    Authors: We thank the referee for highlighting this important point. Our cycle-accurate simulator and analytical models do account for the reconfiguration, control, and data-movement overheads associated with the CAR execution model, reconfigurable SoC pre-computation, and broadcast mechanisms. These costs are modeled based on the hardware implementation details provided in Sections 3 and 4. However, to make this explicit and strengthen the comparison, we will add a dedicated subsection in the Experimental Results section that provides a breakdown of these overheads and validation against the baseline models. This will ensure transparency in the apples-to-apples comparison. revision: yes

  2. Referee: [§4] §4 (or equivalent evaluation subsection): no description is given of the benchmark selection, input graph characteristics, error bars, or the precise modeling of PIM fabric control logic costs; without these, the 7--8x compute-density claim cannot be assessed as load-bearing evidence.

    Authors: We agree that additional details on the evaluation methodology are necessary for full assessment of the results. In the revised manuscript, we will expand Section 4 (or the evaluation subsection) to include: (1) a detailed description of the benchmark selection criteria and the characteristics of the input graphs used (e.g., number of nodes, edges, sparsity levels), (2) error bars or statistical measures from multiple runs where applicable, and (3) a precise description of how the PIM fabric control logic costs are modeled in our simulations, including area and energy estimates. This will provide the necessary context to evaluate the 7--8x compute-density claim. revision: yes

Circularity Check

0 steps flagged

No circularity: architecture paper with experimental claims, no derivation chain or fitted parameters

full rationale

The paper describes a hardware architecture (NEM-GNN) and reports empirical speedups/energy numbers from experiments against prior SOTA. No equations, fitted parameters, self-definitional steps, or load-bearing self-citations appear in the abstract or description. Claims rest on external benchmark comparisons rather than reducing to inputs by construction. This matches the default expectation of no significant circularity for non-mathematical papers.

Axiom & Free-Parameter Ledger

0 free parameters · 0 axioms · 0 invented entities

Abstract-only review supplies no information on free parameters, axioms, or invented entities.

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Forward citations

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