Pith. sign in

REVIEW 4 major objections 6 minor 43 references

Accelerating Transistor-Level Simulation of Integrated Circuits via Equivalence of RC Long-Chain Structures

T0 review · 4 major / 6 minor · reviewed 2026-08-06 · deepseek-v4-flash

Challenge this review Re-run · record.json Download PDF Read on arXiv ↗ Review JSON

Pith's one-line read This paper proves that the current entering a uniform RC long chain is exactly fixed by the port voltage and the chain length through a closed-form admittance $Y_n(\omega)$, and uses that equivalence to delete chain interior nodes…

desk verdict Real but modest RC-chain reduction with a verification gap in the benchmark claims; deserves review, not a pass. read the letter →

arxiv 2508.13159 v1 pith:JDN3AQBF submitted 2025-07-16 cs.AR cs.PF

Ruibai Tang , Wenlai Zhao This is my paper · ORCID
classification cs.ARcs.PF
keywords transistor-levelsimulationRClongchainfrequency-domainequivalencetimeconstantreductiontransientanalysiscircuitaccelerationnodeelimination
verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

Transistor-level simulation of integrated circuits is slow because every time step requires factoring a large sparse matrix. The paper identifies a recurring substructure in real circuits: long chains built from identical resistors and grounded capacitors, which occupy on average 6.34% of the nodes. It derives an exact frequency-domain equivalence for such chains: the current entering the chain is determined solely by the port voltage and the chain length through an admittance $Y_n(\omega)$. From that equivalence it obtains three reduction rules for small, intermediate, and large time constants. If the equivalence holds, the interior nodes of these chains can be collapsed, shrinking the simulation matrix and speeding up transient analysis by 8.8% on average (up to 22%) with 0.7% relative error on standard benchmark circuits.

What carries the argument

The central object is the RC long chain: a path of $n$ equal resistors, with every node grounded through an equal capacitor, terminating in a closed end. Its behaviour is carried by the port admittance $Y_n(\omega)$, the ratio of input current to port voltage in the frequency domain, obtained by solving the KCL recurrence with characteristic roots $a$ and $b$. The paper evaluates the inverse Fourier transform with a Gaussian envelope $e^{-M^2t^2}$ to guarantee convergence, and enforces causality either by forcing $V_0$ to vanish after the time step or by replacing $Y_n$ with its causal version via a Hilbert transform. A numerically stable form $H_n(\omega)$ is introduced to compute $Y_n$ without cancellation. These pieces turn the chain into a one-port element whose current can be written directly from $V_0$, which is what allows the interior nodes to be eliminated.

What would settle it

Take any benchmark circuit's original netlist and the simplified netlist produced by the paper's chain deletion, and list every edge incident to a deleted interior node; if any such edge connects to a MOSFET terminal or to a node outside the chain, the deletion changes the circuit beyond the claimed load equivalence. A direct test is to modify one circuit so that an interior chain node drives a transistor gate, rerun the transient simulation, and check whether the output waveform moves by more than the claimed 0.7% relative error.

Watch

Extended reading notes

Core claim

The central claim is that a uniform RC long chain—$n$ identical resistors $R$ in series with $n+1$ identical grounded capacitors $C$—has a port behaviour completely captured by the admittance $Y_n(\omega)$ in equation (6), so the current $I(t)$ into the chain is a function only of the port voltage $V_0$ and the length $n$. Solving the KCL equations by Fourier transform gives a second-order recurrence whose characteristic roots yield this closed form. Depending on how the time constant $\tau=RC$ compares with the simulation time step, the paper derives three regimes: for small $\tau$, all nodes charge together and $I(t)\approx (n+1)C\,dV_0/dt - \frac{n(n+1)}{2}RC^2\,d^2V_0/dt^2$ (equation 17); for large $\tau$, only the first two nodes respond and the rest of the chain contributes negligibly (equation 19); for $\tau$ of the same order as the time step, the paper proposes an $m$-order recurrence in past currents and voltages as a conceptual direction, without a full implementation. The benchmark simplification deletes all interior chain nodes and replaces the port capacitor by $(n+1)C$. On the benchmark circuits, this yields an average 8.8% speedup (up to 22%) with 0.7% relative error, with the largest gains on circuits whose chains hold the largest share of nodes.

Load-bearing premise

The method assumes every interior node of a detected chain is a pure two-terminal link—connected only to its two chain neighbours through equal resistors and to ground through a capacitor—with no gate, drain, or other branch attached, and the benchmark experiments do not explicitly verify this property for the chains they simplified.

Editorial extensions

If this is right

  • For small time constants, each chain can be replaced by a single port node with capacitance $(n+1)C$, removing $n$ nodes and their resistors from the simulation matrix.
  • For large time constants, only the first two nodes of the chain matter; the remaining nodes can be discarded without appreciable error.
  • For time constants comparable to the simulation step, a recurrence over past currents and voltages would extend the reduction into the regime where node-elimination methods are not reliable.
  • The speedup on a given circuit grows with the share of nodes held in chains; circuits without such chains show no improvement.
  • The reduction is a preprocessing step, so it composes with any downstream sparse solver and does not change the numerical integration scheme.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

  • A natural extension: because $Y_n(\omega)$ depends only on $n$, $R$, and $C$, a simulator could precompute it for every chain length in a netlist and turn the reduction into a lookup rather than a per-chain derivation.
  • The same-order recurrence is a short-memory approximation of the convolution with $Y_n$; if implemented, it could be combined with node-elimination methods to reduce chains that currently fall outside both approaches' regimes.
  • Because the reported speedup tracks the split ratio, the method should give larger gains on power grids, clock trees, or interconnect-dominated netlists where RC chains are denser than in these benchmarks.
  • The weighted relative-error metric used in the paper downweights near-zero current samples; circuits dominated by long quiet periods may show larger per-point deviations than the 0.7% average, so the error number should be read as a weighted aggregate, not a worst case.
Share X Bluesky LinkedIn Reddit HN

Signed reviews

No signed human review yet.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Referee Report

4 major / 6 minor

Summary. The paper studies uniform RC ladder networks ('long chains') attached to a core circuit at one port. It derives an exact frequency-domain admittance Y_n(ω) by solving the KCL recurrence, then proposes three approximations according to the time-constant regime: small (Eq. 17), same order (Eq. 18), and large (Eq. 19). The paper validates the small- and large-regime approximations on synthetic RC chains in Ngspice and applies a chain reduction to ISCAS-85 benchmarks, reporting an average 8.8% speedup and 0.7% relative error. The same-order method is explicitly left as future work.

Significance. The exact closed-form admittance for the uniform RC ladder is a useful theoretical result and is derived without fitting parameters. The asymptotic formulas for small and large time constants are physically plausible and receive synthetic validation. The benchmark study addresses a real performance bottleneck, and the code is open-sourced. However, the central empirical claims are currently weakened by an unverified chain-reduction procedure and by the gap between the abstract's 'three methods' and the two implemented regimes; the significance is contingent on addressing these issues.

major comments (4)
  1. [Section 5.2, Table 8] The reported 8.8%/0.7% result rests on replacing each chain by a single grounded capacitor (n+1)C at the chain head. This replacement is exact only when every deleted interior node is a pure two-terminal ladder node with exactly two resistive connections and one capacitor to ground, and with no gate, drain, source, or other branch touching it. The paper does not specify the chain-detection algorithm used to build *_simp.net, does not state that it verifies the absence of side connections at every deleted node, and remaps output nodes inside chains to V(chain_start). Consequently, the comparison does not measure voltages at deleted output nodes, and the claimed 0.7% relative error could mask large local errors. Please specify the detector, verify the purity of all deleted nodes (or handle impure chains), and report errors at the original output nodes.
  2. [Abstract and Section 4.4] The abstract and the contribution list claim three reduction methods, but Section 4.4 explicitly states that the same-order method (Eq. 18) is only a conceptual direction with no implementation or accuracy analysis, and Section 5 confirms that experiments cover only Eq. (17) and Eq. (19). The claim of 'three methods' is therefore not supported by the reported work. Either implement and evaluate Eq. (18) or revise the abstract and contributions to report two demonstrated methods plus a proposed extension.
  3. [Section 5.1] For the small-time-constant case with EXP input, the reported relative errors are on the order of 10^-1 for n≤64. The paper attributes this to 'differing discretization strategies' without providing evidence. Since the abstract's accuracy claim is unqualified, this large error should be explained quantitatively, or the scope of Eq. (17) should be restricted, for example to smooth inputs with bounded derivatives.
  4. [Section 4.5] The decision rule uses hand-picked parameters α=10 and m=⌊n/2⌋ for n>64, and the Gaussian width M in Eq. (7) is given only as a range. No sensitivity analysis is provided showing how accuracy and speedup vary with these choices, and no selection criterion is given for M within its stated range. Please add a sensitivity study or justify these choices from the error analysis.
minor comments (6)
  1. [Abstract] The phrase 'our methods yields' should be corrected to 'our methods yield'.
  2. [Section 3.3] The sentence 'all resistors in these chains have the same resistance value of 0.953316Ω' appears to refer specifically to c1355, while the following sentence says values vary from circuit to circuit; clarify that the numerical values are for c1355 or state the per-circuit uniformity differently.
  3. [Section 4.1] The definitions of F_n(s) and G_n(s) involve integrals over all ω, while the numerical evaluation truncates to |λ|≤25; state the truncation error bound or justify the cutoff.
  4. [Section 4.4] The expansion leading to the recurrence with γ_k and β_k omits the definition of I^(k) and the transition to the final recurrence is not derived; since this is explicitly future work, mark the equations as tentative or provide the omitted derivation.
  5. [Section 4.5] The condition 's/α ≤ τ_c ≤ α·d' mixes the simulation step s and the elapsed time d; clarify whether the upper bound should involve d or s and why the regime boundary depends on total simulated time.
  6. [Section 5.2, Table 8] c3540 and c7552 have exactly zero error despite c3540 having a nonzero split ratio; explain why (for example, no observed output lies inside a reduced chain), otherwise the zero entries appear to be placeholders.

Circularity Check

0 steps flagged · score 0.0 of 10

No significant circularity: the exact port admittance and the small/large-time-constant reduction formulas are derived from KCL and explicit asymptotic expansions, with no fitted input renamed as a prediction.

full rationale

The derivation chain is self-contained. Equation (6) follows algebraically from the KCL recurrence (1) and the closed-terminal boundary condition, so the statement that the entering current is determined by the port voltage and chain length is a solved result rather than an assumed one. The small-tau formula (17) and large-tau formula (19) are obtained from the n=1 convolution solution (12) under stated scale assumptions (tau << s and tau >> elapsed time d), with the threshold alpha=10 explicitly chosen rather than tuned to the reported speedups or errors. The only coefficients that would be fitted to a waveform class, gamma_k and beta_k in equation (18), belong to the same-order method, and Section 4.4 states this is only a conceptual direction 'without delving into its detailed implementation or accuracy analysis, which we leave as future work'; equation (18) is not used in either evaluation. The benchmark results in Section 5.2 are external measurements obtained by simulating the original Ngspice netlists and the reduced netlists and comparing their outputs and runtimes, so the 8.8% speedup and 0.7% error are not forced by a fitted quantity. The simplified netlist in Section 5.2 replaces a chain by (n+1)C at the head, which is only the leading term of (17); whether dropping the higher-order term is accurate is a modeling-error question, not a circular one. The limitations that do appear are validation rather than circularity concerns: Section 5.2 does not specify the chain-detection algorithm used to build *_simp.net, and the replacement of a deleted output node's expression by the chain-head voltage changes the quantity being compared; both are reproducibility and verification gaps for the empirical claim, not reductions of the mathematical derivation to its inputs. No load-bearing self-citation or imported uniqueness theorem is present; external references such as TICER [29], KLU [11], and the ISCAS-85 benchmarks [5] are used as independent sources.

Assumptions & free parameters 4 free parameters · 5 assumptions · 0 invented entities

The central derivation has no fitted constants; the free parameters are engineering thresholds and one future-work coefficient set. The main axioms are the ideal chain structure and the linear-port-voltage approximation.

free parameters (4)
  • alpha threshold for time-constant regimes = 10
    Section 4.5 sets the boundary between small, same-order, and large time constants at alpha=10 without derivation; this determines when Eq. (17) is applied.
  • Gaussian damping parameter M = M in [1, 1e-6/s]; used as 1e4 in experiments
    Introduced in Section 4 to make Fourier integrals convergent; affects F_n(s) and G_n(s), although the final asymptotic formulas are not very sensitive.
  • recurrence coefficients gamma_k, beta_k = not determined; to be pre-computed per input waveform class
    Eq. (18), the same-order method, requires coefficients fit to the expected V0 waveform (SIN/PULSE); not implemented and left as future work.
  • reduced chain length m for n>64 = floor(n/2) or ceil(log2 n)
    Section 4.5 recommends solving a shorter chain for n>64 to balance error and elimination; not used in the benchmark tests.
assumptions (5)
  • standard math Kirchhoff's current law and the Fourier derivative identity FT(dV/dt)=j omega FT(V)
    Used to transform the chain ODE system into the algebraic recurrence in Eq. (4).
  • domain assumption All chain resistors have equal resistance R and all chain capacitors have equal capacitance C
    Eq. (1) and the characteristic-root solution (5) require uniformity; Section 3.3 reports this holds for the benchmark chains.
  • domain assumption Interior chain nodes have no connections to the rest of the circuit besides the two series resistors and the grounded capacitor
    The two-port admittance model in Eq. (6) is only valid if the chain is electrically isolated from the core except at V0; Section 3.3's decomposition implies this but the detection algorithm is not given.
  • ad hoc to paper The port voltage V0(t) is approximately linear over one simulation step and can be extended with a Gaussian envelope for Fourier inversion
    Eq. (7) introduces this approximation to make the F_n(s) and G_n(s) integrals converge; it is an engineering approximation, not an exact identity.
  • domain assumption For benchmark circuits the Ngspice time step s satisfies tau_c < s/alpha with alpha=10 for every reduced chain
    This is the stated validity condition for Eq. (17) in Section 4.5, but Section 5.2 does not report the adaptive time steps actually used.

how reviews work

0 comments
Cite this review

Pith. "Pith review of Accelerating Transistor-Level Simulation of Integrated Circuits via Equivalence of RC Long-Chain Structures." pith.science (2026). https://pith.science/paper/JDN3AQBF

@misc{pith2026250813159,
  author       = {Pith},
  title        = {Pith review of: Accelerating Transistor-Level Simulation of Integrated Circuits via Equivalence of RC Long-Chain Structures},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/JDN3AQBF}},
  note         = {Machine review of arXiv:2508.13159}
}
read the original abstract

Transistor-level simulation plays a vital role in validating the physical correctness of integrated circuits. However, such simulations are computationally expensive. This paper proposes three novel reduction methods specifically tailored to RC long-chain structures with different scales of time constant. Such structures account for an average of 6.34\% (up to 12\%) of the total nodes in the benchmark circuits. Experimental results demonstrate that our methods yields an average performance improvement of 8.8\% (up to 22\%) on simulating benchmark circuits which include a variety of functional modules such as ALUs, adders, multipliers, SEC/DED checkers, and interrupt controllers, with only 0.7\% relative error.

Discussion (0). Continue with ORCID to comment.

Reference graph

Works this paper leans on

43 extracted references · 37 canonical work pages

  1. [1]

    Charalampos Antoniadis, Nestor Evmorfopoulos, and Georgios Stamoulis. 2019. A Rigorous Approach for the Sparsification of Dense Matrices in Model Order Reduction of RLC Circuits. In ���� ���� �������� ������ ���������� ���������� �����. 1–6

    work page 2019

  2. [2]

    Charalampos Antoniadis, Nestor Evmorfopoulos, and Georgios Stamoulis. 2019. Efficient sparsification of dense circuit matrices in model order reduction. In ����������� �� ��� ���� ���� ��� ����� ������ ������ ���������� ���������� (Tokyo, Japan) ������� ����. Association for Computing Machinery, New York, NY, USA, 255–260. doi:10.1145/3287624.3287658

    work page arXiv 2019

  3. [3]

    Janos Benk, Georg Denk, and Konrad Waldherr. 2017. A holistic fast and par- allel approach for accurate transient simulations of analog circuits. ������� �� ����������� �� ��������7, 1 (2017)

    work page 2017

  4. [4]

    C. W. Bomhof and H. A. van der Vorst. 2000. A parallel linear system solver for circuit simulation problems. ��������� ������ ������� ���� ������������7, 7-8 (2000), 649–665. doi:10.1002/1099-1506(200010/12)7:7/8<649::AID-NLA217>3.0. CO;2-W

    work page doi:10.1002/1099-1506(200010/12)7:7/8 2000

  5. [5]

    Franc Brglez and Hideo Fujiwara. 1985. A neutral netlist of 10 combinational benchmark circuits and a targeted translator in FORTRAN

    work page 1985

  6. [6]

    M. E. Brinson and S. Jahn. 2009. Qucs: A GPL software package for circuit simulation, compact device modelling and circuit macromodelling from DC to RF and beyond. ���� �� ������ ������22, 4 (July 2009), 297–319

    work page 2009

  7. [7]

    Cadence Design Systems. [n. d.]. �������. https://www.cadence.com/en_US/ home/tools/custom-ic-analog-rf-design/circuit-simulation.html

    work page

  8. [8]

    Xiaoming Chen, Yu Wang, and Huazhong Yang. 2012. Parallel Circuit Simula- tion on Multi/Many-core Systems. In ���� ���� ���� ������������� �������� ��� ����������� ���������� ��������� ��������� � ��� �����. IEEE, 2530–2533

    work page 2012

Show all 43 references
  1. [9]

    Kang Cheng, Zuochang Ye, and Wenjian Yu. 2012. Model Order Reduction for Large Scale RC Networks Based on Optimal Elimination. ������� �� ��������� ����� ������ � �������� ��������24, 11 (2012), 1506–1512. https://www.jcad. cn/cn/article/id/f2529738-ccf9-4d88-8725-90e3050a8e24

    2012

  2. [10]

    Timothy A. Davis. 2004. Algorithm 832: UMFPACK V4.3—an unsymmetric- pattern multifrontal method. ��� ������ ����� ������30, 2 (June 2004), 196–199. doi:10.1145/992200.992206

    2004

  3. [11]

    Davis and Natarajan

    Timothy A. Davis and Natarajan. 2010. Algorithm 907 - KLU, A Direct Sparse Solver for Circuit Simulation Problems. ��� ������ ����� ��������37, 3 (2010), 1–17

    2010

  4. [12]

    Thornquist Eric R

    Heidi K. Thornquist Eric R. Keiter, Richard L. Schiek. 2013. Xyce( � ) Parallel Electronic Simulator. [Computer Software] https://doi.org/10.11578/dc.20171025

    2013 doi

  5. [13]

    Axel Feldmann and Daniel Sanchez. 2023. Spatula: A Hardware Accelerator for Sparse Matrix Factorization. In ����������� �� ��� ���� ������ �������� ������������� ��������� �� �����������������(Toronto, ON, Canada) ������ ����. Association for Computing Machinery, New York, NY,...

    2023

  6. [15]

    Hansen, Hakan Yalcin, and John P

    Mark C. Hansen, Hakan Yalcin, and John P. Hayes. 1999. Unveiling the ISCAS-85 Benchmarks: A Case Study in Reverse Engineering. ���� ���� ����16, 3 (July 1999), 72–80. doi:10.1109/54.785838

    1999 doi

  7. [16]

    Limin Hao and Guoyong Shi. 2021. High-Dimensional Extension of the TICER Algorithm. ���� ������������ �� �������� ��� ������� �� ������� ������68, 11 (2021), 4722–4734. doi:10.1109/TCSI.2021.3106390

    2021

  8. [17]

    Hutchinson, E.R

    S.A. Hutchinson, E.R. Keiter, and R.J. Hoekstra. 2000. The Xyce Parallel Electronic Simulator - An Overview. Sandia National Lab. (SNL-NM), Albuquerque, NM (United States); Sandia National Lab. (SNL-CA), Livermore, CA (United States)

    2000

  9. [18]

    Jeremy Johnson, Timothy Chagnon, Petya Vachranukunkiet, Prawat Nagvajara, and Chika Nwankpa. 2008. Sparse LU decomposition using FPGA. (01 2008)

    2008

  10. [19]

    Nachiket Kapre and Andre DeHon. 2009. Parallelizing sparse Matrix Solve for SPICE circuit simulation using FPGAs. In ���� ������������� ���������� �� ������������������ ����������. IEEE, 190–198

    2009

  11. [20]

    K.S. Kundert. 1986. Sparse matrix techniques and their applications to circuit simulation.. In ������� ��������� ����������� ��� ������. A. E. Ruehli Ed. North- Holland, New York

    1986

  12. [21]

    Kundert and A Sangiovanni-Vincentelli

    K.S. Kundert and A Sangiovanni-Vincentelli. 1988. ������ ������ ������ ���. Tech- nical Report. Tech. rep., Dept. of EE and CS, UC Berkeley

    1988

  13. [22]

    Zhiqiang Liu, Wenjian Yu, and Zhuo Feng. 2022. feGRASS: Fast and Effective Graph Spectral Sparsification for Scalable Power Grid Analysis.���� ������������ �� �������������� ������ �� ���������� �������� ��� �������41, 3 (2022), 681–694. doi:10.1109/TCAD.2021.3060647

    2022

  14. [23]

    Nagel and D.O

    Laurence W. Nagel and D.O. Pederson. 1973. ����� ����������� ������� ���� ���������� ������� ���������. Technical Report UCB/ERL M382. http://www2. eecs.berkeley.edu/Pubs/TechRpts/1973/22871.html

    1973

  15. [24]

    Ngspice. [n. d.]. ������������� ����. https://ngspice.sourceforge.io/docs.html

  16. [25]

    Odabasioglu, M

    A. Odabasioglu, M. Celik, and L.T. Pileggi. 1998. PRIMA: passive reduced-order interconnect macromodeling algorithm. ���� ������������ �� �������������� ������ �� ���������� �������� ��� �������17, 8 (1998), 645–654. doi:10.1109/43. 712097

    1998 doi

  17. [26]

    Denis Oyaro and Piero Triverio. 2016. TurboMOR-RC: An Efficient Model Order Reduction Technique for RC Networks With Many Ports. ���� ������������ �� �������������� ������ �� ���������� �������� ��� �������35, 10 (2016), 1695–1706. doi:10.1109/TCAD.2016.2531046

    2016

  18. [27]

    He Peng and Chung-Kuan Cheng. 2009. Parallel transistor level circuit simulation using domain decomposition methods. In ���� ���� ��� ����� ������ ������ ���������� ����������. 397–402. doi:10.1109/ASPDAC.2009.4796513

    2009

  19. [28]

    B.N. Sheehan. 1999. TICER: Realizable reduction of extracted RC circuits. In ���� �������� ������������� ���������� �� �������������� ������� ������ �� ��������� ������ ����� �������������. 200–203. doi:10.1109/ICCAD.1999.810649

    1999

  20. [29]

    Bernard N. Sheehan. 2007. Realizable Reduction of RC Networks. ���� �������� ����� �� �������������� ������ �� ���������� �������� ��� �������26, 8 (2007), 1393–1407. doi:10.1109/TCAD.2007.891374

    2007

  21. [30]

    Siemens. [n. d.]. ���� ��������. https://eda.sw.siemens.com/en-US/ic/eldo/

  22. [31]

    M. Sipics. 2007. Sparse matrix algorithm drives SPICE performance gains. ���� ���� ��� �� ��(2007)

    2007

  23. [32]

    Spielman and Nikhil Srivastava

    Daniel A. Spielman and Nikhil Srivastava. 2011. Graph Sparsification by Effective Resistances. ���� �� ������� 40, 6 (2011), 1913–1926. arXiv:https://doi.org/10.1137/080734029 doi:10.1137/080734029

    2011 doi

  24. [33]

    Spielman and Shang-Hua Teng

    Daniel A. Spielman and Shang-Hua Teng. 2008. Spectral Sparsification of Graphs. ���� abs/0808.4134 (2008). arXiv:0808.4134 http://arxiv.org/abs/0808.4134

    2008 arXiv

  25. [34]

    Synopsys. [n. d.]. ������. https://www.synopsys.com/implementation-and- signoff/ams-simulation/primesim-hspice.html

  26. [35]

    Robert Tarjan. 1972. Depth-First Search and Linear Graph Algorithms. ���� �� ������� 1, 2 (1972), 146–160. arXiv:https://doi.org/10.1137/0201010 doi:10.1137/ 0201010

    1972 doi

  27. [36]

    Leyun Tian, Yuyang Ye, and Hao Yan. 2022. GNN-based TICER for RC Reduction on Large-scale Interconnect. In ���� ���� ���� ������������� ���������� �� ������ ����� � ���������� ������� ���������� ��������. 1–3. doi:10.1109/ICSICT55466. 2022.9963409

    2022

  28. [37]

    Jingye Xu and Masud Chowdhury. 2010. Circuit Level Issues of Interconnect Pipelining in Nanoscale Integrated Circuits. ����� ��� �����������2 (06 2010), ������ ���� ��� ������ ���� 52–64. doi:10.2174/1876402911002020052

    2010 doi

  29. [38]

    Fan Yang, Xuan Zeng, Yangfeng Su, and Dian Zhou. 2007. RLCSYN: RLC Equiv- alent Circuit Synthesis for Structure-Preserved Reduced-order Model of Inter- connect. In ���� ���� ������������� ��������� �� �������� ��� ������� �������. 2710–2713. doi:10.1109/ISCAS.2007.378521

    2007

  30. [39]

    Phillips

    Zuochang Ye, Dmitry Vasilyev, Zhenhai Zhu, and Joel R. Phillips. 2008. Sparse Implicit Projection (SIP) for reduction of general many-terminal networks. In ���� �������� ������������� ���������� �� �������������� ������. 736–743. doi:10.1109/ICCAD.2008.4681658

    2008

  31. [40]

    Yibin Zhang, Zhiqiang Liu, and Shan Shen. 2024. Spectral Sparsity Model Reduc- tion Method for IC Post Simulation. In ����� �������� ������� ���� ���������� ���� �����

    2024

  32. [41]

    Zijia Zhang, Dan Niu, Zhou Jin, Pengju Chen, Zhenya Zhou, and Changyin Sun

  33. [42]

    Xueqian Zhao, Zhuo Feng, and Cheng Zhuo. 2014. An efficient spectral graph sparsification approach to scalable reduction of large flip-chip power grids. In ���� �������� ������������� ���������� �� �������������� ������ �������. 218–223. doi:10.1109/ICCAD.2014.7001355

    2014

  34. [43]

    Yuchao Zhong, Yunfan Zuo, Leyun Tian, Sen Hu, and Hao Yan. 2024. CGAT- TICER: A Compressed GAT-based TICER for RC Reduction. 155–159. doi:10. 1109/ISEDA62518.2024.10617713

    2024

  35. [1421]

    doi:10.11578/dc.20171025.1421

Pith tools

Reviewed August 6, 2026 · model on record in the stance chip above.