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Fault-tolerant Quantum Computation without Distillation on a 2D Device

T0 review · 2 major / 4 minor · reviewed 2026-08-11 · deepseek-v4-flash

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Pith's one-line read The paper shows that a looped pipeline architecture can implement a fault-tolerant non-Clifford CCZ gate on a 2D device, at a current time cost about twice that of magic-state distillation.

desk verdict A careful and honest architecture mapping for Brown's linear-time CCZ on a looped pipeline, with a resource comparison that favors distillation but rests on an extrapolated distance estimate. read the letter →

arxiv 2412.12529 v2 pith:JIUARMJX submitted 2024-12-17 quant-ph

Thomas R. Scruby , Kae Nemoto , Zhenyu Cai This is my paper · ORCID
classification quant-ph
keywords loopedpipelinearchitecturesurfacecodesnon-CliffordgateCCZjust-in-timedecodingmagicstatedistillationquantumerrorcorrectionqubitshuttling
verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

This paper establishes that a looped pipeline architecture—physical qubits shuttled in synchronised loops, with several qubits per loop forming stacked arrays—can implement the fault-tolerant, linear-time CCZ gate between three 2D surface codes. The shuttling schedule needed is only slightly more involved than the one already used for a standard surface code in the same architecture. The paper then compares this no-distillation route to magic-state distillation for the same architecture and finds that, at current decoder performance, distillation is about twice as fast in time at the target error rate $P_{\mathrm{ccz}} \sim 3 \times 10^{-10}$, with comparable or better space use. The bottleneck is the just-in-time decoder, which forces very large code distances; the paper argues that this decoder has been little studied and could improve substantially.

What carries the argument

The load-bearing object is the looped pipeline architecture: qubits circulate clockwise around fixed shuttling loops in synchrony, and placing multiple qubits per loop stacks independent layers of a code without extra hardware. Inter-loop interactions realise intra-layer stabiliser checks, while intra-loop interactions realise transversal gates between layers, giving effective 3D connectivity on a 2D chip. The second ingredient is the linear-time CCZ gate, which reorders the transversal CCZ of three 3D surface codes so each qubit experiences the same sequence—initialise, measure $Z$ stabilisers, apply physical CCZ, measure out—but slices of the 3D codes are processed one by one in time. Fault tolerance is supplied by just-in-time decoding, which guesses the syndrome of the corresponding 3D code at each timestep; the paper's architecture adds a three-step slice cycle and code-deformation stages for in-place operation.

What would settle it

A full circuit-level Monte Carlo simulation of the complete three-slice linear-time CCZ protocol at distances 50 through 100, measuring the logical CCZ error rate at $p = 5 \times 10^{-4}$, would settle whether the distance needed for $P_{\mathrm{ccz}} \sim 3 \times 10^{-10}$ is near 100 or far below it.

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Extended reading notes

Core claim

The central claim is that a strictly 2D device with short-range shuttling loops can run the linear-time CCZ gate of Ref. [6] using the same physical operations as multiple planar surface codes: short-range shuttling on fixed paths, single- and two-qubit gates, and single-qubit Pauli measurements. The implementation maps three different 2D layer codes (a standard square-lattice surface code and two mirrored kagome-lattice codes) and their two-layer 3D slices onto loops of a single grid, with intra-loop interactions supplying transversal operations between layers and inter-loop interactions supplying stabiliser measurements within layers. A three-step slice cycle (two full loop cycles plus a half-cycle ancilla shift) measures all needed $Z$ stabilisers. Resource estimates for a 2048-bit factoring workload put the in-place gate at roughly 700 code cycles and a $5d \times 10d$ footprint, versus about 330 cycles for a CCZ distillation factory placed in the same corridor, so magic-state distillation is about twice as fast at $P_{\mathrm{ccz}} \sim 3 \times 10^{-10}$; the gap narrows to about 1.5x at $P_{\mathrm{ccz}} \sim 10^{-7}$. The paper attributes the overhead almost entirely to the low threshold and poor sub-threshold scaling of the just-in-time decoder, not to the gate itself, and argues that improved decoders—or hybrid post-selection schemes—could change this balance.

Load-bearing premise

The resource comparison depends on the extrapolated estimate that the three-code gate needs a code distance near 100; if circuit-level noise demands much less (or much more), the factor-of-two time gap shrinks or grows accordingly.

Editorial extensions

If this is right

  • A looped pipeline device can host a fault-tolerant non-Clifford gate without changing the physical operation set of the surface code, only the shuttling schedule and some local constant-depth circuits.
  • At the target error rate for 2048-bit factoring, the in-place linear-time CCZ costs about 700 code cycles and a $5d \times 10d$ patch, while a CCZ distillation factory in the same space produces and teleports a gate in about 330 cycles.
  • Using linear-time CCZ to build factories instead of applying it in place gives a space overhead about 1.4 times larger and a time overhead about twice as large as distillation factories.
  • If the target CCZ error rate is relaxed to $10^{-7}$, the time gap shrinks to about 1.5x, and the space freed by the gate no longer accommodates a factory per three qubits.
  • Over asymptotically small error rates, the linear-time gate's exponential suppression for linear distance growth beats the exponential trial overhead of post-selection-based distillation, though not in the practical regime considered here.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

  • A circuit-level simulation of the full three-slice protocol would be the natural next test: if an optimised just-in-time decoder approaches standard surface-code thresholds, the factor-of-two gap likely closes or reverses.
  • The same intra-loop transversal interaction mechanism could be used for other transversal operations among stacked codes, potentially reducing the cost of Clifford factories or enabling new code-deformation routines beyond CCZ.
  • The architecture's value may lie less in replacing distillation today than in providing a fallback universal gate set for platforms where shuttling is cheap and magic-state routing is expensive; the paper's own numbers quantify that trade-off.
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Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Referee Report

2 major / 4 minor

Summary. The paper proposes a concrete implementation of Brown's linear-time CCZ gate (Ref. [6]) on a looped pipeline architecture, giving a detailed shuttling schedule, a mapping of the three surface-code layers and slices onto shuttling loops, and code-deformation procedures for converting standard rotated surface-code patches into the required lattices. It then compares the space-time cost of this in-place CCZ gate with the cost of magic state distillation for a large-scale factoring scenario (2048-bit RSA, N=6000 logical qubits), concluding that distillation is currently faster by roughly a factor of two and that the gap is dominated by the performance of the just-in-time decoder. The paper is explicitly framed as a resource study rather than a claim of practical advantage for the non-distillation approach.

Significance. If the construction is correct, the manuscript provides a concrete architectural blueprint for fault-tolerant non-Clifford gates on a 2D device without magic state distillation, using only short-range shuttling, local gates, and measurements. The detailed mapping of the two-layer slices and the three-step stabiliser measurement schedule is a useful technical contribution, and the paper is commendably transparent about the limitations of its numerical extrapolation. The data underlying Fig. 12 are made available, and the simulations use publicly available code. The negative resource comparison is itself useful as a benchmark and identifies the JIT decoder as the main bottleneck. However, the quantitative factor-of-two speed advantage claimed for distillation is load-bearing and rests on an extrapolation that the authors themselves describe as unreliable, which limits the strength of the headline comparison.

major comments (2)
  1. [Sec. IV B, Fig. 12] The quantitative resource comparison (T'_lin = 7 d_ccz = 700 code cycles vs T_msd ≈ 330 code cycles, giving a factor-of-two speed advantage for magic state distillation) depends critically on the estimate d_ccz ~ 100. This value is obtained by a linear fit to five Monte Carlo points (L in the range 30 to 40) for a single red code under phenomenological noise, not for the full three-code CCZ gate or for the proposed shuttling schedule. The authors themselves state that this estimate is 'unreliable' and that the simulated slices in Ref. [31] are not the two-layer slices used in the construction. No circuit-level simulation of the full protocol is provided. If the true distance is larger, the distillation advantage grows; if it is smaller (e.g., d_ccz = 50), T'_lin becomes comparable to T_msd and the claimed factor-of-two disadvantage disappears. Since this factor is a central result of the paper, the estimate needs either a substantial strengthening (e.g., circuit-level or at least three-code simulations) or the quantitative claim should be removed and the comparison stated only qualitatively as 'currently in favour of distillation'.
  2. [Sec. III B and Sec. III C] The paper asserts in the introduction and Sec. III B that 'we thus expect the entire protocol to be fault-tolerant' based on the fault-tolerance proof for the JIT decoder in Ref. [6]. However, the specific implementation here differs from Ref. [6] in several ways: it uses two-layer slices of a different geometry, a three-step stabiliser measurement with a half-cycle advancement of inter-layer ancilla qubits, a compiled physical CCZ gate (six CNOTs), and the looped-pipeline shuttling schedule itself. No argument is given that the JIT decoding proof extends to these modifications, and no simulation covers the correlated XZZ errors that arise when an X error on one code passes through the physical CCZ to the other codes. The resource estimate implicitly assumes that the logical error rate of the full three-code gate is the same as that of the single-code phenomenological simulations. Please either provide a fault-tolerance argument for the exact schedule or explicitly state this as an additional unverified assumption and discuss how it would affect the resource comparison.
minor comments (4)
  1. [Introduction and Sec. II B] There is a repeated typo 'looped pipleline' in the introduction and Sec. II B; this should read 'looped pipeline'.
  2. [Sec. IV A] The expression T_msd = 230 + 2d + 3d with d = 21 gives 335 code cycles, not 330; please correct the arithmetic or explicitly round to 335.
  3. [Sec. V] In the example with target Pccz = 10^-7, the value d_ccz = 50 is introduced without explaining how it is obtained from Fig. 12; please either show the extrapolation or label this as an assumption.
  4. [Fig. 2 caption and Ref. [32]] In the caption of Fig. 2, 'pipeline /f_low direction' appears to be a LaTeX error and should read 'pipeline/flow direction'. Also, Ref. [32] has a doubled 'https://' in its URL.

Circularity Check

0 steps flagged · score 0.0 of 10

No circularity found: the linear-CCZ schedule and resource comparison are genuine constructions and quantitative estimates, not inputs renamed as predictions.

full rationale

The paper's derivation chain is not circular. The linear-time CCZ gate is taken from Brown's external work [6], and the looped-pipeline architecture from [11] is used as a prior hardware scheme; the new contribution is a concrete mapping of the three code slices onto that architecture with an explicit shuttling schedule. The cost formulas Tlin = 6 d_ccz and T'_lin = 7 d_ccz are bookkeeping from the described schedule (two code cycles for expansion, one for collapse/gate, 2 d_ccz steps), not fitted quantities. The distillation comparison uses external published data and formulas (Gidney and Ekerå [28], Fowler and Gidney [29], Gidney and Fowler [30]) with stated distances and cycle counts. The one input estimated from the authors' own numerical work, d_ccz ~ 100, is explicitly flagged as unreliable, is described as a lower bound, and the paper notes that larger values would only strengthen its conclusion that distillation is faster. Thus the central claim does not reduce to a self-citation or to a fitted parameter called a prediction; it is a falsifiable overhead comparison with clearly stated assumptions. The self-citations [11, 12, 31, 32] are used as prior architecture and code/data resources, not as an unverified uniqueness or correctness theorem that forces the conclusion, so they do not raise the circularity score.

Assumptions & free parameters 3 free parameters · 4 assumptions · 0 invented entities

The central resource conclusion rests on d_ccz ~ 100, a number obtained by fitting five Monte Carlo points, and on several domain assumptions about shuttling timing and decoder transfer. Nothing here is circular in the sense of assuming the conclusion, but the numerical estimate is a fitted quantity rather than a derived one, and the fault-tolerance carryover is asserted rather than proven.

free parameters (3)
  • d_ccz (linear CCZ code distance) = ~100
    Estimated by linear extrapolation of JIT decoder Monte Carlo data (Fig. 12) to Pccz ~ 3e-10 under phenomenological noise; the authors call the estimate unreliable and use it as a lower bound.
  • p (physical gate error rate) = 5e-4
    Chosen as a representative hardware error rate for the resource estimates; all derived distances, d = 21 and d1 = 13, scale with this choice.
  • phenomenological noise rate for JIT simulations = 4.67e-4
    Used in the Monte Carlo simulations in Fig. 12; no circuit-level noise model is used, so the connection between this rate and physical gate errors is an assumption.
assumptions (4)
  • domain assumption The fault-tolerance proof of the JIT decoder for the slices in Ref. [6] extends to the modified slices used in this paper.
    Sec. I says 'we thus expect the entire protocol to be fault-tolerant' based on Ref. [6]; no proof is given for the new lattice slices and shuttling schedule.
  • domain assumption The phenomenological noise simulations of a single red code are representative of the full three-code linear CCZ under circuit-level noise.
    This underpins the d_ccz ~ 100 estimate in Sec. IV B; the authors note that the simulated slices differ from the ones in the paper.
  • domain assumption Steps 2 and 3 of the slice stabilizer measurement together take about one code cycle, so the expand stage takes about two code cycles.
    Stated in Sec. III B 2, and used to derive Tlin = 6 d_ccz in Sec. III C; shuttling is assumed not to be the rate-limiting step.
  • standard math The standard surface code threshold formula Pcycle = 0.1(100p)^((d+1)/2) applies for setting the Clifford-operation code distance.
    Borrowed from Ref. [29] and used in Sec. IV A to set d = 21; this is an accepted numerical threshold formula in the literature.

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Cite this review

Pith. "Pith review of Fault-tolerant Quantum Computation without Distillation on a 2D Device." pith.science (2026). https://pith.science/paper/JIUARMJX

@misc{pith2026241212529,
  author       = {Pith},
  title        = {Pith review of: Fault-tolerant Quantum Computation without Distillation on a 2D Device},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/JIUARMJX}},
  note         = {Machine review of arXiv:2412.12529}
}
read the original abstract

We show how looped pipeline architectures - which use short-range shuttling of physical qubits to achieve a finite amount of non-local connectivity - can be used to efficiently implement the fault-tolerant non-Clifford gate between 2D surface codes described in (Sci. Adv. 6, eaay4929 (2020)). The shuttling schedule needed to implement this gate is only marginally more complex than is required for implementing the standard 2D surface code in this architecture. We compare the resource cost of this operation with the cost of magic state distillation and find that, at present, this comparison is heavily in favour of distillation. The high cost of the non-Clifford gate is almost entirely due to the relatively low performance of the just-in-time decoder used as part of this process, which necessitates very large code distances in order to achieve suitably low logical error rates. We argue that, as very little attention has previously been given to the study and optimisation of these decoders, there are potentially significant improvements to be made in this area.

Figures

Figures reproduced from arXiv: 2412.12529 by the authors.

Figure 1
Figure 1. FIG. 1. An example of three 3D surface code volumes which [PITH_FULL_IMAGE:figures/full_fig_p002_1.png] view at source ↗
Figure 2
Figure 2. FIG. 2. Five-qubit arrays implemented using different shut [PITH_FULL_IMAGE:figures/full_fig_p003_2.png] view at source ↗
Figure 3
Figure 3. FIG. 3. Interactions within layers are enabled by inter-loop [PITH_FULL_IMAGE:figures/full_fig_p004_3.png] view at source ↗
Figures from the paper (10 more)
Figure 4
Figure 4. Figure 4: FIG. 4. Layers and slices through each of the three codes + [PITH_FULL_IMAGE:figures/full_fig_p004_4.png]
Figure 5
Figure 5. Figure 5: FIG. 5. Mapping of the layers and slices from Fig. [PITH_FULL_IMAGE:figures/full_fig_p005_5.png]
Figure 6
Figure 6. Figure 6: FIG. 6. Pipelined implementation of the three 2D layers from [PITH_FULL_IMAGE:figures/full_fig_p006_6.png]
Figure 7
Figure 7. Figure 7: FIG. 7. Pipelined implementation of the three slices from [PITH_FULL_IMAGE:figures/full_fig_p007_7.png]
Figure 8
Figure 8. Figure 8: FIG. 8. Conversion of a distance-3 rotated surface code (thick [PITH_FULL_IMAGE:figures/full_fig_p008_8.png]
Figure 9
Figure 9. Figure 9: FIG. 9. Conversion of a distance-3 rotated surface code to the [PITH_FULL_IMAGE:figures/full_fig_p008_9.png]
Figure 10
Figure 10. Figure 10: FIG. 10. Conversion of a distance-3 rotated surface code to [PITH_FULL_IMAGE:figures/full_fig_p009_10.png]
Figure 11
Figure 11. Figure 11: FIG. 11 [PITH_FULL_IMAGE:figures/full_fig_p010_11.png]
Figure 12
Figure 12. Figure 12: FIG. 12. Logical [PITH_FULL_IMAGE:figures/full_fig_p010_12.png]
Figure 13
Figure 13. Figure 13: FIG. 13. Each patch here actually represents a stack of [PITH_FULL_IMAGE:figures/full_fig_p011_13.png]

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Forward citations

Cited by 1 Pith paper

Reviewed papers in the Pith corpus that reference this work. Sorted by Pith novelty score. Full citation record

  1. Planar fault-tolerant circuits for non-Clifford gates on the 2D color code

    quant-ph 2025-05 conditional novelty 8.0 of 10

    The paper constructs a family of planar fault-tolerant 'twisted color circuits' that implement logical T gates and magic-state measurements on the 2D color code via a path-integral and color-cohomology framework.

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Pith tools

Reviewed August 11, 2026 · model on record in the stance chip above.