Image Classification on IBM Quantum Computers

Hwidong Yoo; Jiook Cha; Junghoon Justin Park; Jun-gyeong Park; Kwangmin Yu

REVIEW 3 major objections 4 minor 32 references

Image Classification on IBM Quantum Computers

T0 review · 3 major / 4 minor · reviewed 2026-08-01 · deepseek-v4-flash

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Pith's one-line read A 12-qubit quantum classifier can run ten-class MNIST end-to-end on a current 127-qubit superconducting processor, with parallel circuit packing delivering a near-fourfold inference speedup at no mean accuracy cost.

desk verdict A solid, honestly-scoped feasibility study: the ten-class MNIST deployment on 127-qubit hardware holds up, but the 'no benefit to hardware fine-tuning' claim rests on a two-iteration null and should be softened. read the letter →

arxiv 2607.17705 v1 pith:JKEAA3QV submitted 2026-07-20 quant-ph

Junghoon Justin Park , Jiook Cha , Jun-gyeong Park , Hwidong Yoo , Kwangmin Yu This is my paper · ORCID

classification quant-ph

keywords quantummachinelearningimageclassificationmulti-programmingNISQvariationalclassifierMNISTtwo-phasetrainingIBMEagle

verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

This paper claims that ten-class MNIST image classification can be run end-to-end on a current 127-qubit superconducting quantum processor, and that a practical workflow for noisy intermediate-scale quantum devices is to train the quantum model on a classical simulator and reserve the quantum hardware for inference only. The authors show this by combining a two-phase training protocol that avoids the costly parameter-shift gradients of on-hardware training, a 12-qubit circuit selected from a five-ansatz comparison for its accuracy–compilation-cost trade-off, and Quantum Multi-Programming, which packs four copies of the trained circuit onto one device so that four samples are inferred per job submission. They report that QMP keeps mean test accuracy statistically unchanged while cutting job submissions fourfold and delivering a ~3.8–4x end-to-end speedup, and that two epochs of on-hardware fine-tuning do not measurably improve accuracy. The paper is careful to note that the quantum module shows no per-parameter accuracy advantage over a matched classical network at this scale, so it frames the result as a feasibility-and-workflow demonstration rather than a claim of quantum advantage.

What carries the argument

The load-bearing mechanism is the combination of a two-phase training protocol and Quantum Multi-Programming (QMP). Phase 1 trains only the classical encoder and readout with Adam on a noiseless simulator while the quantum parameters stay frozen at random initialization; Phase 2 optimizes only the 15 quantum parameters with the gradient-free COBYLA algorithm, either on a simulator or on hardware, avoiding the 2N circuit executions per step that parameter-shift gradients would require on a real device. QMP packs K identical logical circuits onto disjoint, routing-disconnected regions of the 127-qubit heavy-hex lattice; because no entangling gate crosses circuit boundaries, the joint state fac

What would settle it

Run the hybrid Phase 2 with all 20 COBYLA epochs on the quantum processor across the same three seeds and compare K=1 test accuracy against the simulator-only checkpoint: if the mean improves by more than approximately two test samples (about 2.7 percentage points), the paper's conclusion that on-hardware fine-tuning yields no measurable benefit is refuted.

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Extended reading notes

Core claim

On its own terms, the paper's central discovery is that a nontrivial 12-qubit parameterized quantum circuit can serve as the feature map of a ten-class image classifier executed on real IBM Eagle hardware, with a modest and stable accuracy cost: the same trained weights that score 79.11% on a noiseless simulator score 73.78% on the device, a hardware-noise penalty of 5.33 percentage points that reproduces across seeds. The second discovery is that Quantum Multi-Programming — packing K=4 copies of the 12-qubit circuit onto 48 physically separated qubits — is mathematically equivalent to serial execution in the noiseless limit and on hardware leaves the mean test accuracy unchanged within samp

Load-bearing premise

The load-bearing premise is that the absence of a measurable accuracy gain from two epochs of on-hardware COBYLA fine-tuning (tested on a 75-sample test set, three seeds, where the paper's own noise threshold is about two samples) justifies the recommendation to train on a simulator and use hardware only for inference; if more hardware epochs moved accuracy, that recommendation would collapse.

Editorial extensions

If this is right

If the workflow is correct, multi-class quantum image classification on current hardware is feasible without on-hardware training, removing the parameter-shift cost that has confined most hardware QML to binary tasks.
QMP gives a structural throughput gain for inference: with per-job overhead dominating wall time on cloud-accessed processors, packing K circuits reduces job submissions K-fold and delivers a near-K-fold speedup at no mean accuracy cost.
The null result for on-hardware fine-tuning implies that for small quantum parameter counts, the trained quantum circuit can be treated as a fixed nonlinear feature map, so simulator training plus hardware inference is the appropriate deployment pattern on NISQ devices.
The five-ansatz comparison with post-transpilation depth and CNOT counts provides a template for choosing classifier circuits for hardware deployment based on accuracy–cost trade-offs rather than accuracy alone.
Because the paper finds no per-parameter accuracy advantage over a matched classical MLP at this scale, the contribution is a controlled experimental template for isolating hardware noise, training location, and packing effects — a benchmark others can reuse.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

If the variance amplification seen at K=4 is dominated by per-day calibration drift across the four circuits, then averaging over multiple circuit assignments (or over more seeds) should recover the K=1 mean with a smaller standard error, making QMP effectively free at higher packing factors — a test the paper did not run.
The result that two hardware COBYLA epochs did not move accuracy suggests an even stronger conjecture: for these shallow circuits, the Phase-2 loss landscape is so flat that the classical encoder/readout alone determines the decision boundary. A direct test would be to train only the classical layers (no Phase 2 at all) and compare accuracy; the paper's flat Phase 2 curves already hint this would
The workflow of training on a noiseless simulator and deploying for inference on hardware transfers naturally to other NISQ-era learning tasks — kernel-based quantum models, quantum generative models, or hybrid models where the quantum circuit is a fixed feature map — as long as the circuit is small enough to simulate faithfully during training.
A testable extension: push QMP to K=8 or higher on the same device. The paper's factorization argument predicts the mean should stay within sampling noise; if instead a mean degradation appears, it would mark the onset of noise-driven cross-circuit interference that the current K=4 study cannot detect.

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Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Desk Editor's Note

read the letter

First, what to know: this paper actually runs ten-class MNIST on a 127-qubit Eagle, uses QMP to pack four identical 12-qubit circuits into one job, and does it with a controlled five-cell design that holds bit-identical weights across most contrasts. That is genuinely new in the hardware QML literature, which has mostly stopped at binary or low-accuracy multi-class. The central feasibility claim — a 12-qubit classifier running at 74–79% on real hardware — is supported. The QMP equivalence is derived from state factorization and verified to 1e-6 on a noiseless simulator; the matched-capacity classical baseline is an honest calibration; the negative results are framed as feasibility, not advantage. Credit where due: the experimental design, the seeded reproducibility, and the frank discussion of the 75-sample test set are all above average for this area.

The soft spots, in proportion:

1. The ansatz pilot selected VQC ZigZag using the same 75-sample test set that later appears in the headline table. That introduces a small optimistic bias in the architecture choice. It doesn't break the feasibility claim, but the reported accuracies are, strictly, post-selection. The authors should say this more plainly or re-measure on a fresh split.

2. The stress-test note is right about the fine-tuning null. The "train on simulator, deploy for inference only" workflow is the paper's most practically interesting recommendation, but it is built on two COBYLA hardware iterations per seed (epochs 19–20, B=20). The key contrast, Cell 2→4, is +3.11 pts, which is about 2 samples on a 75-sample test set — inside the paper's own noise threshold. Calling the conclusion "unambiguous" overstates what a three-seed, two-iteration null can support. A real fine-tuning benefit of similar size would not be detected. The recommendation should be softened or re-measured with more hardware iterations.

3. Minor: the wall-time speedup (3.76x vs 4x ceiling) comes from single runs without repeated-job error bars, and device load was not held fixed. The effect is large, so this is a detail, but worth a caveat.

Overall the paper is a serious, readable feasibility study. The main advertised result — that multi-class classification can run end-to-end on current hardware with QMP packing — holds. The workflow recommendation is appropriately conditional after the stress test, but that's a revision, not a rejection.

Who benefits: anyone working on QML hardware deployment, NISQ workflows, or QMP. I'd bring it to a reading group and I'd cite it as a state-of-the-art feasibility demonstration. It deserves a serious referee and, with revisions, publication.

Referee Report

3 major / 4 minor

Summary. This paper reports a hybrid classical-quantum classifier for ten-class MNIST executed end-to-end on a 127-qubit IBM Eagle processor. The main technical contributions are a two-phase training protocol (Adam on classical encoder/readout layers with frozen quantum parameters, followed by COBYLA optimization of quantum parameters), the first application of Quantum Multi-Programming (QMP) to a trained quantum classifier at K=4 packing, and a five-cell controlled comparison designed to isolate hardware noise, QMP packing effects, and on-hardware fine-tuning. The headline empirical claims are: a 12-qubit VQC reaches about 74–79% accuracy on hardware with a modest, reproducible noise penalty; QMP packing leaves mean accuracy statistically unchanged while amplifying cross-seed variance and reducing job submissions roughly fourfold; and two epochs of on-hardware COBYLA fine-tuning produce no measurable accuracy gain, motivating an inference-only deployment strategy. The paper also benchmarks against a matched-capacity classical MLP and finds no per-parameter quantum advantage, framing the contribution as a feasibility-and-workflow demonstration.

Significance. If the results hold, this is a useful feasibility-and-workflow result: it demonstrates a non-trivial multi-class quantum image classifier on current superconducting hardware, provides a clean shared-weight five-cell design that isolates hardware noise and packing effects, and gives a simple noiseless proof that QMP is equivalent to serial execution when no inter-circuit gates are applied. The matched-capacity classical baseline and the honest framing as a feasibility study are strengths. The central limitations are that the model-selection pilot and the final evaluation share the same 75-sample test set, and that the null result for on-hardware fine-tuning is probed by only two COBYLA hardware iterations per seed. These issues currently prevent the absolute accuracy numbers and the strong workflow recommendation from being taken at face value.

major comments (3)

[§3.2, Table 1; §3.1, Table 3] The model-selection pilot in §3.2 reports test accuracy on the Ntest=75 subset and selects VQC ZigZag as the highest-accuracy model. The five-cell evaluation in Table 3 then reports test accuracy on the same Ntest=75 subset. Because the test set has already been used to choose the architecture, the absolute accuracies in Table 3 and the comparison to the classical MLP in §4.5 are not unbiased estimates of generalization. This does not destroy the within-group cell contrasts, which compare bit-identical weights, but it is load-bearing for the feasibility claim that a 12-qubit classifier achieves 74–79% on ten-class MNIST. Please hold out a separate test set for final evaluation, or report the pilot selection metric on the validation set and reserve the test set for the final five-cell results.
[§4.4, §2.3.2] The claim that on-hardware fine-tuning yields no accuracy gain, described as 'unambiguous' in §4.4, is supported by only two COBYLA iterations per seed on the QPU (B=20, one iteration per epoch, epochs 19–20). The key contrast Cell 2→4 is +3.11 pts, which the paper itself treats as approximately two test samples and within noise. With three seeds and no formal power analysis, this cannot rule out a modest real benefit of the same size. The flat Phase 2 curves in Fig. 3 are equally consistent with an optimizer that was barely run. Please either run more hardware iterations with a proper uncertainty quantification, or reframe the conclusion as 'no detectable benefit within the tested budget' and temper the inference-only workflow recommendation accordingly.
[Table 4, §4.1] The paper's 'within sampling noise' criterion is based on the 75-sample test-set granularity (~1.33% per sample), but the contrasts in Table 4 are differences of three-seed means. The standard error of a three-seed mean difference is typically about 1–2 pts for these cells; for Cell 2→4, the difference of 3.11 pts is roughly 3 standard errors of the difference if the reported cross-seed standard deviations are used. Calling this 'within noise' conflates per-sample test-set resolution with seed-to-seed variability. A formal paired or unpaired test, or a bootstrap over seeds, should be reported before concluding that the hardware-training effect is zero.

minor comments (4)

[Table 1 caption] The caption contains a duplicated sentence about post-transpilation metrics on the IBM basis; please remove the repetition.
[Fig. 3] The text states that COBYLA 'moves the loss without changing a single classification decision,' but Fig. 3 shows validation accuracy, not loss. Please clarify whether the loss curves are shown or state that the claim is inferred from accuracy trajectories.
[§2.4.1] The noiseless QMP verification is reported for K=1 and K=2 only. The factorization argument in Eq. (3) is general, but stating why K=4 was not simulated (statevector size) would help avoid the impression that the verification is incomplete.
[§3.2, Table 1] The pilot reports VQC ZigZag test accuracy as 78.7±0.0% across three seeds. Perfect zero spread is surprising given that seeds change the data subset and optimizer initialization; please report the individual seed values or explain the source of determinism.

Circularity Check

0 steps flagged · score 2.0 of 10

No circular derivation: central claims rest on a tensor-factorization proof and controlled comparisons, not on fitted inputs or self-citation chains.

full rationale

The derivation chain is self-contained at every load-bearing point. The QMP equivalence is not assumed: Sec. 2.4.1 states 'Because no inter-circuit gate is ever applied, the joint state immediately before measurement factorizes' and gives Eq. (3); the noiseless equivalence follows from that factorization, not from any fitted parameter or cited theorem. The main empirical claims are controlled comparisons with shared checkpoints (Cells 1-3 share one simulator-trained checkpoint, Cells 4-5 one hybrid checkpoint), so contrasts isolate single variables; no parameter is fitted to the test set and then relabeled a prediction. The inference-only workflow does rest on the null result that two COBYLA hardware epochs do not improve accuracy, and this is a weak test by the paper's own scale: Sec. 2.3.2 allows 'B = 20 (one COBYLA iteration per epoch)', while Sec. 4.1 treats differences below '≈2.7 percentage points' as noise, making the +3.11 pt Cell 2→4 contrast indistinguishable from a modest real benefit. That is an underpowered empirical conclusion, not a circular one; the paper itself acknowledges its scale limits in the Conclusion. The QMP references ([20,27-30]) include author K. Yu, but the load-bearing 'QMP is inert' claim is proven and simulator-verified, not imported from those citations, so the self-citation is not load-bearing. No step reduces to its own inputs.

Assumptions & free parameters 5 free parameters · 5 assumptions · 0 invented entities

The central claims rest on standard quantum mechanics (factorization), on the assumption that the pinned heavy-hex layout prevents inter-circuit coupling, and on the assumed dominance of per-job overhead. The trained weights and hyperparameters are fitted or chosen by hand, but they are standard model parameters rather than hidden knobs introduced ad hoc; the key data-dependent choices are the data split/seeds, the COBYLA budgets, and the ansatz selection, which used the test set.

free parameters (5)

Classical encoder/readout weights phi (9,550 parameters) = trained via Adam, values not listed
Fit to the 350-sample MNIST subset in Phase 1; the accuracy numbers depend on these trained weights, which are standard model parameters rather than hidden knobs.
Quantum circuit angles theta (15 parameters) = COBYLA-optimized or frozen at 0.1*N(0,1) init
Phase 2 optimizes these; the no-fine-tuning comparison is over theta.
Data split and seeds = 350 train / 75 val / 75 test, seeds 2024, 2025, 2026
The 75-sample test set gives 1.33% resolution; all headline numbers are tied to this hand-chosen split.
COBYLA budget and shot count = B=500 (Aer) / B=20 (hybrid), 256 shots
Hand-chosen; the hybrid budget of one iteration per hardware epoch directly limits the power of the fine-tuning null result.
Architecture hyperparameters = nq=12, L=3, K=4
Chosen via a five-ansatz pilot; the ansatz selection used the test set (Sec. 3.2), adding a data-dependent choice to the headline numbers.

assumptions (5)

standard math Tensor-product factorization: with no inter-circuit gates, the joint state factorizes as |Psi> = |psi_1> (x) ... (x) |psi_K> (Eq. 3).
Standard quantum mechanics; the QMP equivalence result follows directly from this.
domain assumption The transpiler introduces no inter-circuit SWAPs because the four 12-qubit circuits are routing-disconnected on the pinned heavy-hex layout (Sec. 2.4, 3.4.1).
If violated, per-circuit predictions are no longer independent on hardware and the no-mean-cost QMP claim could fail.
domain assumption Device calibration thresholds (readout and ECR errors below stated bounds) keep the four circuits' noise profiles comparable (Sec. 3.4.1).
Supports the interpretation that K=4 variance amplification is not due to an outlier-noisy circuit.
domain assumption 256 shots per circuit suffice to approximate the analytic decision boundary (verified 79.11 vs 78.7, Sec. 3.2).
Underpins all sampled measurements in the five-cell framework.
domain assumption Per-job queue overhead dominates per-sample wall time on the cloud backend (Sec. 4.3).
The throughput-advantage conclusion of QMP depends on this; the observed ~3.76-3.96x speedup is consistent with it.

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Cite this review

Pith. "Pith review of Image Classification on IBM Quantum Computers." pith.science (2026). https://pith.science/paper/JKEAA3QV

@misc{pith2026260717705,
  author       = {Pith},
  title        = {Pith review of: Image Classification on IBM Quantum Computers},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/JKEAA3QV}},
  note         = {Machine review of arXiv:2607.17705}
}

abstract

Quantum machine learning on real noisy intermediate-scale quantum (NISQ) hardware has remained largely confined to binary or few-class tasks, limited by the cost of on-hardware training and the underuse of large devices at inference. We present a unified framework that classifies ten-class MNIST end-to-end on a $127$-qubit IBM Eagle processor, with three central contributions. First, a two-phase protocol decouples a gradient-based classical optimization of the encoder and readout from a gradient-free optimization of the quantum parameters, removing the parameter-shift gradient cost that makes on-hardware training impractical. Second, we introduce Quantum Multi-Programming to a trained quantum classifier for the first time, packing multiple circuit copies onto one device to deliver parallel inference at no mean-accuracy cost while cutting quantum-processor job submissions proportionally. Third, a controlled comparison shows that on-hardware fine-tuning yields no measurable accuracy gain, motivating a practical NISQ workflow: train on a classical simulator and reserve the hardware for inference only. Benchmarked against a matched-capacity classical network, the quantum module shows no per-parameter accuracy advantage at this scale; we therefore frame the work as a feasibility-and-workflow demonstration for multi-class quantum image classification on current hardware.

Discussion (0). Continue with ORCID to comment.

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Pith tools

Reviewed August 1, 2026 · model on record in the stance chip above.

[1] [1]

A., Korepin, V., Pascuzzi, V

Chowdhury, T. A., Korepin, V., Pascuzzi, V. R. & Yu, K. Quantum utility in simulating the real-time dynamics of the Fermi-Hubbard model using supercon- ducting quantum computers.Applied Physics Reviews13, 011434 (2026). URL https://doi.org/10.1063/5.0306069

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