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REVIEW 3 major objections 5 minor 16 references

Comparing ternary and binary adders and multipliers

T0 review · 3 major / 5 minor · reviewed 2026-08-14 · deepseek-v4-flash

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Pith's one-line read Ternary arithmetic loses to binary when basic cells are counted

desk verdict Useful negative result for ternary arithmetic, but the multiplier conclusion rests on a single transistor count and the 'cannot compete' claim overshoots the evidence. read the letter →

arxiv 1908.07299 v1 pith:JPNFV72Q submitted 2019-08-20 cs.AR

Daniel Etiemble This is my paper · ORCID
classification cs.AR
keywords ternaryaddersmultipliersbinaryCNTFETtransistorcountinformationratiomultivaluedlogic
verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

Ternary (three-valued) logic promises fewer wires and fewer arithmetic cells than binary, since one trit carries $\log_2(3)\approx 1.585$ bits. This paper tests that promise by comparing adders and multipliers of equal information capacity, implemented in the same carbon-nanotube field-effect transistor (CNTFET) technology and measured by transistor count. The author's central claim is that ternary loses: a 1-trit adder needs 4.4 to 15.5 times as many transistors as a 1-bit adder, while the break-even ratio is only $IR = \log(3)/\log(2)\approx 1.585$, and a 1-trit multiplier is about 6.3 times heavier than a 1-bit multiplier against a break-even of $IR^2\approx 2.51$. Because the count of basic cells is only slightly smaller in ternary (e.g., five 1-trit adders versus eight 1-bit adders), the inflated cell complexity dominates and the ternary operators cannot compete on area, interconnect, power, or delay. The paper matters because it provides a quantitative, technology-matched baseline for a literature full of isolated ternary circuit proposals.

What carries the argument

The load-bearing identity is the information ratio $IR = \log(3)/\log(2)\approx 1.585$, which converts equal computing power between binary and ternary: $N$ bits correspond to $M = N/IR$ trits. This ratio turns the comparison into a single cost threshold: a ternary cell can win only if its transistor count is below $IR$ times the binary cell for adders, and below $IR^2$ for the elementary multiplier, because a ternary multiplier cell emits both a product and a carry and thereby doubles the number of partial-product rows. The paper applies the threshold to transistor counts of CNTFET cells — a 1-trit full adder at 124 transistors and a 1-trit multiplier at 38, against binary cells at 8–28 and 6 respectively — and to carry-lookahead and carry-skip overheads, showing the ternary cell costs exceed the thresholds.

What would settle it

Build or simulate a 5-trit and an 8-bit adder in the same CNTFET technology with equal supply voltage and design rules, and measure delay, power, and area; if the 5-trit adder wins on a combined metric, the claim fails. More directly, any design of a 1-trit full adder with 13 or fewer transistors for an 8-transistor binary full adder, or a 1-trit multiplier at 15 or fewer transistors against a 6-transistor binary gate, would cross the paper's own break-even thresholds and overturn the conclusion.

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Extended reading notes

Core claim

The central discovery is a pair of break-even thresholds, derived from the information ratio $IR = \log(3)/\log(2)\approx 1.585$, that decide the contest before any layout is drawn. An $M$-trit adder needs only $M\approx N/IR$ full-adder cells to do the work of an $N$-bit adder, so ternary is competitive only if one 1-trit full adder costs no more than $IR\approx 1.585$ times one 1-bit full adder. Surveying CNTFET designs, the paper finds the 1-trit full adder at 124 transistors versus 8 to 28 for binary full adders, ratios of 4.4 to 15.5, so the threshold is missed by a wide margin. For multipliers, the 1-trit multiplier must stay below $IR^2\approx 2.51$ times the 1-bit multiplier, but the counted 38-transistor 1-trit cell is 6.3 times a 6-transistor and gate, and the ternary reduction tree also spends more on full adders. The author concludes that despite fewer external wires and fewer elementary blocks, ternary adders and multipliers cannot compete with binary ones in the same technology.

Load-bearing premise

The whole comparison rests on the assumption that transistor count is a sufficient proxy for overall hardware cost — that more transistors always mean more area, power, delay, and interconnect, so the ternary circuits' larger counts decide the contest.

Editorial extensions

If this is right

  • For carry-propagate, carry-lookahead, and carry-skip adders alike, the verdict is the same: any 1-trit full adder costing more than $1.585$ times the 1-bit full adder makes the $M$-trit adder lose to the $N$-bit adder.
  • Ternary multipliers face a double penalty: the 1-trit multiplier must stay under $2.51$ times the 1-bit multiplier, and the 1-trit full adders used in the reduction tree must also stay near the adder threshold; the counted cells fail both.
  • The outward advantage of ternary — fewer input/output wires and fewer elementary blocks — is real but is outweighed by internal interconnect, area, power, and delay, all of which scale with transistor count.
  • The comparison method carries over to other multivalued radices: replace $IR$ by $\log(r)/\log(2)$ and test the same cell-count thresholds.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

  • The break-even ratios double as design targets: a ternary circuit with a 1-trit full adder at or below $1.585$ times a matched 1-bit full adder would reverse the adder conclusion, so the paper implicitly sets a falsifiable engineering goal (roughly 13 transistors if the binary cell is 8).
  • If a metric other than transistor count dominates — for example, off-chip pin count in interconnect-bound systems — the paper's negative conclusion does not automatically transfer, and ternary could still win in that narrower regime.
  • The same threshold logic suggests a scaling test for radix 4 or radix 5: as the radix grows, cell complexity typically rises quickly while $IR$ grows slowly, so the break-even condition becomes harder to satisfy, not easier.
  • A direct experimental check would be to fabricate an 8-bit binary and a 5-trit ternary adder in the same CNTFET process and compare measured delay-power-area products; the paper's transistor-count prediction implies ternary should be worse on all three.
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Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Referee Report

3 major / 5 minor

Summary. This manuscript compares binary and ternary adders and multipliers at equal information throughput, using M = N/IR with IR = log(3)/log(2) ≈ 1.585. It first derives cell-count comparisons: a ternary ripple-carry, carry-lookahead, or carry-skip adder uses fewer 1-trit full adders than a binary adder uses 1-bit full adders, but the 1-trit adder must cost less than IR times the 1-bit adder to break even; for multipliers, the 1-trit multiplier must cost less than IR² times the 1-bit AND, and the carry generated by each 1-trit multiplier doubles the number of partial-product lines. The paper then uses published CNTFET designs to count transistors: a 124T ternary full adder versus 8–28T binary full adders, a 27T threshold-logic ternary FA versus an 11T binary FA, and a 38T 1-trit multiplier versus a 6T AND. From these counts it concludes that ternary adders and multipliers cannot compete with binary ones, since observed ratios are 4.4–15.5 for adders and about 6.3 for the multiplier cell, and the CLA and carry-skip carry circuitry is also more costly for ternary.

Significance. The paper provides a clean and useful quantitative framework: the breakeven ratios IR and IR² are correctly derived from the information ratio, and the adder comparison is robust because even the best cited ternary FA is more than IR times the best cited binary FA. If transistor count is accepted as a proxy for hardware complexity, the negative result for ternary adders is convincing. The multiplier comparison identifies the right structural issue (carry generation doubling the number of partial-product lines), and the overall conclusion is plausible, but it is less robust than the adder conclusion because it depends on a single 1-trit multiplier cell and because the full multiplier totals are never tabulated in transistor counts. The paper is useful as a reference-point comparison for the MVL/ternary logic community, provided the missing sensitivity analysis is supplied.

major comments (3)
  1. [VI.A] The 1-trit multiplier is represented by a single 38T design (Equations 1–3), and no evidence is given that this count is close to minimal. The breakeven value against a 6T binary AND is IR² × 6 ≈ 15T, so the 38T cell supports the qualitative conclusion, but the margin is not overwhelming; the adder section itself shows that a different design style (threshold logic, Section V.A) reduces a 124T ternary FA to 27T. A threshold-logic or otherwise optimized 1-trit multiplier in the 20–30T range would shrink the overall multiplier margin substantially. Please add a survey of existing 1-trit multiplier designs, a lower-bound argument, or a sensitivity analysis of the full multiplier ratio as a function of this cell count. Without this, the strong claim that ternary multipliers 'cannot compete' is not fully established.
  2. [VI.B / Table III] The paper never provides a complete transistor-count table for whole multipliers analogous to Table VI for adders. Section VI.B compares only the reduction trees in equivalent-FA terms and states that the difference 'is not able to compensate' the FA advantage, but it does not add the partial-product generator counts to the comparison. In addition, Table III gives 12 ternary HAs for the 5×5 case while Section VI.B says 14. Please give explicit total transistor counts for the N = 8, 12, and 16 comparisons, using consistent cell counts, and do so for both cited ternary FA designs (124T and 27T) to show the range of the final ratio. This is necessary to support the multiplier conclusion quantitatively.
  3. [IV.B / VII] The abstract and Section VII make an unqualified claim that the ternary operators have more connections, more chip area, more propagation delays, and more power dissipation because they have more transistors. Section IV.B explicitly adopts transistor count as the only complexity criterion; the step from transistor count to delay and power is an assumption, not a demonstrated relation. For example, a logically shallower but transistor-heavier circuit can have a shorter critical path, and interconnect counts depend on cell placement and routing, not only on transistor count. Please either provide supporting data for the delay/power/area inference or restrict the conclusion to 'more transistors and, correspondingly, higher wiring and area under the same cell style.'
minor comments (5)
  1. [III.A.2] The text 'M = N/1.858' should read 'M = N/1.585'; the value 1.858 is inconsistent with the information ratio defined in the paper.
  2. [V.B.4] The sentence 'For CPAs, CSAs and CSAs, the M-trit adders cannot compete' contains a repeated 'CSAs'; it should read 'For CPAs, CLAs and CSAs'.
  3. [V.B.1] In the sentence 'a M-trit multiplier will be more efficient than a N-bit multiplier', the word 'multiplier' should be 'adder', since the section is about ripple-carry adders.
  4. [Table VIII] The entries in Table VIII sum to 320, not 310 as listed; the 5-trit CLA carry-count row should be recomputed.
  5. [VI.B] The number of ternary half adders in the reduction tree is given as 12 in Section III.A.2 and as 14 in Section VI.B; these counts should be reconciled.

Circularity Check

0 steps flagged · score 0.0 of 10

No significant circularity; the conclusions are computed from externally cited transistor counts and information-theoretic ratios.

full rationale

The paper's derivation is self-contained arithmetic over external data. It first computes breakeven cell-complexity ratios from cell counts: an 8-bit CPA uses eight 1-bit FAs versus five 1-trit FAs for a 5-trit adder, so ternary wins only if a 1-trit FA costs no more than 8/5 of a 1-bit FA; similarly, multipliers have N^2/M^2 ≈ IR^2 partial-product cells, giving the IR^2 multiplier breakeven. These thresholds are not assumed outcomes; they are derived from counting cells. The actual transistor counts (124T ternary FA versus 28T, 14-16T, and 8T binary FAs; 38T 1-trit multiplier versus 6T 1-bit multiplier; carry circuitry counts in Tables VII-IX) are taken from external CNTFET design papers [3]-[6], not generated by the present conclusion. The only self-citation, [1], is historical context ('Having presenting such a comparison in 1988 [1]') and carries none of the argument's weight. The paper's limitation that transistor count is a proxy for hardware competitiveness is an evidentiary assumption, not a circular one: the conclusion 'cannot compete' is broader than the proxy, but that is a robustness/correctness concern. No equation or table in the paper is defined in terms of the conclusion it supports, and no fitted parameter is later renamed as a prediction. The comparison therefore does not reduce to its inputs; a different external count could change the verdict, which is exactly what a non-circular empirical comparison does.

Assumptions & free parameters 0 free parameters · 5 assumptions · 0 invented entities

No free parameters are fitted to data; IR is a mathematical constant and all transistor counts are taken from cited circuit designs. The central claim rests mainly on domain assumptions about how to measure equal computing capability and hardware cost, listed above.

assumptions (5)
  • domain assumption Information equivalence M = N/IR with IR = log(3)/log(2) equates ternary and binary computing capability.
    Section I, Table I. Assumes each ternary digit is equivalent to 1.585 bits and that arithmetic capability scales with the number of information-carrying wires.
  • domain assumption Transistor count is a sufficient proxy for interconnects, chip area, power, and propagation delay.
    Section IV.B. The paper states transistor count is only an estimation but then uses it to conclude ternary 'cannot compete' on all these metrics.
  • domain assumption The reference ternary cells from [4], [5], [6] are representative of ternary CNTFET complexity.
    Section V.A. The 124-transistor ternary full adder is built from the 2017 half-adder; no exhaustive survey of ternary adder designs is given.
  • domain assumption A half adder has about half the transistor count of a full adder (1 HA = 0.5 FA).
    Section III.A.3. Used to compute equivalent full-adder counts for multiplier comparison tables.
  • domain assumption Ternary carry signals are binary and 1-trit multiplication produces a product trit plus a binary carry.
    Sections II and III. This design convention matches the cited ternary arithmetic literature and shapes the multiplier partial-product count.

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Cite this review

Pith. "Pith review of Comparing ternary and binary adders and multipliers." pith.science (2026). https://pith.science/paper/JPNFV72Q

@misc{pith2026190807299,
  author       = {Pith},
  title        = {Pith review of: Comparing ternary and binary adders and multipliers},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/JPNFV72Q}},
  note         = {Machine review of arXiv:1908.07299}
}
read the original abstract

While many papers have proposed implementations of ternary adders and ternary multipliers, no comparisons have generally been done with the corresponding binary ones. We compare the implementations of binary and ternary adders and multipliers with the same computing capability according to the basic blocks that are 1-bit and 1-trit adders and 1-bit and 1-trit multipliers. Then we compare the complexity of these basic blocks by using the same CNTFET technology to evaluate the overall complexity of N-bit adders and M-trit adders on one side, and NxN bit multipliers and MxM trits multipliers with M = N/IR (IR = log(3)/log(2) is the information ratio). While ternary adders and multipliers have less input and output connections and use less basic building blocks, the complexity of the ternary building blocks is too high and the ternary adders and multipliers cannot compete with the binary ones.

Figures

Figures reproduced from arXiv: 1908.07299 by the authors.

Figure 1
Figure 1. Carry Propagate Adder fast adders. Considering all the possible versions is out of the scope of this paper. We just consider two other schemes which purpose is to speed-up the carry propagation. B. Carry Look-ahead Adders (CLAs) [PITH_FULL_IMAGE:figures/full_fig_p002_1.png] view at source ↗
Figure 3
Figure 3. presents a 4-bit binary skip adder. As the CPA, it has four 1-bit full adders. The carry “skip" scheme uses the Pi propagate function of the CLA, a And gate to compute P0.P1.P2.P3 and a two-input multiplexer. For the “skip" part, the only difference between the binary and the ternary version is the computation of the propagate functions, which have been defined for the CLA [PITH_FULL_IMAGE:figures/full_fig_p002_3.png] view at source ↗
Figure 2
Figure 2. presents a 4-bit carry look-ahead adder. This adder has the same number of full adders than the CPA. The binary equations of the carry computation part are well-known: Gi = Ai.Bi P i = Ai xor Bi or P i = Ai + Bi C1 = G0 + P0.C0 C2 = G1 + G0.P1 + P0.P1.C0 C3 = G2 + G1.P2 + G0.P1.P2 + P0.P1.P2.C0 C4 = G3 + G2.P3 + G1.P2.P3 + G0.P1.P2.P3 + P0.P1.P2.P3.C0 [PITH_FULL_IMAGE:figures/full_fig_p002_2.png] view at source ↗
Figures from the paper (7 more)
Figure 5
Figure 5. Figure 5: 5*5 trit multiplication with a Wallace tree [PITH_FULL_IMAGE:figures/full_fig_p003_5.png]
Figure 4
Figure 4. Figure 4: 8*8 bit multiplication with a Wallace tree [PITH_FULL_IMAGE:figures/full_fig_p003_4.png]
Figure 7
Figure 7. Figure 7: Decoder and encoder circuits [4] [PITH_FULL_IMAGE:figures/full_fig_p005_7.png]
Figure 8
Figure 8. Figure 8: Sum binary parts. While the half adder compute Sum10, Sum20 and Cm0 with an implicit input carry equal to 0, similar circuitry can be used to compute Sum11, Sum21 and Cm1 when the input carry is 1. Two multiplexers controlled by the input carry are used to compute the …
Figure 6
Figure 6. Figure 6: General scheme of m-valued circuits [PITH_FULL_IMAGE:figures/full_fig_p005_6.png]
Figure 11
Figure 11. Figure 11: Ternary Full Adder with capacitive inputs [PITH_FULL_IMAGE:figures/full_fig_p006_11.png]
Figure 10
Figure 10. Figure 10: Binary Full Adder with capacitive inputs [PITH_FULL_IMAGE:figures/full_fig_p006_10.png]

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