REVIEW 15 cited by
The Championship Simulator: Architectural Simulation for Education and Competition
Not yet reviewed by Pith; the record is open.
This paper has not been read by Pith yet. Machine review is queued; the pith claim, tier, and objections will appear here once it completes.
SPECIMEN: schema-true, not a live event
T0 review · schema-true
One-sentence machine reading of the paper's core claim.
pith:XXXXXXXX · record.json · timestamp
Signed reviews
read the original abstract
Recent years have seen a dramatic increase in the microarchitectural complexity of processors. This increase in complexity presents a twofold challenge for the field of computer architecture. First, no individual architect can fully comprehend the complexity of the entire microarchitecture of the core. This leads to increasingly specialized architects, who treat parts of the core outside their particular expertise as black boxes. Second, with increasing complexity, the field becomes decreasingly accessible to new students of the field. When learning core microarchitecture, new students must first learn the big picture of how the system works in order to understand how the pieces all fit together. The tools used to study microarchitecture experience a similar struggle. As with the microarchitectures they simulate, an increase in complexity reduces accessibility to new users. In this work, we present ChampSim. ChampSim uses a modular design and configurable structure to achieve a low barrier to entry into the field of microarchitecural simulation. ChampSim has shown itself to be useful in multiple areas of research, competition, and education. In this way, we seek to promote access and inclusion despite the increasing complexity of the field of computer architecture.
Forward citations
Cited by 15 Pith papers
-
Why Do Prefetchers Fail? Let Agents Answer
An agent-driven loop that turns a prefetcher's residual misses into new sub-prefetchers yields a 17-engine design claimed to beat human designs on held-out workloads.
-
Beyond Static Policies: Dynamic Selection Among Modern Microarchitectural Policies
A binary runtime choice between two L1D prefetchers recovers most of the performance left by any fixed policy, with a small decision tree or bandit rule as the selector.
-
Themis: Software-Defined Hardware Prefetching
Page-granular, profile-computed prefetch-disable hints stored in page-table entries reduce useless hardware prefetches by ~40% and improve IPC by 0.2–13.8% across seven prefetchers on datacenter traces.
-
ArchEval: Measuring AI Agents as Computer Architects
LLM agents beat architecture baselines with full simulator harnesses, but only one configuration stays above baseline without feedback, and performance modeling remains weak.
-
CHIA: An open-source framework for principled, agentic AI-driven hardware/software co-design research
CHIA is an open-source framework for agentic AI-driven hardware/software co-design using CHIA loops as directed cyclic graphs, a tool library, and features for reliable experimentation, shown via five case studies.
-
When Mitigations Backfire: Timing Channel Attacks and Defense for PRAC-Based RowHammer Mitigations
PRAC's Alert Back-Off mitigation creates observable memory latency spikes that leak partial AES keys, and periodic activity-independent RFMs close the leak with 3.4 percent average overhead.
-
RogueRFM: Attacking Refresh Management for Covert-Channel and Denial-of-Service
An attacker can abuse DDR5 Refresh Management so one DRAM bank's activity stalls all other banks, creating a 31.3 KB/s covert channel and up to 67% slowdown of co-running workloads.
-
Dissecting Conditional Branch Predictors of Apple Firestorm and Qualcomm Oryon for Software Optimization and Architectural Analysis
First known recovery of Apple Firestorm and Qualcomm Oryon conditional branch predictor internals, with identification of two new misprediction-inducing effects and a software mitigation.
-
PIMID: A Full-System Simulator with Intricacy and Diversity for Processing-in-Memory
PIMID unifies dual-execution-model, multi-technology, multi-placement PIM simulation and finds technology, PE scaling, and message-passing collectives dominate end-to-end time and energy.
-
ArchAgent v2: A Case Study with the Data Prefetching Championship
An LLM-based evolutionary framework automatically discovered a multi-level prefetcher that beats the prior hand-designed DPC4 champion on held-out traces.
-
Aneto: Predicting System Performance by Exploiting Cross-Workload Regularity
Aneto predicts a workload's CPI under a new memory system from a single run's CPI, LLC miss rate, and miss penalty, via a cross-workload regression of the blocking factor.
-
On the Limits of Machine-Learned Ranking for Modern Microarchitectural Policies
ML predictors rank processor configurations well in aggregate but fall below chance on counter-intuitive reversals and barely beat a no-feature baseline for closely matched policies.
-
Microflow: Microarchitectural Causal Observability for Deep Cross-Layer Analysis and Optimization
Microflow builds a typed causal graph from simulator traces so that stalls can be traced across software, pipeline, and resource layers, exposing root causes such as a RAS corruption cascade in leela and cross-loop co...
-
Vulcan: Instance-specialized, Verifiable Systems Heuristics Through LLM-driven Search
Vulcan finds instance-specific cache and memory-tiering heuristics via LLM-driven evolutionary search, but its evaluation overlaps training traces with test traces and the abstract overstates the body's results.
-
Random Adaptive Cache Placement Policy
A random eviction plus V-Way hybrid cache reports hit rates on four traces without any baseline comparison.
Discussion (0). Continue with ORCID to comment.