Paper Citation Record · LEDGER

ProtocolLLM: RTL Benchmark for SystemVerilog Generation of Communication Protocols

As of 8 August 2026, this Paper Citation Record lists 39 of 39 outbound references and 1 inbound Pith citation observation for arXiv:2506.07945.

A citation records a reference. It does not transfer a finding from one paper to another.

pith.paper-citation-record.v1
2506.07945 v2

Coverage vector

measured 39 of 39 reference resolution

Typed states for the displayed outbound observations.

Source: paper_references, paper_reference_links, observed 2026-08-07T05:27:36.184407Z

measured 40 of 40 standing notices

One-hop event checks from named stored sources.

Source: scholarly_work_events, retraction_status_cache, observed 2026-08-07T06:34:17.273281+00:00

measured 1 of 1 inbound itemization

Pith citing papers itemized under the disclosed page cap.

Source: paper_references, paper_reference_links, observed 2026-08-04T10:19:31.688560Z

measured 0 of 1 external citation measurements

A source-named dated measurement, never combined with another source.

Source: cited_works

Reference resolution

39 of 39 outbound references displayed

verified exact2
verified fuzzy15
unresolved21
parse uncertain1
malformed identifier0
metadata mismatch0

External citation measurements

No source-named external measurement is stored.

Outbound references

Observation 7e4aca70-e1da-4573-b35a-4c31622712d1 · outbound

This paper cites Claude opus.

ProtocolLLM: RTL Benchmark for SystemVerilog Generation of Communication Protocols Claude opus

Reference 1

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T05:27:37.029310Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.

Observation 4bee1b3a-5dce-4ffd-ae65-163d76dac0a4 · outbound

This paper cites Claude sonnet.

ProtocolLLM: RTL Benchmark for SystemVerilog Generation of Communication Protocols Claude sonnet

Reference 2

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T05:27:37.014043Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.

Observation 5f542a62-f6d1-43b7-81f7-30077eebce20 · outbound

This paper cites an unresolved cited work.

ProtocolLLM: RTL Benchmark for SystemVerilog Generation of Communication Protocols Unresolved cited work

Reference 3

Resolution: unresolved; raw_fallback, observed 2026-08-07T05:27:36.998236Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.

Observation bb815a44-a833-4675-96c0-887dcbc83e43 · outbound

This paper cites Pyhdl- eval: An llm evaluation framework for hardware design using python- embedded dsls,.

ProtocolLLM: RTL Benchmark for SystemVerilog Generation of Communication Protocols Pyhdl- eval: An llm evaluation framework for hardware design using python- embedded dsls,

Reference 4

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T05:27:36.982900Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.

Observation 1611d0de-f386-44e7-bd0d-06d3e76cd285 · outbound

This paper cites Smart communication in a wired sensor- and actuator-network of a modular robot actuator system using a hop- protocol with delta-routing,.

ProtocolLLM: RTL Benchmark for SystemVerilog Generation of Communication Protocols Smart communication in a wired sensor- and actuator-network of a modular robot actuator system using a hop- protocol with delta-routing,

Reference 5

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T05:27:36.965830Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.

Observation f5b14f88-5514-41d2-a174-7af720141848 · outbound

This paper cites Chipgpt: How far are we from natural language hardware design,.

ProtocolLLM: RTL Benchmark for SystemVerilog Generation of Communication Protocols Chipgpt: How far are we from natural language hardware design,

Reference 6

Resolution: unresolved; no resolver link, observed 2026-08-07T05:27:36.015930Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation a13aab40-fade-4027-ac33-0a1050142589 · outbound

This paper cites Gemini 2.5: Pushing the Frontier with Advanced Reasoning, Multimodality, Long Context, and Next Generation Agentic Capabilities.

ProtocolLLM: RTL Benchmark for SystemVerilog Generation of Communication Protocols Gemini 2.5: Pushing the Frontier with Advanced Reasoning, Multimodality, Long Context, and Next Generation Agentic Capabilities

Reference 7

Resolution: unresolved; no resolver link, observed 2026-08-07T05:27:36.020854Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 81d4d43d-c720-47ba-882f-61fbd6922e57 · outbound

This paper cites Exploring and characterizing large language models for embedded system development and debugging,.

ProtocolLLM: RTL Benchmark for SystemVerilog Generation of Communication Protocols Exploring and characterizing large language models for embedded system development and debugging,

Reference 8

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T05:27:36.949302Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.

Observation f0dc5c48-bec0-4f9a-a2cc-4da267792734 · outbound

This paper cites Assertllm: Generating and evaluating hardware verification assertions from design specifications via multi-llms,.

ProtocolLLM: RTL Benchmark for SystemVerilog Generation of Communication Protocols Assertllm: Generating and evaluating hardware verification assertions from design specifications via multi-llms,

Reference 9

Resolution: unresolved; no resolver link, observed 2026-08-07T05:27:36.036648Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 82e2afc0-e2b0-4986-a30e-1e2f9011d4e1 · outbound

This paper cites All Artificial, Less Intelligence: GenAI through the Lens of Formal Verification.

ProtocolLLM: RTL Benchmark for SystemVerilog Generation of Communication Protocols All Artificial, Less Intelligence: GenAI through the Lens of Formal Verification

Reference 10

Resolution: verified exact; local_arxiv, observed 2026-08-07T05:27:36.537268Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.

Observation b9940c38-714a-4236-8195-7e29b7fbb732 · outbound

This paper cites TuRTLe: A Unified Evaluation of LLMs for RTL Generation.

ProtocolLLM: RTL Benchmark for SystemVerilog Generation of Communication Protocols TuRTLe: A Unified Evaluation of LLMs for RTL Generation

Reference 11

Resolution: verified exact; local_arxiv, observed 2026-08-07T05:27:36.510441Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.

Observation 480b4146-1067-4756-8dac-0222d286ce71 · outbound

This paper cites Towards LLM-Powered Verilog RTL Assistant: Self-Verification and Self-Correction.

ProtocolLLM: RTL Benchmark for SystemVerilog Generation of Communication Protocols Towards LLM-Powered Verilog RTL Assistant: Self-Verification and Self-Correction

Reference 12

Resolution: unresolved; no resolver link, observed 2026-08-07T05:27:36.054040Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation cdce50b4-bde1-4bc4-a851-b49ac8bc7e76 · outbound

This paper cites OpenCoder: The Open Cookbook for Top-Tier Code Large Language Models.

ProtocolLLM: RTL Benchmark for SystemVerilog Generation of Communication Protocols OpenCoder: The Open Cookbook for Top-Tier Code Large Language Models

Reference 13

Resolution: unresolved; no resolver link, observed 2026-08-07T05:27:36.059269Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 6a8e573e-2b64-4a4c-8232-9f0412a38426 · outbound

This paper cites Qwen2.5-Coder Technical Report.

ProtocolLLM: RTL Benchmark for SystemVerilog Generation of Communication Protocols Qwen2.5-Coder Technical Report

Reference 14

Resolution: unresolved; no resolver link, observed 2026-08-07T05:27:36.064345Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 99dff6dc-cb93-4a92-a504-cc7da5f9e6ee · outbound

This paper cites Automated synthesis of hardware designs using symbolic feedback and grammar-constrained decoding in large language models,.

ProtocolLLM: RTL Benchmark for SystemVerilog Generation of Communication Protocols Automated synthesis of hardware designs using symbolic feedback and grammar-constrained decoding in large language models,

Reference 15

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T05:27:36.932675Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.

Observation a13f2fad-4efe-404f-a1bd-d2098181a5f6 · outbound

This paper cites A Survey on Large Language Models for Code Generation.

ProtocolLLM: RTL Benchmark for SystemVerilog Generation of Communication Protocols A Survey on Large Language Models for Code Generation

Reference 16

Resolution: unresolved; no resolver link, observed 2026-08-07T05:27:36.074233Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 0abd343c-98e5-489f-8f15-9ec8e49526ad · outbound

This paper cites Swe-bench: Can language models resolve real-world github issues?.

ProtocolLLM: RTL Benchmark for SystemVerilog Generation of Communication Protocols Swe-bench: Can language models resolve real-world github issues?

Reference 17

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T05:27:36.914156Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.

Observation efc90441-1487-4947-834d-f48e5be24243 · outbound

This paper cites Hdleval benchmarking llms for multiple hdls,.

ProtocolLLM: RTL Benchmark for SystemVerilog Generation of Communication Protocols Hdleval benchmarking llms for multiple hdls,

Reference 18

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T05:27:36.897910Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.

Observation 727aff90-8517-4575-9cd1-500477bfec37 · outbound

This paper cites Uart communication protocol and how it works,.

ProtocolLLM: RTL Benchmark for SystemVerilog Generation of Communication Protocols Uart communication protocol and how it works,

Reference 19

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T05:27:36.881511Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.

Observation e6661c43-60c1-4878-9e4c-8e08e5462dbb · outbound

This paper cites Interfacing of mems motion sensor with fpga using i2c protocol,.

ProtocolLLM: RTL Benchmark for SystemVerilog Generation of Communication Protocols Interfacing of mems motion sensor with fpga using i2c protocol,

Reference 20

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T05:27:36.865817Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.

Observation c78d5a6f-3809-4a0b-9678-d3c6db89e1bb · outbound

This paper cites Autosilicon: Scaling up rtl design generation capability of large language models,.

ProtocolLLM: RTL Benchmark for SystemVerilog Generation of Communication Protocols Autosilicon: Scaling up rtl design generation capability of large language models,

Reference 21

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T05:27:36.850067Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.

Observation ba35aa8f-fdf2-426a-b9d7-5bc7501dfe49 · outbound

This paper cites StarCoder: may the source be with you!.

ProtocolLLM: RTL Benchmark for SystemVerilog Generation of Communication Protocols StarCoder: may the source be with you!

Reference 22

Resolution: unresolved; no resolver link, observed 2026-08-07T05:27:36.101730Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation a246702b-d547-46a2-92a2-6b623bb95b4c · outbound

This paper cites Verilogeval: Evaluating large language models for verilog code generation,.

ProtocolLLM: RTL Benchmark for SystemVerilog Generation of Communication Protocols Verilogeval: Evaluating large language models for verilog code generation,

Reference 23

Resolution: unresolved; no resolver link, observed 2026-08-07T05:27:36.106823Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 92fa7bc8-35c0-406d-92b9-1d11ad3eed08 · outbound

This paper cites StarCoder 2 and The Stack v2: The Next Generation.

ProtocolLLM: RTL Benchmark for SystemVerilog Generation of Communication Protocols StarCoder 2 and The Stack v2: The Next Generation

Reference 24

Resolution: unresolved; no resolver link, observed 2026-08-07T05:27:36.111466Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation e00af0db-2ebd-456b-967f-954bb8a5dc2b · outbound

This paper cites RTLLM: An Open-Source Benchmark for Design RTL Generation with Large Language Model.

ProtocolLLM: RTL Benchmark for SystemVerilog Generation of Communication Protocols RTLLM: An Open-Source Benchmark for Design RTL Generation with Large Language Model

Reference 25

Resolution: unresolved; no resolver link, observed 2026-08-07T05:27:36.116201Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 938291ee-6b64-4992-ace6-d302e6a2d94d · outbound

This paper cites Rtllm: An open-source benchmark for design rtl generation with large language model,.

ProtocolLLM: RTL Benchmark for SystemVerilog Generation of Communication Protocols Rtllm: An open-source benchmark for design rtl generation with large language model,

Reference 26

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T05:27:36.822971Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.

Observation 15d63152-2ca2-49fc-8014-55e5ec79bebd · outbound

This paper cites Serial peripheral interface (spi),.

ProtocolLLM: RTL Benchmark for SystemVerilog Generation of Communication Protocols Serial peripheral interface (spi),

Reference 27

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T05:27:36.806684Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.

Observation 5f92df7d-5544-4b77-ac76-9a1af6ebe627 · outbound

This paper cites Gpt-4.1,.

ProtocolLLM: RTL Benchmark for SystemVerilog Generation of Communication Protocols Gpt-4.1,

Reference 28

Resolution: parse uncertain; no resolver link, observed 2026-08-07T05:27:36.130808Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 4b80fe08-1b9b-4033-bd8a-07b0e93d445c · outbound

This paper cites GPT-4 Technical Report.

ProtocolLLM: RTL Benchmark for SystemVerilog Generation of Communication Protocols GPT-4 Technical Report

Reference 29

Resolution: unresolved; no resolver link, observed 2026-08-07T05:27:36.135599Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 4414c998-2e4e-4c46-9e2b-2bd766721ff5 · outbound

This paper cites A survey of research in large language models for electronic design automation,.

ProtocolLLM: RTL Benchmark for SystemVerilog Generation of Communication Protocols A survey of research in large language models for electronic design automation,

Reference 30

Resolution: unresolved; no resolver link, observed 2026-08-07T05:27:36.140642Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 2d967e3a-bbce-4a8a-ac51-069d61d88105 · outbound

This paper cites Usart, spi, i2c, and communication protocols,.

ProtocolLLM: RTL Benchmark for SystemVerilog Generation of Communication Protocols Usart, spi, i2c, and communication protocols,

Reference 31

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T05:27:36.767363Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.

Observation 04278365-2610-4d17-b8bd-c3e561e715ff · outbound

This paper cites Evaluating Large Language Models for Automatic Register Transfer Logic Generation via High-Level Synthesis.

ProtocolLLM: RTL Benchmark for SystemVerilog Generation of Communication Protocols Evaluating Large Language Models for Automatic Register Transfer Logic Generation via High-Level Synthesis

Reference 32

Resolution: unresolved; no resolver link, observed 2026-08-07T05:27:36.151403Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 143cba06-df52-46a9-98c9-e22a1442607f · outbound

This paper cites Benchmarking large language models for auto- mated verilog rtl code generation,.

ProtocolLLM: RTL Benchmark for SystemVerilog Generation of Communication Protocols Benchmarking large language models for auto- mated verilog rtl code generation,

Reference 33

Resolution: unresolved; no resolver link, observed 2026-08-07T05:27:36.156625Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 1b5f1a72-d916-46ae-889a-c82741b68563 · outbound

This paper cites Verigen: A large language model for verilog code generation,.

ProtocolLLM: RTL Benchmark for SystemVerilog Generation of Communication Protocols Verigen: A large language model for verilog code generation,

Reference 34

Resolution: unresolved; no resolver link, observed 2026-08-07T05:27:36.162177Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation b3f22a93-62c7-4fd8-a916-62af175fc489 · outbound

This paper cites VHDL-Eval: A Framework for Evaluating Large Language Models in VHDL Code Generation.

ProtocolLLM: RTL Benchmark for SystemVerilog Generation of Communication Protocols VHDL-Eval: A Framework for Evaluating Large Language Models in VHDL Code Generation

Reference 35

Resolution: unresolved; no resolver link, observed 2026-08-07T05:27:36.167362Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 083f52ca-2d37-470b-9301-ad9c16a37aed · outbound

This paper cites Understanding the i2c bus: A beginner’s guide to simplifying communication,.

ProtocolLLM: RTL Benchmark for SystemVerilog Generation of Communication Protocols Understanding the i2c bus: A beginner’s guide to simplifying communication,

Reference 36

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T05:27:36.727498Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.

Observation a062c18c-e004-42bb-849d-172756067885 · outbound

This paper cites VFlow: Discovering Optimal Agentic Workflows for Verilog Generation.

ProtocolLLM: RTL Benchmark for SystemVerilog Generation of Communication Protocols VFlow: Discovering Optimal Agentic Workflows for Verilog Generation

Reference 37

Resolution: unresolved; no resolver link, observed 2026-08-07T05:27:36.178869Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation ea8c9136-d970-41f8-99eb-74bb7764cec1 · outbound

This paper cites Verithoughts: Enabling automated verilog code generation us- ing reasoning and formal verification,.

ProtocolLLM: RTL Benchmark for SystemVerilog Generation of Communication Protocols Verithoughts: Enabling automated verilog code generation us- ing reasoning and formal verification,

Reference 38

Resolution: unresolved; no resolver link, observed 2026-08-07T05:27:36.184407Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 006295bd-5943-4edf-964a-f56f2a0a00bd · outbound

This paper cites Exploring and Characterizing Large Language Models For Embedded System Development and Debugging.

ProtocolLLM: RTL Benchmark for SystemVerilog Generation of Communication Protocols Exploring and Characterizing Large Language Models For Embedded System Development and Debugging

Reference 2023

Resolution: unresolved; no resolver link, observed 2026-08-07T05:27:36.031238Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Pith citing papers

Observation 1c7d73f9-2bc9-4f73-8e73-1350c7470e07 · inbound

LLM-Empowered Agentic MAC Protocols: A Dynamic Stackelberg Game Approach cites this paper.

LLM-Empowered Agentic MAC Protocols: A Dynamic Stackelberg Game Approach ProtocolLLM: RTL Benchmark for SystemVerilog Generation of Communication Protocols

Reference 18

Resolution: unresolved; no resolver link, observed 2026-08-04T10:19:31.688560Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.