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arxiv: 2606.21454 · v1 · pith:KA4HFW7Unew · submitted 2026-06-19 · 💻 cs.AR

COMPOSE: Static Timing-driven Composable Reconfigurable Architecture for Accelerating Recurrence-Bound Loops

Rohan Juneja , Vishruti Ranjan , Rakshith Harish , Li-Shiuan Peh This is my paper

Pith reviewed 2026-06-26 12:47 UTC · model grok-4.3

classification 💻 cs.AR
keywords CGRAcomposable architecturerecurrence-bound loopsstatic timingprocessing element formationperformance improvementenergy efficiency
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The pith

COMPOSE forms processing elements dynamically in CGRAs using static timing to fuse operations across loop iterations and cut inter-iteration serialization.

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The paper presents COMPOSE as a composable CGRA that uses compile-time static timing data to form processing elements on the fly rather than fixing them to single operations. This spatial fusion across iterations, combined with selective slack use, breaks the serialization that recurrence dependencies impose in traditional CGRAs. Deferring registration of locally consumable values further trims register-file and memory traffic. A reader would care because recurrence-bound loops appear in many compute-heavy workloads yet resist standard parallelization; the approach claims to raise throughput and cut energy without added hardware cost. If the method holds, it demonstrates that timing-guided composition at compile time can safely increase utilization where rigid schedules fall short.

Core claim

COMPOSE enables dynamic formation of PEs at compile time guided by static timing information. By spatially fusing operations across loop iterations and selectively utilizing slack, COMPOSE resolves inter-iteration dependencies that limit throughput and enables low latency execution by reducing slack wastage. Additionally, the architecture reduces register file pressure by deferring output registration when intermediate values remain locally consumable, which significantly lowers redundant memory traffic.

What carries the argument

The composable CGRA that performs compile-time, static-timing-guided dynamic formation of processing elements to fuse operations across iterations.

If this is right

  • Recurrence-bound loops achieve higher throughput because inter-iteration dependencies are resolved by spatial fusion rather than serialized scheduling.
  • Energy-delay product drops on average by 2.9x because slack is consumed and register-file traffic is reduced.
  • Area and power overheads remain minimal while delivering the gains over fixed-PE baselines.
  • Workloads with abundant but recurrence-limited parallelism become better candidates for CGRA acceleration.

Where Pith is reading between the lines

These are editorial extensions of the paper, not claims the author makes directly.

  • The same timing-guided composition idea might apply to other spatial architectures if their place-and-route tools can export equivalent slack data.
  • Compiler passes that currently target only operation scheduling could be extended to also decide fusion boundaries using the same static timing model.
  • In memory-constrained embedded systems the reduced register traffic could translate into smaller on-chip memories without performance loss.

Load-bearing premise

Static timing information available at compile time is accurate and sufficient to guide safe dynamic PE formation and slack use without introducing new dependencies or needing runtime corrections.

What would settle it

Execute the evaluated workloads on fabricated hardware where measured delays deviate from the compile-time static timing model and check whether the reported 1.6x performance gain and absence of dependency violations still hold.

Figures

Figures reproduced from arXiv: 2606.21454 by Li-Shiuan Peh, Rakshith Harish, Rohan Juneja, Vishruti Ranjan.

Figure 1
Figure 1. Figure 1: Timing-aware spatial composition in COMPOSE. Fusing low-latency operations into virtual PEs absorbs un￾exploited timing slack, compressing the DFG depth and re￾solving inter-iteration dependencies without violating the global clock period. tiles, all with the goal of mapping compute kernels onto a regular fabric for high throughput and good energy efficiency. These architectures are mapped with a software … view at source ↗
Figure 2
Figure 2. Figure 2: Physical implementation and timing paths of a silicon-proven CGRA chip with support for COMPOSE. 0 250 500 750 1000 1250 Critical-path latency [ps] and normalized delay [FO4] LOAD MUL (*) SUB (-) CLT (<) CGT (>) ADD (+) ARS (>>>) CEQ (==) RS (>>) LS (<<) SELECT XOR (^) OR (|) CMERGE BR AND (&) MOVC NOP Router to Router NOP SEL BITWISE SHIFT ARTH MEM 12nm (ps) 40nm (ps) FO4 (12nm) FO4 (40nm) 807.0 ps (100%)… view at source ↗
Figure 3
Figure 3. Figure 3: Critical-path delays in 12nm and 40nm technolo￾gies. Absolute delays (ps) are shown alongside technology￾normalized FO4 counts, illustrating that operator logical depth remains largely unchanged across technology nodes. This normalization highlights the significant timing variance between different operation classes. Even within an ALU, many operations are effectively wiring or selection operations, such a… view at source ↗
Figure 4
Figure 4. Figure 4: Six kernels with code and dataflow graphs. Nodes are colored by per-node critical-path-delay (scale at left: [PITH_FULL_IMAGE:figures/full_fig_p005_4.png] view at source ↗
Figure 5
Figure 5. Figure 5: COMPOSE Framework The COMPOSE framework unifies circuit-level timing insights into a hardware-driven compilation strategy to optimize mapping for CGRAs. As illustrated in [PITH_FULL_IMAGE:figures/full_fig_p006_5.png] view at source ↗
Figure 6
Figure 6. Figure 6: STA-Aware Mapping with and without Recurrence Co-location, where each color represents a distinct composite. [PITH_FULL_IMAGE:figures/full_fig_p007_6.png] view at source ↗
Figure 7
Figure 7. Figure 7: Spatial composition of 2 PEs across 4 hops into 1 VPE. The interconnect microarchitecture enables combina￾tional traversal through intermediate PEs, while ALU input (𝐼1,𝐼2) and output (𝑅𝐸𝑆) bypass multiplexers facilitate the chaining of multiple operations. Standard registers, indicated in black, are bypassed to ensure single cycle propagation. is parametrically adaptable to various NoC routing microarchit… view at source ↗
Figure 8
Figure 8. Figure 8: Normalized cycle count across workloads comparing baselines and COMPOSE against the theoretical minimum. dither llist fft susan bfs viterbi tinydes popcount aes crc32 gemm convolutional2d spmspm sddmm 0 10 Normalized EDP Generic CGRA CGRA-Express-like Pre-Map In-Map COMPOSE Input-to-output latency Trend (Right Axis) Loop-carried path Bitwise-heavy 23.04 Linear algebra 0 20 Normalized Input￾to-Output Latenc… view at source ↗
Figure 9
Figure 9. Figure 9: Normalized EDP and input-to-output latency across workloads for all baselines and COMPOSE. dither llist fft susan bfs viterbi tinydes aes crc32 gemm convolutional2d sddmm 0 25 50 75 100 Utilization (%) Generic CGRA CGRA-Express-like Pre-Map In-Map COMPOSE [PITH_FULL_IMAGE:figures/full_fig_p011_9.png] view at source ↗
Figure 10
Figure 10. Figure 10: Improved PE utilization with COMPOSE. dither llist fft susan bfs viterbi tinydes aes crc32 gemm convolutional2d sddmm 0 25 50 75 Reduction in Registered Outputs (%) CGRA-Express-like Pre-Map In-Map COMPOSE [PITH_FULL_IMAGE:figures/full_fig_p011_10.png] view at source ↗
Figure 11
Figure 11. Figure 11: Reduction in intermediate register writes com￾pared to Generic CGRA. aes bfs dither fft llist susan crc32 popcount tinydes viterbi convolutional2d gemm sddmm spmspm 0.0 2.5 5.0 7.5 10.0 Normalized # of cycles Generic CGRA COMPOSE Single Hop Multi Hop [PITH_FULL_IMAGE:figures/full_fig_p011_11.png] view at source ↗
Figure 15
Figure 15. Figure 15: reports FP16 cycle counts. COMPOSE retains up to a 1.7× cycle reduction over Generic CGRA (on fft), smaller than the integer fft susan gemm conv2d spmspm sddmm 0 1 2 Normalized # of Cycles Generic CGRA CGRA-Express-like Pre-Map In-Map COMPOSE [PITH_FULL_IMAGE:figures/full_fig_p012_15.png] view at source ↗
Figure 14
Figure 14. Figure 14: Scalability on 8×8 CGRA for large DFGs; cycles normalized to COMPOSE show consistent improvements [PITH_FULL_IMAGE:figures/full_fig_p012_14.png] view at source ↗
read the original abstract

Coarse-Grained Reconfigurable Architectures (CGRAs) provide a spatially programmable substrate well suited for accelerating compute-intensive workloads with abundant parallelism. However, traditional CGRA execution models rely on rigid, fixed-size processing elements (PEs) that are statically bound to individual operations, which forces inter-iteration dependencies to be resolved through serialized scheduling. This limits throughput and reduces parallelism across loop iterations. Moreover, static execution schedules often fail to exploit available timing slack between operations, leading to resource underutilization and increased latency. The frequent registering of intermediate results further exacerbates pressure on register files and local memories, introducing data movement overheads that reduce energy efficiency, particularly in power or memory constrained environments. To address these challenges, we introduce COMPOSE, a composable CGRA architecture that enables dynamic formation of PEs at compile time guided by static timing information. By spatially fusing operations across loop iterations and selectively utilizing slack, COMPOSE resolves inter-iteration dependencies that limit throughput and enables low latency execution by reducing slack wastage. Additionally, the architecture reduces register file pressure by deferring output registration when intermediate values remain locally consumable, which significantly lowers redundant memory traffic. Across a diverse set of workloads, COMPOSE on average delivers 1.6x performance improvement and 2.9x EDP reduction over state-of-the-art (SOTA), at minimal area and power overheads.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit. Tearing a paper down is the easy half of reading it; the pith above is the substance, this is the friction.

Referee Report

2 major / 1 minor

Summary. The paper introduces COMPOSE, a composable CGRA that enables compile-time dynamic formation of processing elements (PEs) guided by static timing information. By spatially fusing operations across loop iterations, selectively consuming timing slack, and deferring registration of locally consumable values, the architecture aims to resolve inter-iteration dependencies, reduce slack wastage, and lower register-file and memory pressure in recurrence-bound loops. The central empirical claim is an average 1.6× performance improvement and 2.9× EDP reduction versus SOTA at minimal area/power overhead.

Significance. If the performance and EDP claims are substantiated by sound experiments and the static-timing assumption holds, the work would offer a practical way to improve CGRA utilization for loops that are currently limited by rigid PE sizing and serialized inter-iteration scheduling. The compile-time composability approach is a concrete contribution to the CGRA literature.

major comments (2)
  1. [Abstract] Abstract: the manuscript states concrete 1.6× performance and 2.9× EDP numbers yet supplies no experimental methodology, workload list, baseline descriptions, or error analysis. Without these details it is impossible to assess whether the reported gains are supported by the data.
  2. [Architecture / Timing model (exact section number not visible in provided text)] Architecture and timing model sections: the 1.6×/2.9× claim rests on the premise that static timing information available at compile time is accurate and complete enough to (a) safely fuse operations into dynamic PEs, (b) consume slack without creating unaccounted dataflow edges, and (c) defer registration without runtime correction. The manuscript provides no cycle-accurate simulation with perturbed delays, formal timing verification, or sensitivity analysis that this condition holds for the evaluated workloads; this assumption is load-bearing for the central performance claim.
minor comments (1)
  1. [Abstract] The abstract would be clearer if it briefly named the benchmark suite or loop characteristics used to obtain the reported averages.

Simulated Author's Rebuttal

2 responses · 0 unresolved

We thank the referee for the detailed and constructive review. We address each major comment below and indicate the revisions we will make to strengthen the manuscript.

read point-by-point responses

  1. Referee: [Abstract] Abstract: the manuscript states concrete 1.6× performance and 2.9× EDP numbers yet supplies no experimental methodology, workload list, baseline descriptions, or error analysis. Without these details it is impossible to assess whether the reported gains are supported by the data.

    Authors: We agree that the abstract would benefit from additional context on the evaluation. The full manuscript details the workloads, baselines (including SOTA CGRA designs), cycle-accurate simulation methodology, and performance metrics in the experimental evaluation section. To address the concern, we will revise the abstract to include a concise statement referencing the evaluation methodology, the set of recurrence-bound loop workloads, and the comparison baselines used to obtain the reported averages. revision: yes

  2. Referee: [Architecture / Timing model (exact section number not visible in provided text)] Architecture and timing model sections: the 1.6×/2.9× claim rests on the premise that static timing information available at compile time is accurate and complete enough to (a) safely fuse operations into dynamic PEs, (b) consume slack without creating unaccounted dataflow edges, and (c) defer registration without runtime correction. The manuscript provides no cycle-accurate simulation with perturbed delays, formal timing verification, or sensitivity analysis that this condition holds for the evaluated workloads; this assumption is load-bearing for the central performance claim.

    Authors: The architecture uses static timing analysis from standard synthesis flows to guide compile-time composition and slack consumption, which is a deliberate design choice to avoid runtime overhead. The reported results are obtained from cycle-accurate simulations that incorporate the timing model for the evaluated workloads. We acknowledge that explicit sensitivity analysis under perturbed delays or formal verification of all dataflow edges would further substantiate robustness. We will add a sensitivity study in the revised manuscript that perturbs interconnect and PE delays within realistic bounds and reports the resulting performance variation. revision: yes

Circularity Check

0 steps flagged

No circularity; architecture claims rest on external experimental evaluation

full rationale

The provided abstract and description contain no equations, fitted parameters, self-citations, or derivation steps that reduce to inputs by construction. Performance and EDP numbers are presented as measured outcomes over SOTA baselines rather than quantities forced by the timing model itself. The architecture proposal is therefore self-contained against external benchmarks with no load-bearing self-referential elements.

Axiom & Free-Parameter Ledger

0 free parameters · 1 axioms · 1 invented entities

Review is limited to the abstract; no free parameters, axioms, or invented entities are explicitly quantified. The core addition is the proposed composable architecture itself.

axioms (1)
  • domain assumption Traditional CGRAs rely on rigid fixed-size PEs statically bound to operations, forcing serialized inter-iteration scheduling.
    Explicitly stated as the starting limitation in the abstract.
invented entities (1)
  • Composable CGRA with compile-time dynamic PE formation no independent evidence
    purpose: To enable spatial fusion of operations across iterations and reduce register file pressure via deferred registration.
    This is the central new construct introduced by the paper.

pith-pipeline@v0.9.1-grok · 5799 in / 1272 out tokens · 22492 ms · 2026-06-26T12:47:48.136339+00:00 · methodology

discussion (0)

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Reference graph

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