Evaluating the Scalability of Binary and Ternary CNN Workloads on RRAM-based Compute-in-Memory Accelerators

Arunkumar Vaidyanathan; Jan Moritz Joseph; Jos\'e Cubero-Cascante; Noah Flohr; Rainer Leupers; Rebecca Pelke

REVIEW 3 major objections 4 minor 1 cited by

Evaluating the Scalability of Binary and Ternary CNN Workloads on RRAM-based Compute-in-Memory Accelerators

T0 review · 3 major / 4 minor · reviewed 2026-08-15 · deepseek-v4-flash

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Pith's one-line read Ternary neural networks tolerate wire resistance and low ADC resolution on RRAM crossbars better than binary ones, but use about 40% more energy per MAC.

desk verdict Useful simulation framework and a genuinely interesting TNN-vs-BNN robustness result, but the central 40% energy-efficiency penalty is not derivable from the printed energy model. read the letter →

arxiv 2505.07490 v3 pith:KIJLVPFR submitted 2025-05-12 eess.SP

José Cubero-Cascante , Rebecca Pelke , Noah Flohr , Arunkumar Vaidyanathan , Rainer Leupers , Jan Moritz Joseph This is my paper · ORCID

classification eess.SP

keywords compute-in-memoryRRAMcrossbarwireparasiticsADCresolutionbinaryneuralnetworksternarycalibrationenergyefficiency

verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

Ternary neural networks, whose weights and activations take values in {-1,0,1}, are more tolerant than binary networks to the two main scalability limits of RRAM-based compute-in-memory accelerators: resistive wire parasitics inside the crossbar and coarse analog-to-digital conversion. To support this claim, the paper builds a fast vectorised solver for crossbar output currents, a layer-wise ADC calibration rule, and a statistics-based energy model, then compares binary and ternary versions of two CNN workloads across five memristive technologies. The intended upshot is a practical design trade: ternary networks pay about 40% more energy per MAC, but they can use larger crossbars and 4-bit ADCs without losing baseline accuracy. If these models are right, accelerator designers should weigh input sparsity, not just weight precision, when choosing a quantization scheme.

What carries the argument

The load-bearing mechanism is Algorithm 1, a vectorised iterative conductance-reduction solver for 1T1R crossbars with resistive wires. It treats each column as a chain of parallel/series conductance combinations with the parasitic wire conductance $g_{wire}=1/R_p$, updating each column's effective conductance by $g_{per col} \leftarrow (g_{per col}+g_{row})\,g_{wire}/(g_{per col}+g_{row}+g_{wire})$ for every active row, then reading the output current as $g_{per col} V_{read}$. Because the iteration runs for all columns simultaneously using SIMD operations, it is fast enough for design-space sweeps and is the basis for the parasitics resilience comparison. The other two pieces are the ADC calibration rule of Eq. (6) (choose the layer scale so the $\mu \pm 3\sigma$ output range maps to the ADC's full scale) and the additive energy model of Eq. (9) that sums row-driver, ADC, and cell energies per MAC.

What would settle it

Reproduce the SPICE validation of Algorithm 1 with a complete 1T1R netlist using the same LRS/HRS values and wire-resistance sweep; if the output-current error exceeds 0.15% or the accuracy-vs-$R_p$ curves shift enough to change the TNN-vs-BNN ordering, the central claim is unsupported.

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Extended reading notes

Core claim

The central claim is that operand sparsity—the zeros in ternary inputs—is the deciding factor in how gracefully a workload degrades on an RRAM crossbar. In simulations, the ternary versions of LeNet-5 and VGG-7 maintain baseline top-1 accuracy at higher parasitic wire resistances than their binary counterparts across the considered memristive technologies and crossbar sizes. The same sparsity compresses the ADC output histograms, so a layer-wise calibration rule that sets the ADC step from the observed output distribution lets both workloads run at 4-bit ADC resolution with minimal accuracy loss, where 6-8 bits are needed without calibration. The cost is energy: because ternary encodings require two dot-product cycles per operation, their energy efficiency is on average 40% lower than the binary versions under the same 4-bit ADC and crossbar size.

Load-bearing premise

The whole comparison rests on Algorithm 1's iterative conductance reduction being a faithful model of 1T1R crossbar behaviour with resistive wires; the paper states a SPICE error below 0.15% without showing the netlist, comparison points, or validation methodology, so if that circuit model is wrong, the parasitics-resilience ranking loses its foundation.

Editorial extensions

If this is right

Designers can use the fast parasitics solver as a stand-in for SPICE when sweeping crossbar size and wire resistance during early accelerator exploration.
If the calibration result generalizes, 4-bit ADCs—much cheaper and less power-hungry than 6- or 8-bit parts—would suffice for binary and ternary CNN inference on RRAM crossbars.
The 40% energy penalty quantifies the real cost of ternary weights: for energy-constrained devices, binary networks remain the better default unless accuracy or parasitic tolerance forces the ternary choice.
The column-utilisation curves make explicit that energy efficiency saturates as crossbars grow, so there is an optimal crossbar size beyond which larger arrays buy nothing.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

Because the efficiency gap is computed at equal ADC resolution, a design that exploits the TNN's lower ADC requirement (say, 3-bit instead of 4-bit) could narrow or reverse the 40% energy penalty.
The $\mu \pm 3\sigma$ calibration rule is inherently tied to the calibration data; out-of-distribution inputs would push ADC outputs beyond the chosen range, so robust deployment would need per-dataset recalibration or a wider margin.
The same iterative conductance reduction might extend to multi-level cells and analog inputs if the conductance matrix entries are replaced by per-cell values, making the solver a building block for mixed-precision CIM simulation.

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Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Desk Editor's Note

read the letter

Short version: this is a working paper with a real contribution - the vectorized parasitic solver and the calibration method do what they claim, and the finding that TNNs tolerate parasitics and low ADC resolution better than BNNs is plausible and well-supported by the accuracy experiments. The problem is the headline energy number. Eq. 8 defines tile energy as O_t times a per-cycle term. Eq. 9 divides by O_t N_t M_t to get per-MAC energy. If O_t is the number of cycles (1 for BNN, 2 for TNN), it cancels, so the two-cycle overhead the text credits for the TNN penalty is divided out. If O_t is meant to be the number of full MVM operations, then the per-cycle term has to be multiplied by the cycle count, and the T-I case still omits the second ADC conversion. Either way, the printed equations do not produce a 40% penalty. You need an explicit denominator of N_t M_t or a factor 2 in the numerator for ternary mappings. The stress-test note got this right, and it is a load-bearing flaw for Section IV-F and the abstract.

What is genuinely new and good: the vectorized conductance-reduction solver (Algorithm 1) is a clever alternative to CrossSim, and the layer-wise ADC scale calibration (Eq. 6-7) convincingly shows 4-bit ADCs suffice with negligible accuracy loss across the two networks. The parasitics resilience comparison (Fig. 3) is the strongest part: the qualitative trend survives the model details, and the mechanism - operand sparsity - is independently observable, not an artifact. The authors also did the honest thing by using external energy parameters for the ADC and row drivers.

Soft spots beyond the energy model: the SPICE validation behind the 0.15% error claim is not shown (no netlist, no comparison points), there is no released code or data, no error bars or seeds for the accuracy or energy numbers, and the workload set is two networks. The 'active columns' typo in the discussion of Eq. 9 is minor but confusing. None of these would worry me much if the energy model were fixed.

Bottom line: the framework and the parasitics/ADC results are worth a serious referee. The energy-efficiency headline needs to be reworked or heavily qualified. If that is done, the paper would be a solid systems contribution. If it is not, the abstract overclaims.

Referee Report

3 major / 4 minor

Summary. The paper presents simulation models for evaluating RRAM-based compute-in-memory (CIM) accelerators running binary and ternary CNN workloads. The authors propose a vectorized algorithm (Algorithm 1) for computing crossbar output currents under resistive wire parasitics, claiming a maximum error below 0.15% against SPICE. They also propose an ADC calibration method with a layer-wise scale parameter and a statistics-based energy model. Using these components, they compare binary neural networks (BNNs) and ternary neural networks (TNNs) on LeNet-5 and VGG-7, concluding that TNNs are more resilient to wire parasitics, require lower ADC resolution (4 bits with calibration), but suffer a 40% reduction in energy efficiency. The paper is an extended simulation study with no hardware measurements.

Significance. If the energy-efficiency and resilience comparisons are correct, the paper provides useful design guidance for RRAM-based CIM accelerators, particularly the finding that operand sparsity in TNNs helps tolerate wire parasitics and coarse ADC quantization. The vectorized parasitics solver and the ADC calibration scheme are practical contributions that could be reused by other groups. The quantitative headline, however, is currently compromised by an inconsistency in the printed energy model: the two-cycle overhead for TNNs cancels out of Eq. (9), so the reported 40% energy-efficiency penalty is not derivable from the equations as written. The paper also omits the SPICE verification details behind the 0.15% error claim and reports no error bars or seeds. These issues are fixable with additional text and a corrected derivation, so the central methodology remains defensible.

major comments (3)

[Section III-C, Eqs. (8)-(9) and Section IV-F] The printed energy model cannot produce the claimed 40% energy-efficiency penalty for TNNs. Equation (8) defines E_t = O_t (N_t x_t E_RD + M_t E_ADC + N_t M_t x_t g_t V_R^2 T_R), and Eq. (9) divides by O_t N_t M_t to obtain E_MAC = x_t E_RD/M_t + E_ADC/N_t + x_t g_t V_R^2 T_R. The factor O_t cancels, so the number of MVM cycles per operation does not enter the per-MAC energy. If O_t counts full MVM operations, then T-I/T-II require two cycles per operation and Eq. (8) must have a factor of two in all three bracketed terms; if O_t counts cycles, then the total number of MACs for a ternary tile is O_t N_t M_t/2 and the denominator in Eq. (9) overcounts by a factor of two. Under either reading, the sentence in Section IV-F that the two dot-product cycles 'decrease overall energy efficiency' is not derivable from the model as printed. The 40% headline therefore needs a corrected cycle-counting equation and a recomputation before it can be accepted.
[Section III-A] The claim that Algorithm 1 computes output currents with a maximum error of 0.15% compared to SPICE is unsupported in the manuscript. There is no netlist description, no specification of the tested crossbar sizes, parasitic resistance ranges, or conductance values, and no list of comparison points. Since the parasitics-resilience comparison in Fig. 3 rests on the correctness of this circuit model, the authors should either add an appendix with the SPICE setup and the error-vs-configuration data or provide the verification scripts. This is a reproducibility gap, not necessarily an error, but it is load-bearing for the wire-parasitics claims.
[Section IV-C/D/E/F] All quantitative comparisons are single point estimates: 200 images are used for profiling, 100 for accuracy evaluation, and no random seeds or confidence intervals are reported for either the accuracy curves or the energy-efficiency numbers. Because the ADC-calibration scale s_l is fit to the profiling histograms, the reported 4-bit result and the TNN-vs-BNN gaps could vary with the calibration set; reporting variance over seeds or bootstraps would strengthen the three central claims.

minor comments (4)

[Section III-C, after Eq. (9)] The sentence 'a high number of active colums Nt is important to amortise the elevated energy cost of ADC conversions' should read 'active rows N_t'; the ADC energy term E_ADC/N_t is amortized by the number of rows per column, not columns, and the word 'colums' is misspelled.
[Section III-A, Algorithm 1] The text says 'the iteration loop (lines 5-7)' but the loop in Algorithm 1 spans lines 4-6; please correct the line reference.
[Section IV-F, Fig. 5] Fig. 5 reports energy efficiency for B-I and T-I only, while Figs. 3 and 4 include all four encoding schemes; a sentence explaining the omission of B-II and T-II from the energy comparison would help.
[Section IV-C and IV-D] The profiling uses 200 images and the accuracy evaluation uses 100 images; please clarify whether these are disjoint image sets and whether the same test images are reused across experiments.

Circularity Check

0 steps flagged · score 2.0 of 10

No significant circularity: the central BNN/TNN accuracy and ADC-resolution findings follow from measured operand sparsity, while the energy numbers combine external component models with a prior self-cited crossbar model. The main concern is that Eq. 9 cancels the two-cycle factor the text credits for the 40% TNN penalty, a consistency gap rather than a circular derivation.

full rationale

The paper's central parasitics and ADC-resolution comparisons are not circular. The TNN advantage is attributed to zero-valued operands: Section IV-D states 'The TNN workloads show a clear advantage against BNN, resulting from higher input sparsity,' and Section IV-C shows that ternary encodings yield narrower ADC output ranges. This is an independently observable property of threshold-quantized activations, not an output re-injected as an input. The ADC calibration method (Eqs. 6-7) is a calibration procedure on a small training-set subset and is then evaluated on a separate batch of 100 images, so the '4 bits are enough' result is a design evaluation, not a fitted parameter renamed as a prediction. The energy model in Eqs. 8-9 uses a prior self-cited crossbar model [5] plus external NeuroSim [15] and ADC [1] values; while [5] is authored by the present group, it is a previously published calibrated component model, and the comparison quantities (x_t, N_t, M_t) are profiled from the workloads, so no central claim reduces to a fit. The one serious internal issue is that Eq. 9 divides E_t by O_t N_t M_t, which cancels O_t identically, whereas Section IV-F explains the 40% TNN energy-efficiency loss by 'the need for two dot-product cycles per operation.' As printed, the model cannot produce that mechanism; reproducing the claimed penalty would require an unstated denominator or an extra factor. This is an equation/consistency defect in the derivation chain, not circularity in the sense of a prediction being equivalent to its inputs. The SPICE validation claim (error below 0.15%) is asserted without netlist or methodology details, but that is a verification gap. Overall, no load-bearing circular step was found.

Assumptions & free parameters 2 free parameters · 3 assumptions · 0 invented entities

The central claims rest on a small set of calibration parameters (s_l and the 3-sigma rule) and on standard circuit and energy-modeling assumptions. No new physical entities are introduced.

free parameters (2)

layer-wise ADC scale s_l = computed per layer via Eq (6)
Set by calibration on 200 profiling images to match the mean plus/minus 3-sigma range; controls the quantisation step in Eq (5) and directly affects the accuracy versus ADC resolution results in Fig 4.
calibration range factor (3 sigma) = 3 standard deviations
Hand-picked constant in Eq (7) that determines the target ADC range; no sensitivity analysis is provided to justify this choice.

assumptions (3)

domain assumption The iterative series/parallel conductance reduction in Algorithm 1 correctly models the 1T1R crossbar with resistive wire parasitics.
The algorithm is stated without proof and the SPICE validation is only claimed, not shown (Section III-A).
standard math ADC quantization is uniform with step delta_Q and the differential dot-product current is proportional to the weight-vector product (Eqs. 3-5).
Standard ideal-ADC assumption; reasonable for a first-order model.
domain assumption The energy model from Eqs. (8)-(9) approximates run-time MVM energy using average input statistics and external RD/ADC energy values.
Assumes additivity of component energies and that the statistics from the profiling set generalize to the full workload (Section III-C).

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Cite this review

Pith. "Pith review of Evaluating the Scalability of Binary and Ternary CNN Workloads on RRAM-based Compute-in-Memory Accelerators." pith.science (2026). https://pith.science/paper/KIJLVPFR

@misc{pith2026250507490,
  author       = {Pith},
  title        = {Pith review of: Evaluating the Scalability of Binary and Ternary CNN Workloads on RRAM-based Compute-in-Memory Accelerators},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/KIJLVPFR}},
  note         = {Machine review of arXiv:2505.07490}
}

read the original abstract

The increasing computational demand of Convolutional Neural Networks (CNNs) necessitates energy-efficient acceleration strategies. Compute-in-Memory (CIM) architectures based on Resistive Random Access Memory (RRAM) offer a promising solution by reducing data movement and enabling low-power in-situ computations. However, their efficiency is limited by the high cost of peripheral circuits, particularly Analog-to-Digital Converters (ADCs). Large crossbars and low ADC resolutions are often used to mitigate this, potentially compromising accuracy. This work introduces novel simulation methods to model the impact of resistive wire parasitics and limited ADC resolution on RRAM crossbars. Our parasitics model employs a vectorised algorithm to compute crossbar output currents with errors below 0.15% compared to SPICE. Additionally, we propose a variable step-size ADC and a calibration methodology that significantly reduces ADC resolution requirements. These accuracy models are integrated with a statistics-based energy model. Using our framework, we conduct a comparative analysis of binary and ternary CNNs. Experimental results demonstrate that the ternary CNNs exhibit greater resilience to wire parasitics and lower ADC resolution but suffer a 40% reduction in energy efficiency. These findings provide valuable insights for optimising RRAM-based CIM accelerators for energy-efficient deep learning.

Figures

Figures reproduced from arXiv: 2505.07490 by the authors.

**Figure 2.** ADC output histograms for each layer of the VGG-7 network. Each [PITH_FULL_IMAGE:figures/full_fig_p004_2.png] view at source ↗

**Figure 3.** Impact of wire parasitics on accuracy. Each subplot presents a unique [PITH_FULL_IMAGE:figures/full_fig_p005_3.png] view at source ↗

Figures from the paper (2 more)

**Figure 4.** Figure 4: Accuracy vs. ADC resolution, comparing calibrated and uncalibrated settings. Calibration allows low-resolution ADCs with minimal accuracy loss. [PITH_FULL_IMAGE:figures/full_fig_p006_4.png]

**Figure 5.** Figure 5: Energy efficiency and column utilisation vs. crossbar size. [PITH_FULL_IMAGE:figures/full_fig_p006_5.png]

Discussion (0). Continue with ORCID to comment.

Forward citations

Cited by 1 Pith paper

Reviewed papers in the Pith corpus that reference this work. Sorted by Pith novelty score. Full citation record

Optimizing Binary and Ternary Neural Network Inference on RRAM Crossbars using CIM-Explorer
cs.ET 2025-05 conditional novelty 6.0 of 10

CIM-Explorer integrates a TVM-based compiler, multiple RRAM crossbar mappings, and simulators into a design-space exploration flow for binary and ternary neural networks.

Reference graph

Works this paper leans on

23 extracted references · 19 canonical work pages · cited by 1 Pith paper

[1]

Modeling analog-digital-converter energy and area for compute-in-memory accel- erator design,

T. Andrulis, R. Chen, H.-S. Lee, J. S. Emer, and V . Sze, “Modeling analog-digital-converter energy and area for compute-in-memory accel- erator design,” 2024

work page 2024
[2]

CiMLoop: A flexible, accurate, and fast compute-in-memory modeling tool,

T. Andrulis, J. S. Emer, and V . Sze, “CiMLoop: A flexible, accurate, and fast compute-in-memory modeling tool,” in2024 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS), 2024, pp. 10–23

work page 2024
[3]

Parasitic-aware modeling and neural network training scheme for energy-efficient processing-in- memory with resistive crossbar array,

T. Cao, C. Liu, Y . Gao, and W. L. Goh, “Parasitic-aware modeling and neural network training scheme for energy-efficient processing-in- memory with resistive crossbar array,” IEEE Journal on Emerging and Selected Topics in Circuits and Systems , vol. 12, no. 2, pp. 436–444, 2022, conference Name: IEEE Journal on Emerging and Selected Topics in Circuits a...

work page 2022
[4]

Quasi-2d lead-tin perovskite memory devices fabricated by blade coating,

L. Chen, J. Xi, E. K. Tekelenburg, K. Tran, G. Portale, C. J. Brabec, and M. A. Loi, “Quasi-2d lead-tin perovskite memory devices fabricated by blade coating,” Small Methods, vol. 8, no. 2, p. 2300040, 2024. 345678 ADC resolution (bits) 0 20 40 60 80 100T op 1% accuracy VGG-7 - NX = 64 345678 ADC resolution (bits) T op 1% accuracy VGG-7 - NX = 128 345678 ...

work page 2024
[5]

A calibratable model for fast energy estimation of MVM operations on RRAM crossbars,

J. Cubero-Cascante, A. Vaidyanathan, R. Pelke, L. Pfeifer, R. Leupers, and J. M. Joseph, “A calibratable model for fast energy estimation of MVM operations on RRAM crossbars,” in 2024 IEEE 6th International Conference on AI Circuits and Systems (AICAS) . IEEE, 2024, pp. 537–538

work page 2024
[6]

Parallel programming of an ionic floating-gate memory array for scalable neuromorphic computing,

E. J. Fuller, S. T. Keene, A. Melianas, Z. Wang, S. Agarwal, Y . Li, Y . Tuchman, C. D. James, M. J. Marinella, J. J. Yang, A. Salleo, and A. A. Talin, “Parallel programming of an ionic floating-gate memory array for scalable neuromorphic computing,” Science, vol. 364, no. 6440, pp. 570–574, 2019

work page 2019
[7]

Larq: An Open-Source Library for Training Binarized Neural Networks,

L. Geiger and P. Team, “Larq: An Open-Source Library for Training Binarized Neural Networks,” Journal of Open Source Software , vol. 5, no. 45, p. 1746, Jan. 2020

work page 2020
[8]

Array programming with NumPy,

C. R. Harris, K. J. Millman, S. J. van der Walt, R. Gommers, P. Virtanen, D. Cournapeau, E. Wieser, J. Taylor, S. Berg, N. J. Smith, R. Kern, M. Picus, S. Hoyer, M. H. van Kerkwijk, M. Brett, A. Haldane, J. F. del R ´ıo, M. Wiebe, P. Peterson, P. G ´erard-Marchant, K. Sheppard, T. Reddy, W. Weckesser, H. Abbasi, C. Gohlke, and T. E. Oliphant, “Array progr...

2020

Show all 23 references

[9]

Accurate deep neural network inference using computational phase- change memory,

V . Joshi, M. Le Gallo, S. Haefeli, I. Boybat, S. R. Nandakumar, C. Piveteau, M. Dazzi, B. Rajendran, A. Sebastian, and E. Eleftheriou, “Accurate deep neural network inference using computational phase- change memory,” Nature Communications, vol. 11, no. 1, p. 2473, May 2020

2020
[10]

Deep learning,

Y . LeCun, Y . Bengio, and G. Hinton, “Deep learning,” Nature, vol. 521, no. 7553, pp. 436–444, May 2015

2015
[11]

Ternary weight networks,

B. Liu, F. Li, X. Wang, B. Zhang, and J. Yan, “Ternary weight networks,” in ICASSP 2023 - 2023 IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP) , 2023, pp. 1–5

2023
[12]

Compute-in-memory technologies for deep learning acceleration,

F.-h. Meng and W. D. Lu, “Compute-in-memory technologies for deep learning acceleration,” IEEE Nanotechnology Magazine , vol. 18, no. 1, pp. 44–52, 2024

2024
[13]

Analysis of vmm computation strategies to implement bnn applications on rram arrays,

V . Parmar, S. K. Kingra, S. Negi, and M. Suri, “Analysis of vmm computation strategies to implement bnn applications on rram arrays,” APL Machine Learning , vol. 1, no. 2, p. 026108, 04 2023

2023
[14]

Optimizing binary and ternary neural network inference on RRAM crossbars using CIM-Explorer,

R. Pelke, J. Cubero-Cascante, N. Bosbach, N. Degener, F. Idrizi, L. M. Reimann, J. M. Joseph, and R. Leupers, “Optimizing binary and ternary neural network inference on RRAM crossbars using CIM-Explorer,”
[15]

DNN+NeuroSim V2.0: An end-to-end benchmarking framework for compute-in-memory accelerators for on-chip training,

X. Peng, S. Huang, H. Jiang, A. Lu, and S. Yu, “DNN+NeuroSim V2.0: An end-to-end benchmarking framework for compute-in-memory accelerators for on-chip training,” IEEE Transactions on Computer- Aided Design of Integrated Circuits and Systems , vol. 40, no. 11, pp. 2306–2319, 2021

2021
[16]

Training and operation of an integrated neuromorphic network based on metal-oxide memristors,

M. Prezioso, F. Merrikh-Bayat, B. D. Hoskins, G. C. Adam, K. K. Likharev, and D. B. Strukov, “Training and operation of an integrated neuromorphic network based on metal-oxide memristors,” Nature, vol. 521, no. 7550, pp. 61–64, May 2015

2015
[17]

A full spectrum of computing-in-memory technologies,

Z. Sun, S. Kvatinsky, X. Si, A. Mehonic, Y . Cai, and R. Huang, “A full spectrum of computing-in-memory technologies,” Nature Electronics , vol. 6, no. 11, pp. 823–835, Nov 2023

2023
[18]

T. P. Xiao, C. H. Bennett, B. Feinberg, M. J. Marinella, and S. Agarwal. Crosssim: accuracy simulation of analog in-memory computing. [Online]. Available: https://github.com/sandialabs/cross-sim
[19]

Analysis and mitigation of parasitic resistance effects for analog in-memory neural network acceleration,

T. P. Xiao, B. Feinberg, J. N. Rohan, C. H. Bennett, S. Agarwal, and M. J. Marinella, “Analysis and mitigation of parasitic resistance effects for analog in-memory neural network acceleration,” Semiconductor Science and Technology, vol. 36, no. 11, p. 114004, 2021

2021
[20]

Fully hardware-implemented memristor convolutional neural network,

P. Yao, H. Wu, B. Gao, J. Tang, Q. Zhang, W. Zhang, J. J. Yang, and H. Qian, “Fully hardware-implemented memristor convolutional neural network,” Nature, vol. 577, no. 7792, pp. 641–646, Jan 2020

2020
[21]

Binary neural network with 16 mb rram macro chip for classification and online training,

S. Yu, Z. Li, P.-Y . Chen, H. Wu, B. Gao, D. Wang, W. Wu, and H. Qian, “Binary neural network with 16 mb rram macro chip for classification and online training,” in 2016 IEEE International Electron Devices Meeting (IEDM) , 2016, pp. 16.2.1–16.2.4

2016
[22]

A comprehensive review of Binary Neural Network,

C. Yuan and S. S. Agaian, “A comprehensive review of Binary Neural Network,” Artificial Intelligence Review , vol. 56, no. 11, pp. 12 949– 13 013, Nov. 2023, arXiv:2110.06804 [cs]

2023 arXiv
[2025]

Available: https://arxiv.org/abs/2505.14303

[Online]. Available: https://arxiv.org/abs/2505.14303

arXiv

Pith tools

Reviewed August 15, 2026 · model on record in the stance chip above.

[1] [1]

Modeling analog-digital-converter energy and area for compute-in-memory accel- erator design,

T. Andrulis, R. Chen, H.-S. Lee, J. S. Emer, and V . Sze, “Modeling analog-digital-converter energy and area for compute-in-memory accel- erator design,” 2024

work page 2024

[2] [2]

CiMLoop: A flexible, accurate, and fast compute-in-memory modeling tool,

T. Andrulis, J. S. Emer, and V . Sze, “CiMLoop: A flexible, accurate, and fast compute-in-memory modeling tool,” in2024 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS), 2024, pp. 10–23

work page 2024

[3] [3]

Parasitic-aware modeling and neural network training scheme for energy-efficient processing-in- memory with resistive crossbar array,

T. Cao, C. Liu, Y . Gao, and W. L. Goh, “Parasitic-aware modeling and neural network training scheme for energy-efficient processing-in- memory with resistive crossbar array,” IEEE Journal on Emerging and Selected Topics in Circuits and Systems , vol. 12, no. 2, pp. 436–444, 2022, conference Name: IEEE Journal on Emerging and Selected Topics in Circuits a...

work page 2022

[4] [4]

Quasi-2d lead-tin perovskite memory devices fabricated by blade coating,

L. Chen, J. Xi, E. K. Tekelenburg, K. Tran, G. Portale, C. J. Brabec, and M. A. Loi, “Quasi-2d lead-tin perovskite memory devices fabricated by blade coating,” Small Methods, vol. 8, no. 2, p. 2300040, 2024. 345678 ADC resolution (bits) 0 20 40 60 80 100T op 1% accuracy VGG-7 - NX = 64 345678 ADC resolution (bits) T op 1% accuracy VGG-7 - NX = 128 345678 ...

work page 2024

[5] [5]

A calibratable model for fast energy estimation of MVM operations on RRAM crossbars,

J. Cubero-Cascante, A. Vaidyanathan, R. Pelke, L. Pfeifer, R. Leupers, and J. M. Joseph, “A calibratable model for fast energy estimation of MVM operations on RRAM crossbars,” in 2024 IEEE 6th International Conference on AI Circuits and Systems (AICAS) . IEEE, 2024, pp. 537–538

work page 2024

[6] [6]

Parallel programming of an ionic floating-gate memory array for scalable neuromorphic computing,

E. J. Fuller, S. T. Keene, A. Melianas, Z. Wang, S. Agarwal, Y . Li, Y . Tuchman, C. D. James, M. J. Marinella, J. J. Yang, A. Salleo, and A. A. Talin, “Parallel programming of an ionic floating-gate memory array for scalable neuromorphic computing,” Science, vol. 364, no. 6440, pp. 570–574, 2019

work page 2019

[7] [7]

Larq: An Open-Source Library for Training Binarized Neural Networks,

L. Geiger and P. Team, “Larq: An Open-Source Library for Training Binarized Neural Networks,” Journal of Open Source Software , vol. 5, no. 45, p. 1746, Jan. 2020

work page 2020

[8] [8]

Array programming with NumPy,

C. R. Harris, K. J. Millman, S. J. van der Walt, R. Gommers, P. Virtanen, D. Cournapeau, E. Wieser, J. Taylor, S. Berg, N. J. Smith, R. Kern, M. Picus, S. Hoyer, M. H. van Kerkwijk, M. Brett, A. Haldane, J. F. del R ´ıo, M. Wiebe, P. Peterson, P. G ´erard-Marchant, K. Sheppard, T. Reddy, W. Weckesser, H. Abbasi, C. Gohlke, and T. E. Oliphant, “Array progr...

2020