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The Dawn of AI-Native EDA: Opportunities and Challenges of Large Circuit Models

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arxiv 2403.07257 v2 pith:KQZALDIB submitted 2024-03-12 cs.AR cs.ET

classification cs.ARcs.ET
keywords circuitdesignelectronicai-nativedatamodelstoolsai4eda
verification ladder T0 review T1 audit T2 compute T3 formal
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Within the Electronic Design Automation (EDA) domain, AI-driven solutions have emerged as formidable tools, yet they typically augment rather than redefine existing methodologies. These solutions often repurpose deep learning models from other domains, such as vision, text, and graph analytics, applying them to circuit design without tailoring to the unique complexities of electronic circuits. Such an AI4EDA approach falls short of achieving a holistic design synthesis and understanding, overlooking the intricate interplay of electrical, logical, and physical facets of circuit data. This paper argues for a paradigm shift from AI4EDA towards AI-native EDA, integrating AI at the core of the design process. Pivotal to this vision is the development of a multimodal circuit representation learning technique, poised to provide a comprehensive understanding by harmonizing and extracting insights from varied data sources, such as functional specifications, RTL designs, circuit netlists, and physical layouts. We champion the creation of large circuit models (LCMs) that are inherently multimodal, crafted to decode and express the rich semantics and structures of circuit data, thus fostering more resilient, efficient, and inventive design methodologies. Embracing this AI-native philosophy, we foresee a trajectory that transcends the current innovation plateau in EDA, igniting a profound shift-left in electronic design methodology. The envisioned advancements herald not just an evolution of existing EDA tools but a revolution, giving rise to novel instruments of design tools that promise to radically enhance design productivity and inaugurate a new epoch where the optimization of circuit performance, power, and area (PPA) is achieved not incrementally, but through leaps that redefine the benchmarks of electronic systems' capabilities.

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Cited by 7 Pith papers

Reviewed papers in the Pith corpus that reference this work. Sorted by Pith novelty score. Full citation record

  1. FedChip: Federated LLM for Artificial Intelligence Accelerator Chip Design

    cs.AR 2025-07 conditional novelty 6.0 of 10

    FedChip applies federated fine-tuning to LLM-based AI accelerator design, adding a 30k-sample dataset and a Chip@k metric, with a reported 77% quality improvement over high-end LLMs.

  2. RealBench: Benchmarking Verilog Generation Models with Real-World IP Designs

    cs.LG 2025-07 conditional novelty 6.0 of 10

    RealBench measures LLM Verilog generation on complex open-source IP cores with formal verification, and all tested models score near zero on full system designs.

  3. MMCircuitEval: A Comprehensive Multimodal Circuit-Focused Benchmark for Evaluating LLMs

    cs.LG 2025-07 conditional novelty 6.0 of 10

    A new multimodal benchmark of 3,614 circuit QA pairs shows that large language models perform worst on back-end layout and computation tasks, and that current models generally underperform on circuit design questions.

  4. CROP: Circuit Retrieval and Optimization with Parameter Guidance using LLMs

    cs.LG 2025-07 conditional novelty 6.0 of 10

    LLM-based retrieval-augmented tuning of EDA flow parameters found a 9.9% lower-power configuration on one industrial core than classical optimizers.

  5. Towards Reliable AI-Assisted Analog Design: Template-Constrained LLM Agents for SAR ADC Generation

    cs.SE 2026-07 conditional novelty 5.0 of 10

    ATLAS combines template-constrained LLM agents with Bayesian optimization to produce SAR ADC netlists that meet user specs in simulation.

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    MAVF, a multi-agent LLM pipeline, automates module-level IC verification document and testbench generation, claiming 50-83% human effort savings and accuracy gains over single-dialogue LLMs.

  7. QiMeng: Fully Automated Hardware and Software Design for Processor Chip

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    QiMeng is a proposed three-layer architecture for automating processor hardware and software design, with several published components but no integrated implementation yet.

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