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Streamlined Deployment for Quantized Neural Networks

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arxiv 1709.04060 v2 pith:KVXA6PVR submitted 2017-09-12 cs.CV

classification cs.CV
keywords quantizedneuraloperationsqnnsbenefitsbit-serialchallengecomputational
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Running Deep Neural Network (DNN) models on devices with limited computational capability is a challenge due to large compute and memory requirements. Quantized Neural Networks (QNNs) have emerged as a potential solution to this problem, promising to offer most of the DNN accuracy benefits with much lower computational cost. However, harvesting these benefits on existing mobile CPUs is a challenge since operations on highly quantized datatypes are not natively supported in most instruction set architectures (ISAs). In this work, we first describe a streamlining flow to convert all QNN inference operations to integer ones. Afterwards, we provide techniques based on processing one bit position at a time (bit-serial) to show how QNNs can be efficiently deployed using common bitwise operations. We demonstrate the potential of QNNs on mobile CPUs with microbenchmarks and on a quantized AlexNet, which is 3.5x faster than an optimized 8-bit baseline. Our bit-serial matrix multiplication library is available on GitHub at https://git.io/vhshn

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Reviewed papers in the Pith corpus that reference this work. Sorted by Pith novelty score. Full citation record

  1. FINN-GL: Generalized Mixed-Precision Extensions for FPGA-Accelerated LSTMs

    cs.LG 2025-06 conditional novelty 6.0 of 10

    FINN-GL adds ONNX Scan based LSTM support to the FINN compiler, enabling mixed-precision quantized LSTM layers to be synthesized into FPGA accelerators, demonstrated on a ConvLSTM for FI-2010 stock prediction.

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