Pith. sign in

REVIEW 4 major objections 5 minor 34 references

Single-electron tunneling PbS/InP neuromorphic computing building blocks

T0 review · 4 major / 5 minor · reviewed 2026-08-14 · deepseek-v4-flash

Challenge this review Re-run · record.json Download PDF Read on arXiv ↗ Review JSON

Pith's one-line read A single PbS/InP junction exhibits Coulomb blockade and trap-based memory, making it a candidate for ultra-low-energy neuromorphic synapses.

desk verdict Solid experimental building-block paper; the 0.2 fJ and 5 MHz claims rest on a fitted 200 ns parameter and need direct pulse-width data before they're cited. read the letter →

arxiv 1908.08602 v1 pith:KYHD76RA submitted 2019-08-22 physics.app-ph cond-mat.mes-hallcs.ET

Paulo F. Jarschel , Jin H. Kim , Louis Biadala , Maxime Berthe , Yannick Lambert , Richard M. Osgood , Gilles Patriarche , Bruno Grandidier
show 1 more author
Jimmy Xu
This is my paper · ORCID
classification physics.app-phcond-mat.mes-hallcs.ET
keywords single-electrontunnelingCoulombblockadePbSnanoplateletsInPneuromorphiccomputingsynapticplasticityshort-termmemorytrap-mediatedtransport
verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

This paper argues that a single PbS nanoplatelet sitting on p-type InP, with its self-formed oxide interface, behaves as a single-electron tunneling device and as a synaptic element. The same junction that shows a Coulomb-blockade plateau also shows memory, whose strength fades over seconds to hundreds of seconds, giving short- and long-term plasticity. Fitting the current-voltage curves to a double-junction SET circuit yields junction capacitances of about 0.2 to 0.5 aF and resistances of 4 to 20 GΩ. Extrapolating the fitted model, the authors estimate a minimum write pulse of about 200 ns, corresponding to a 5 MHz maximum operating frequency and an energy cost of roughly 0.2 fJ per synaptic operation. If those estimates hold, the structure is a candidate building block for large-scale, liquid-phase-grown neuromorphic networks.

What carries the argument

The load-bearing object is a double tunneling junction: the STM tip/vacuum/PbS nanoplatelet junction in series with the PbS/self-formed oxide/p-InP junction, each modeled as a resistor in series with a parallel resistor-capacitor pair. Fitting steady-state I-V curves gives $C_1 = 5 \times 10^{-19}$ F, $R_1 = 20$ GΩ for the tip junction and $C_2 = 2 \times 10^{-19}$ F, $R_2 = 4$ GΩ for the oxide junction, with a single-electron charging energy $E_e = e^2/(2C)$. The trap states inside the oxide are the memory: electrons trapped during positive bias raise the plateau threshold until they detrap, producing the observed memory fading. This SET-plus-trap mechanism is what converts a simple rectifying junction into a device with non-linear threshold behaviour, short- and long-term plasticity, and a predicted ultra-low switching energy.

What would settle it

Measure a single PbS/InP junction with pulses shorter than 200 ns and check whether its subsequent probe current still changes; also take the same I-V data at room temperature and at 77 K. If a sub-200 ns pulse produces a persistent conductivity change, or if the Coulomb staircase disappears when the stated resistance and temperature conditions are violated, the central energy and speed claim fails.

Watch

Extended reading notes

Core claim

The central claim is that the amorphous oxide layer between PbS and InP acts as a Coulomb island with trap states, so electron transport is a two-step process: tunneling from the STM tip through the nanoplatelet into an oxide trap, then out of the trap. This creates a Coulomb-blockade staircase with a single observable step, whose onset shifts with repeated scans because charge accumulates in oxide traps and detraps slowly. The authors show the same physical effect produces both long-term depression under 100 ms pulse trains and short-term depression after a single 1 ms pulse, and they emulate a spiking neuron by feeding random weighted pulses through the measured transfer function. The paper's quantitative claim is that the fitted SET parameters imply a 200 ns minimum write pulse, a 5 MHz operating ceiling, and about 0.2 fJ dissipated per operation, compared with roughly picojoule-scale biological synapses.

Load-bearing premise

The energy and frequency estimates assume that the fitted 200 ns constant-current response is the shortest pulse that changes the device conductivity and that the fitted capacitances and resistances accurately represent the physical junctions; if the plateau comes from trap-limited conduction rather than Coulomb charging, those numbers would not transfer to real devices.

Editorial extensions

If this is right

  • The same junction can serve as both a weighted synapse and a spiking neuron in an emulated neural network, since voltage pulses change its conductivity and threshold while probe pulses read the state.
  • Arrays of such devices could be grown in liquid phase and stacked vertically, providing a scalable route to neuromorphic hardware without lithographic single-electron transistors.
  • The device's memory-fading gives natural short-term plasticity, with time constants near 1 s and 100 s, which can be used for temporal signal processing.
  • The projected energy and speed of a synaptic operation, about 0.2 fJ and 5 MHz, sit below the roughly picojoule and kilohertz figures of biological synapses.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

  • If the 200 ns plateau is a genuine minimum write pulse rather than a measurement artifact, then read/write separation in an array would require write pulses near 200 ns and shorter read pulses, which may create a speed-accuracy tradeoff not discussed in the paper.
  • Because the oxide layer is inhomogeneous and its thickness varies under each nanoplatelet, device-to-device variation in trap density could produce a population of synapses with different thresholds and time constants, which a network could exploit as a form of stochastic or heterogeneous computation.
  • The condition $E_e > k_B T$ suggests room-temperature operation is plausible in principle, but all transport measurements were taken at 77 K; a direct room-temperature I-V test would be a natural follow-up.
  • The trap-mediated SET mechanism implies that the memory is volatile by construction; using it for long-term storage would require periodic refresh or a second, non-volatile mechanism, which the paper does not explore.
Share X Bluesky LinkedIn Reddit HN

Signed reviews

No signed human review yet.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Referee Report

4 major / 5 minor

Summary. The paper reports scanning tunneling spectroscopy measurements on PbS nanoplatelets grown on p-type InP with a self-formed oxide layer, observing a voltage plateau in I-V curves that shifts with repeated scans, a current that depends on acquisition time and pulse delay, and memory-like relaxation behavior. The authors model the junction as a double-junction single-electron tunneling (SET) circuit, extract capacitances and resistances from a least-squares fit of the I-V curves, and fit the time-dependent current response to a fast constant component followed by an exponential decay. From this they extrapolate a 200 ns minimum pulse width for conductance change, a 5 MHz maximum operating frequency, and a 0.2 fJ minimum Joule energy per synaptic operation. They further simulate short- and long-term plasticity and a spiking-neuron response using the fitted model. The central quantitative claims therefore rest on the fitted parameters and the 200 ns timescale.

Significance. The qualitative observations, including a reproducible plateau, threshold shifting, and memory-fading behavior in a scalable liquid-phase-grown nanostructure, are of potential interest for neuromorphic device research. If the quantitative energy and speed claims were validated by direct measurements, they would be a strong selling point for ultra-low-energy synaptic hardware. Credit is due for providing real experimental data and for testing the data against a SET equivalent-circuit framework. However, the load-bearing quantitative predictions (0.2 fJ, 5 MHz, 200 ns) are not directly measured, lack error bars, and are derived from a fitting model described only verbally. The plasticity demonstrations are simulations, not experimentally validated predictions. These issues undermine the paper's headline claims as currently presented.

major comments (4)
  1. [Section 3 (Figure 4b) and Section 4] The 200 ns minimum pulse width underlying the 5 MHz and 0.2 fJ claims is not directly measured; it is recovered from fitting the integrated current response to a two-component model (700 pA constant high-current response for 200 ns followed by a 4 ms exponential decay), whereas the raw data in Figure 3(a) and 3(c) are acquired on timescales of 0.07–4.6 s and ~30 ms respectively. The paper provides no error analysis, no model-selection justification, and no control experiment (e.g., short-pulse measurements or characterization of the current preamplifier bandwidth) to demonstrate that the 200 ns feature is physical rather than an artifact of the deconvolution. Consequently, the assertion that pulses shorter than 200 ns have no effect on the conductance is unsupported.
  2. [Section 4] The minimum energy estimate of 0.2 fJ is computed as the Joule energy for a 1 V, 1 nA pulse of 200 ns duration, using the steady-state plateau current from Figure 3(a). However, the fitted impulse response in Section 3 gives a constant high-current response of 700 pA, not 1 nA, and the manuscript does not justify why the plateau current should apply to a 200 ns write pulse. The paper should either directly measure the energy of a switching event or explicitly state the assumptions and discuss how the estimate changes if the operating point or the pulse current is different.
  3. [Section 3] The SET model fitting is described only verbally: the text states that a combination of diode curves and sigmoid functions is used and that C1, R1, C2, R2 are extracted from the plateau onset, width, slope, and edge curvature. No equations, confidence intervals, or goodness-of-fit metrics are provided. The extracted C2 = 2×10^-19 F is about three orders of magnitude smaller than a parallel-plate estimate for a ~100-nm nanoplatelet with a ~1-nm oxide, and the explanations (dead layers, depletion) are qualitative. Without a reproducible fitting procedure and error estimates, the physical interpretation of the fitted parameters as evidence of single-electron tunneling is not established, and alternative trap-limited conduction mechanisms are not excluded.
  4. [Section 3 and Figure 5] The plasticity demonstrations in Figure 5 are simulations performed using the fitted model parameters, yet the text presents them as if they were predictions of the physical device, blurring the line between measurement and extrapolation. The distinction between measured data and model output should be made explicit in the main text and in the figure captions; otherwise, the experimental evidence for short- and long-term plasticity is overstated.
minor comments (5)
  1. [Abstract / Introduction / Conclusion] The abstract and introduction state that the minimum energy is "of the order of 1 fJ," while Section 4 and the conclusion state 0.2 fJ; this numerical inconsistency should be reconciled.
  2. [Section 3] The term "Quantum Blockade" is used with reference [6], which is titled "Coulomb blockade of single-electron tunneling"; please standardize the terminology to "Coulomb blockade."
  3. [Section 2] There is a typo: "The sample is negatively bias at V0" should be "The sample is negatively biased at V0."
  4. [Section 2] There is a stray Chinese full-width comma in the sentence "Moreover，there is a memory fading equivalence"; please replace it with a standard comma.
  5. [Section 4] The statement "Pulses shorter than this will not have any effect" is too strong, as no such short pulses were applied; suggest softening to "are predicted to have no effect according to the fitted model."

Circularity Check

1 steps flagged · score 6.0 of 10

The 5 MHz speed and 0.2 fJ energy claims are arithmetic restatements of the fitted 200 ns impulse-response parameter, not independently measured write-pulse thresholds.

  1. fitted input called prediction [Section 3, SET modelling, impulse-response fit; Section 4, Applications to neuromorphic computing, energy/speed estimate]
    "obtaining 700 pA for the highest current response, 1 pA for the minimum current, a duration of 200 ns for the constant high-current response... From the fitted parameters of Figure 4, the voltage pulse width necessary to cause a change in the conductivity is approximately 200 ns, equivalent to a maximum frequency of 5 MHz. ... the energy dissipated purely by Joule effect is of the order of 0.2 fJ."

    The 200 ns value is one of four parameters obtained by fitting a two-component impulse-response model to the time-resolved current data; it is not a directly measured write-pulse threshold. Section 4 then relabels this fitted 'duration of the constant high-current response' as 'the voltage pulse width necessary to cause a change in the conductivity,' and the headline numbers are arithmetic transformations of it: 5 MHz = 1/(200 ns) and 0.2 fJ = (1 V)(1 nA)(200 ns). Thus the quantitative speed/energy predictions are, by construction, restatements of the fitted parameter rather than independent predictions, and the claim that pulses shorter than 200 ns have no effect is an assumption of the model, not a measured result.

full rationale

The experimental core—Coulomb staircase, plateau shifts, and memory/memory-fading behaviors in Figures 1 through 3—is self-contained and not circular. The fitted SET capacitances and resistances are used consistently in the consistency checks and in modeling the I-V curves. However, the neuromorphic headline quantities are not independent: the 200 ns 'minimum pulse width' is the fitted duration of the fast charging component from the same impulse-response data, and the 5 MHz speed and 0.2 fJ energy are direct algebraic transforms of that fit (f = 1/200 ns; E = 1 V × 1 nA × 200 ns). No direct pulse-width experiment establishes that shorter pulses have no effect. The Figure 5 plasticity demonstrations use the same fitted model, so they reproduce the model rather than provide an external test. This is a partial circularity affecting the quantitative performance claims, while the qualitative device behavior remains an experimental result.

Assumptions & free parameters 8 free parameters · 7 assumptions · 0 invented entities

The central neuromorphic figures of merit depend on a set of circuit parameters and a pulse duration that are all fitted to the same experimental data. The physical interpretation of the oxide traps as Coulomb islands is an assumption supported by indirect evidence, and the double-junction SET model is adopted from prior literature without an independent microscopic derivation.

free parameters (8)
  • Tip-vacuum-PbS junction capacitance C1 = 5 x 10^-19 F
    Obtained by least-squares fitting of I-V curves to a combination of diode curves and sigmoid functions (Section 3). Used in the SET model and to estimate operating conditions.
  • Tip-vacuum-PbS junction resistance R1 = 20 GΩ
    Obtained from the same I-V fitting (Section 3). Used in the SET model and to check the resistance condition.
  • PbS-oxide-InP junction capacitance C2 = 2 x 10^-19 F
    Obtained from the same I-V fitting (Section 3). Relevant to the charging energy and temperature limit.
  • PbS-oxide-InP junction resistance R2 = 4 GΩ
    Obtained from the same I-V fitting (Section 3). Used in the SET model.
  • High-current response duration = 200 ns
    Extracted from the impulse response model fit to time-resolved data (Figure 4b); used as the assumed minimum pulse width for synaptic operation in Section 4, directly feeding the 0.2 fJ and 5 MHz estimates.
  • Exponential decay time constant = 4 ms
    From the same impulse response fit (Figure 4b); characterizes the discharging rate in the model.
  • Peak current in impulse response = 700 pA
    Fitted maximum current response in the impulse response model (Figure 4b), used for modeling the time-dependent response.
  • Minimum current in impulse response = 1 pA
    Fitted minimum current response in the impulse response model (Figure 4b), used for modeling the response.
assumptions (7)
  • standard math Coulomb blockade charging energy Ee = e^2/(2C)
    Equation (1) in Section 3, used to derive conditions for observing single-electron tunneling.
  • standard math RC discharge time tau_RC = RC
    Equation (2) in Section 3, used to compare with the quantum lifetime.
  • standard math Uncertainty principle bound Δt ≥ ħC/e^2
    Equation (3) in Section 3, used to set the resistance condition R >> 4 kΩ.
  • standard math Thermal condition Ee > kBT
    Equation (5) in Section 3, used to estimate the temperature limit for observing SET.
  • domain assumption The amorphous interface layer contains trap states that act as Coulomb islands
    Section 2 and 3, inferred from STEM/EDS and transport data; central to the SET interpretation and the memory mechanism.
  • domain assumption The observed I-V plateau is due to single-electron charging rather than another conduction mechanism
    Section 3, supported by fitting but not independently verified; this is the key physical interpretation on which the neuromorphic metrics rest.
  • domain assumption The double-junction SET resistor-capacitor network describes transport in this structure
    Section 3, cited references [30,31]; the fitted parameters are only meaningful if this model applies.

how reviews work

0 comments
Cite this review

Pith. "Pith review of Single-electron tunneling PbS/InP neuromorphic computing building blocks." pith.science (2026). https://pith.science/paper/KYHD76RA

@misc{pith2026190808602,
  author       = {Pith},
  title        = {Pith review of: Single-electron tunneling PbS/InP neuromorphic computing building blocks},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/KYHD76RA}},
  note         = {Machine review of arXiv:1908.08602}
}
read the original abstract

We study single-electron tunneling (SET) characteristics in crystalline PbS/InP junctions, that exhibit single-electron Coulomb-blockade staircases along with memory and memory-fading behaviors. This gives rise to both short-term and long-term plasticities as well as a convenient non-linear response, making this structure attractive for neuromorphic computing applications. For further insights into this prospect, we predict typical behaviors relevant to the field, obtained by an extrapolation of experimental data in the SET framework. The estimated minimum energy required for a synaptic operation is in the order of 1 fJ, while the maximum frequency of operation can reach the MHz range.

Discussion (0). Continue with ORCID to comment.

Reference graph

Works this paper leans on

34 extracted references · 34 canonical work pages

  1. [1]

    Single Charge Tunneling: Coulomb Blockade Phenomena in Nanstructures,

    H. Grabert and M. H. Devoret, "Single Charge Tunneling: Coulomb Blockade Phenomena in Nanstructures," Plenum, 1991

    work page 1991

  2. [2]

    Correlated discrete transfer of single electrons in ultrasmall tunnel junctions,

    K. K. Likharev, "Correlated discrete transfer of single electrons in ultrasmall tunnel junctions," IBM Journal of Research and Development, vol. 32, pp. 144-158, 1 1988

    work page 1988

  3. [3]

    The single-electron transistor,

    M. A. Kastner, "The single-electron transistor," Rev. Mod. Phys., vol. 64, no. 3, pp. 849-858, 7 1992

    work page 1992

  4. [4]

    Metrological applications of single electron tunneling,

    J. M. Martinis, "Metrological applications of single electron tunneling," in Proceedings of Conference on Precision Electromagnetic Measurements Digest, 1994

    work page 1994

  5. [5]

    Application of single electron tunneling: Precision capacitance ratio measurements,

    A. F. Clark, N. M. Zimmerman, E. R. Williams, A. Amar, D. Song, F. C. Wellstood, C. J. Lobb and R. J. Soulen, "Application of single electron tunneling: Precision capacitance ratio measurements," Applied Physics Letters, vol. 66, pp. 2588-2590, 1995

    work page 1995

  6. [6]

    Coulomb blockade of single-electron tunneling, and coherent oscillations in small tunnel junctions,

    D. V. Averin and K. K. Likharev, "Coulomb blockade of single-electron tunneling, and coherent oscillations in small tunnel junctions," Journal of Low Temperature Physics, vol. 62, pp. 345-373, 01 2 1986

    work page 1986

  7. [7]

    Coulomb blockade in monolayer MoS2 single electron transistor,

    K. Lee, G. Kulkarni and Z. Zhong, "Coulomb blockade in monolayer MoS2 single electron transistor," Nanoscale, vol. 8, no. 14, pp. 7755-7760, 2016

    work page 2016

  8. [8]

    Gold Nanoparticles on Functionalized Silicon Substrate under Coulomb Blockade Regime: An Experimental and Theoretical Investigation,

    O. Pluchery, L. Caillard, P. Dollfus and Y. J. Chabal, "Gold Nanoparticles on Functionalized Silicon Substrate under Coulomb Blockade Regime: An Experimental and Theoretical Investigation," The Journal of Physical Chemistry B, vol. 122, pp. 897-903, 2018

    work page 2018

Show all 34 references
  1. [9]

    Coulomb blockade in an atomically thin quantum dot coupled to a tunable Fermi reservoir,

    M. Brotons-Gisbert, A. Branny, S. Kumar, R. Picard, R. Proux, M. Gray, K. S. Burch, K. Watanabe, T. Taniguchi and B. D. Gerardot, "Coulomb blockade in an atomically thin quantum dot coupled to a tunable Fermi reservoir," Nature Nanotechnology, vol. 14, pp. 442-446, 2019

    2019

  2. [10]

    Single electron tunneling technology for neural networks,

    M. J. Goossens, C. J. M. Verhoeven and A. H. M. van Roermund, "Single electron tunneling technology for neural networks," in Proceedings of Fifth International Conference on Microelectronics for Neural Networks, 1996

    1996

  3. [11]

    Neuronal synchrony detection on single-electron neural networks,

    T. Oya, T. Asai, R. Kagaya, T. Hirose and Y. Amemiya, "Neuronal synchrony detection on single-electron neural networks," Chaos, Solitons & Fractals, vol. 27, pp. 887-894, 2006

    2006

  4. [12]

    Bio-Inspired Oscillators with Single-Electron Transistors: Circuit Simulation and Input Encoding Example,

    J. G. Guimarães and A. R. S. Romariz, "Bio-Inspired Oscillators with Single-Electron Transistors: Circuit Simulation and Input Encoding Example," Journal of Computational and Theoretical Nanoscience, vol. 10, pp. 2563-2567, 2013

    2013

  5. [13]

    A Spiking Neural Network implemented with Single-Electron Transistors and NoCs,

    B. dos Santos Pês, J. G. Guimarães, E. Oroski and M. J. do Couto Bonfim, "A Spiking Neural Network implemented with Single-Electron Transistors and NoCs," Nano Communication Networks, vol. 17, pp. 21-29, 2018

    2018

  6. [14]

    A million spiking-neuron integrated circuit with a scalable communication network and interface,

    P. A. Merolla, J. V. Arthur, R. Alvarez-Icaza, A. S. Cassidy, J. Sawada, F. Akopyan, B. L. Jackson, N. Imam, C. Guo, Y. Nakamura, B. Brezzo, I. Vo, S. K. Esser, R. Appuswamy, B. Taba, A. Amir, M. D. Flickner, W. P. Risk, R. Manohar and D. S. Modha, "A million spiking-neuron in...

    2014

  7. [15]

    Neurogrid: A Mixed-Analog-Digital Multichip System for Large-Scale Neural Simulations,

    B. V. Benjamin, P. Gao, E. McQuinn, S. Choudhary, A. R. Chandrasekaran, J. Bussat, R. Alvarez-Icaza, J. V. Arthur, P. A. Merolla and K. Boahen, "Neurogrid: A Mixed-Analog-Digital Multichip System for Large-Scale Neural Simulations," Proceedings of the IEEE, vol. 102, pp. 699-7...

    2014

  8. [16]

    A wafer-scale neuromorphic hardware system for large-scale neural modeling,

    J. Schemmel, D. Briiderle, A. Griibl, M. Hock, K. Meier and S. Millner, "A wafer-scale neuromorphic hardware system for large-scale neural modeling," in Proceedings of 2010 IEEE International Symposium on Circuits and Systems, 2010

    2010

  9. [17]

    The SpiNNaker Project,

    S. B. Furber, F. Galluppi, S. Temple and L. A. Plana, "The SpiNNaker Project," Proceedings of the IEEE, vol. 102, pp. 652-665, 5 2014

    2014

  10. [18]

    Design of ion-implanted MOSFET's with very small physical dimensions,

    R. H. Dennard, F. H. Gaensslen, V. L. Rideout, E. Bassous and A. R. LeBlanc, "Design of ion-implanted MOSFET's with very small physical dimensions," IEEE Journal of Solid-State Circuits, vol. 9, pp. 256-268, 10 1974

    1974

  11. [19]

    Pattern classification by memristive crossbar circuits using ex situ and in situ training,

    F. Alibart, E. Zamanidoost and D. B. Strukov, "Pattern classification by memristive crossbar circuits using ex situ and in situ training," Nature Communications, vol. 4, pp. 2072 EP -, 25 6 2013

    2013

  12. [20]

    Training and operation of an integrated neuromorphic network based on metal-oxide memristors,

    M. Prezioso, F. Merrikh-Bayat, B. D. Hoskins, G. C. Adam, K. K. Likharev and D. B. Strukov, "Training and operation of an integrated neuromorphic network based on metal-oxide memristors," Nature, vol. 521, pp. 61 EP -, 07 5 2015

    2015

  13. [21]

    Single-electron tunneling in a single PbS nanocrystal nucleated on 11- mercaptoundecanoic acid self-assembled monolayer at room temperature,

    P. Jiang, Z.-F. Liu and S.-M. Cai, "Single-electron tunneling in a single PbS nanocrystal nucleated on 11- mercaptoundecanoic acid self-assembled monolayer at room temperature," Journal of Applied Physics, vol. 90, pp. 2039- 2041, 2001

    2001

  14. [22]

    Self-Assembled Networked PbS Distribution Quantum Dots for Resistive Switching and Artificial Synapse Performance Boost of Memristors,

    X. Yan, Y. Pei, H. Chen, J. Zhao, Z. Zhou, H. Wang, L. Zhang, J. Wang, X. Li, C. Qin, G. Wang, Z. Xiao, Q. Zhao, K. Wang, H. Li, D. Ren, Q. Liu, H. Zhou, J. Chen and P. Zhou, "Self-Assembled Networked PbS Distribution Quantum Dots for Resistive Switching and Artificial Synapse...

    2019

  15. [23]

    Synaptic Energy Use and Supply,

    J. Harris, R. Jolivet and D. Attwell, "Synaptic Energy Use and Supply," Neuron, vol. 75, pp. 762-777, 2012

    2012

  16. [24]

    Trap-Free Heterostructure of PbS Nanoplatelets on InP(001) by Chemical Epitaxy,

    L. Biadala, W. Peng, Y. Lambert, J. H. Kim, D. Canneson, A. Houppe, M. Berthe, D. Troadec, D. Deresmes, G. Patriarche, T. Xu, X. Pi, X. Wallart, C. Delerue, M. Bayer, J. Xu and B. Grandidier, "Trap-Free Heterostructure of PbS Nanoplatelets on InP(001) by Chemical Epitaxy," ACS...

    1961

  17. [25]

    Measuring charge trap occupation and energy level in CdSe/ZnS quantum dots using a scanning tunneling microscope,

    M. R. Hummon, A. J. Stollenwerk, V. Narayanamurti, P. O. Anikeeva, M. J. Panzer, V. Wood and V. Bulovi ć ć, "Measuring charge trap occupation and energy level in CdSe/ZnS quantum dots using a scanning tunneling microscope," Phys. Rev. B, vol. 81, no. 11, p. 115439, 3 2010

    2010

  18. [26]

    Room temperature photocurrent response of PbS/InP heterojunction,

    Z. Liu, J. H. Kim, G. E. Fernandes and J. Xu, "Room temperature photocurrent response of PbS/InP heterojunction," Applied Physics Letters, vol. 95, p. 231113, 2009

    2009

  19. [27]

    Deep level transient spectroscopy of interface and bulk trap states in InP metal/oxide/semiconductor structures,

    M. Inuishi and B. W. Wessels, "Deep level transient spectroscopy of interface and bulk trap states in InP metal/oxide/semiconductor structures," Thin Solid Films, vol. 103, pp. 141-153, 1983

    1983

  20. [28]

    Fermi level pinning during oxidation of atomically clean n‐InP(110),

    K. A. Bertness, T. Kendelewicz, R. S. List, M. D. Williams, I. Lindau and W. E. Spicer, "Fermi level pinning during oxidation of atomically clean n‐InP(110)," Journal of Vacuum Science & Technology A, vol. 4, pp. 1424-1426, 1986

    1986

  21. [29]

    Probing the Carrier Capture Rate of a Single Quantum Level,

    M. Berthe, R. Stiufiuc, B. Grandidier, D. Deresmes, C. Delerue and D. Stiévenard, "Probing the Carrier Capture Rate of a Single Quantum Level," Science, vol. 319, pp. 436-438, 2008

    2008

  22. [30]

    I-V characteristics of coupled ultrasmall-capacitance normal tunnel junctions,

    K. Mullen, E. Ben-Jacob, R. C. Jaklevic and Z. Schuss, "I-V characteristics of coupled ultrasmall-capacitance normal tunnel junctions," Phys. Rev. B, vol. 37, no. 1, pp. 98-105, 1 1988

    1988

  23. [31]

    From wave-functions to current-voltage characteristics: overview of a Coulomb blockade device simulator using fundamental physical parameters,

    J. Sée, P. Dollfus, S. Galdin and P. Hesto, "From wave-functions to current-voltage characteristics: overview of a Coulomb blockade device simulator using fundamental physical parameters," Journal of Computational Electronics, vol. 5, pp. 35- 48, 01 3 2006

    2006

  24. [32]

    Scanning-tunneling-microscope observations of Coulomb blockade and oxide polarization in small metal droplets,

    R. Wilkins, E. Ben-Jacob and R. C. Jaklevic, "Scanning-tunneling-microscope observations of Coulomb blockade and oxide polarization in small metal droplets," Phys. Rev. Lett., vol. 63, no. 7, pp. 801-804, 8 1989

    1989

  25. [33]

    Anomalous Capacitance of Thin Dielectric Structures,

    C. A. Mead, "Anomalous Capacitance of Thin Dielectric Structures," Phys. Rev. Lett., vol. 6, no. 10, pp. 545-546, 5 1961

    1961

  26. [34]

    Origin of the dielectric dead layer in nanoscale capacitors,

    M. Stengel and N. A. Spaldin, "Origin of the dielectric dead layer in nanoscale capacitors," Nature, vol. 443, pp. 679-682, 2006

    2006

Pith tools

Reviewed August 14, 2026 · model on record in the stance chip above.