REVIEW 4 major objections 6 minor 77 references
Current AI agents improve real computer-architecture designs only when humans supply the harness and simulator feedback; without that support they fail as autonomous architects.
Reviewed by Pith at T0; open to challenge. T0 means a machine referee read the full paper against a public rubric. the ladder, T0–T4 →
T0 review · grok-4.5
2026-07-12 01:15 UTC pith:LOTMTVYJ
load-bearing objection Real multi-simulator architecture-agent benchmark with a useful L1/L2/L3 support ladder; the assistant-vs-architect framing is directionally right but rests on a single-seed, harness-confounded snapshot. the 4 major comments →
ArchEval: Measuring AI Agents as Computer Architects
The pith
A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.
Core claim
With a prepared harness and repeated simulator feedback, current LLM agents already improve real architecture designs across diverse simulators and meet or exceed challenge baselines; once that support is stripped away, most fall below baseline, and even the strongest configuration reaches only about 1.21× geomean baseline-normalized performance with a 15% performance-modeling pass rate—so today’s agents function as optimization assistants rather than autonomous architects.
What carries the argument
The L1/L2/L3 support ladder: the same architecture task under full harness with repeated verifier feedback (L1), simulator source the agent must assemble into experiments (L2), and static workload evidence with no runnable feedback before submission (L3). Paired with baseline-normalized verifier scores and full trajectory logs, the ladder separates assisted search from simulator-tool use and pre-feedback design judgment.
Load-bearing premise
The general map of “current agents as architects” rests on a single-seed evaluation of twenty intentionally lightweight, budget-bounded challenges with mixed-strength baselines and some process labels produced by one of the agents under test.
What would settle it
A multi-seed re-run in which several independent agent configurations, without the L1 harness, consistently beat the same baselines with calibrated predictions (performance-modeling pass rate well above 15%) across the twenty challenges—or L1 gains vanishing once stronger baselines or longer industrial-scale verifiers replace the lightweight ones.
If this is right
- Near-term use of agents should keep them inside prepared verifier-simulator loops rather than unsupervised early-stage design.
- Progress should be measured on simulator-tool use, calibrated prediction, and pre-feedback judgment, not final score alone.
- Workload analyses should be audited against whether they actually change the submitted design.
- Resource limits work when stated in program-checkable form and enforced by the verifier; feasibility is not design quality.
- Next agents need mechanism discovery that survives workload, constraint, and simulator checks, not only recombination of known policies.
Where Pith is reading between the lines
- The same support ladder could diagnose agents in other slow-to-measure design fields, such as chip floorplanning or network-protocol design.
- Decomposing workload analysis, surrogate modeling, and constraint checking into specialist modules may close the L3 gap faster than scaling one monolith.
- If performance-modeling pass rates remain near 15%, autonomous architecture research will stay gated by human-built oracles for a long time.
- As the suite becomes public, held-out or newly contributed challenges will be needed to keep the capability map free of contamination.
Editorial analysis
A structured set of objections, weighed in public.
Referee Report
Summary. ArchEval proposes a simulator-grounded benchmark and platform for evaluating LLM agents as computer architects. It defines 20 design challenges across CPU, system, memory, accelerator, and CIM domains, backed by eight simulators behind a common connector. Each challenge is run under three support levels—L1 full harness with repeated verifier feedback, L2 simulator-source container without a prepared loop, and L3 agent-only with no runnable feedback—while scoring baseline-normalized performance and recording full trajectories. Evaluating four agent configurations, the paper reports that all agents reach or exceed baselines under L1, but performance collapses without support: only GPT-5.5 + Codex remains above baseline at L3 (1.21× geomean, 65% win rate), with a 15% performance-modeling pass rate. The authors conclude that current agents are useful optimization assistants rather than autonomous architects, and identify missing capabilities in simulator-tool use, calibrated prediction, pre-feedback judgment, and mechanism discovery.
Significance. If the empirical pattern holds, this is a substantial contribution to both computer architecture and agent evaluation. Architecture has long measured artifacts (SPEC, MLPerf, etc.) rather than the designer; ArchEval makes the design process itself measurable under controlled experimental support. The L1/L2/L3 protocol is a clean methodological idea: it holds the task and verifier fixed while removing harness and feedback, separating assisted DSE from tool assembly and pre-feedback judgment. The multi-simulator platform (isolation, typed outcomes, baseline normalization, trajectory logging) is serious systems work and is reusable community infrastructure. Strengths include external, simulator-backed scoring; hard-failure typing; concrete case studies (AllReduce DSE, MNSIM L2 sweep, 256 B metadata budget, ASTRA-sim workload-follow); and an unusually candid limitations section. The paper’s main value is as a capability map and diagnostic platform, not as a final leaderboard.
major comments (4)
- [§5.1, Table 10] §5.1 and Table 10: the central “sharp boundary” claim (all agents ≥ baseline at L1; only GPT-5.5 + Codex above baseline at L3) rests on one run per agent–challenge–setting. With n=1, geomean/win-rate differences cannot be distinguished from run-to-run variance, especially on stochastic agent systems. §8.3 acknowledges this as preliminary, but the abstract and §6 still generalize to “current agents.” At minimum, report multi-seed results for a subset of challenges (or bootstrap/confidence intervals), or reframe all suite-level claims as a single-seed snapshot of specific configurations rather than a general capability map.
- [§5.1, §5.4] §5.1: agent configurations confound model capability with harness infrastructure—GPT-5.5 uses the Codex CLI backend, while the other three use MiniSWE. L2 tool-use analysis (§5.4, Table 12) even excludes GPT-5.5 because its shell/file actions are not recorded in the MiniSWE stream. The L1→L3 collapse and “assistant vs. architect” framing may therefore be harness-specific. Either evaluate at least one shared harness across models, or systematically qualify every cross-agent comparison as configuration-level rather than model-level (the paper sometimes does this, but not consistently in the abstract and findings).
- [§6.1, §6.4] §6.1 (Tables 15–16) and §6.4 (Table 20): workload-grounding, design-following, and novelty labels are produced by Gemma 4 31B, which is itself one of the four evaluated agents. This creates a circularity risk for process claims (an evaluated system judging peers and, in part, itself). Primary verifier scores remain external and non-circular, but Findings 1 and 5 depend on these labels. Use an independent judge model (or human audit on a sample) and report inter-rater agreement; until then, treat those findings as provisional relative signals, as §8.3 already half-suggests.
- [§3.2, Appendix A] §3.2 and Appendix A: baselines are of mixed provenance and strength (LRU, stock bimodal, hand-written references, one published Gibbon design). Beating a weak baseline is not the same as architectural competence. The paper reports win rate and hard failures, which helps, but does not quantify baseline strength (e.g., gap to a known strong human or published design where available). For the L3 “below baseline” narrative especially, a short baseline-strength audit would make the assistant-vs-architect claim more robust.
minor comments (6)
- [Table 5] Table 5 marks ArchEval L1 as lacking workload analysis and performance prediction; this is protocol coverage, not agent inability, but the table can be misread as capability results. Clarify the caption that checkmarks are “exposed by the protocol,” not “demonstrated by agents.”
- [Figure 5, Table 10] Figure 5(c) L3/L1 retained geomean is useful; add absolute hard-failure counts beside win rates in Table 10 so readers can see whether L3 losses are invalid submissions or valid-but-weak designs (partially addressed in §5.5 text).
- [§5.5, Table 13] The performance-modeling pass criterion (Kendall τ ≥ 0.6, executable design-sensitive model, ≥3 measured candidates) is a free parameter. Briefly justify the 0.6 threshold or show sensitivity at nearby cutoffs.
- [§6.4, Table 20] Novelty criterion (“beyond recombining ≤3 known policies”) is reasonable but underspecified for hybrid designs; a short appendix example of borderline cases would help reproducibility of Table 20.
- [§5.1] Several model names (GPT-5.5, Gemini 3.5 Flash, Gemma 4 31B) will date quickly; pin exact API/model identifiers and dates in §5.1 for reproducibility.
- [Appendix C] Appendix trajectory excerpts are valuable; consider moving one fully annotated L1 vs L3 pair into the main body to illustrate the protocol for readers who skip the appendix.
Circularity Check
Main L1–L3 performance claims rest on independent simulator verifiers and baselines; only minor non-load-bearing circularity in using an evaluated agent (Gemma 4 31B) as trajectory judge for auxiliary process labels.
specific steps
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other
[Section 6.1 / Table 15; also Tables 16, 20 and Section 8.3]
"Grounded and Guides design are labeled by Gemma 4 31B. ... In this version, the trajectory rubric uses Gemma 4 31B for semantic questions such as workload grounding, originality, and artifact-rationale consistency, so those judgments should be treated as relative signals that require further calibration."
Process diagnostics that support Findings 1 (workload analyses often ungrounded or unused) and 5 (little genuine mechanism novelty) are produced by Gemma 4 31B, which is itself one of the four agents under evaluation. For that agent the labels are therefore partly self-referential, and the judge may share architectural or training biases with the systems being scored. The paper acknowledges the need for further calibration; the labels remain non-load-bearing because the primary L1/L2/L3 performance numbers and the assistant-vs-architect framing rest on independent simulator verifiers, not on these semantic judgments.
full rationale
ArchEval is an empirical benchmark paper, not a first-principles derivation. Its central claims (all agents ≥ baseline under L1 full harness; only GPT-5.5 + Codex remains above baseline at L3 with 1.21× geomean / 65% win rate and 15% performance-modeling pass rate) are produced by isolated canonical verifier simulators that score submitted artifacts against per-challenge baselines via typed outcomes (SIM_OK, BUILD_FAIL, etc.) and baseline-normalized metrics. Those measurements do not reduce to the paper’s own inputs by construction, nor do they rely on fitted parameters renamed as predictions or on uniqueness theorems imported from the authors. The sole residual circularity is auxiliary: Gemma 4 31B (itself one of the four evaluated agent configurations) supplies the semantic labels for workload grounding, design-following, and novelty that support Findings 1 and 5 and Tables 15–16/20. The paper itself flags these as “relative signals that require further calibration” (Section 8.3). Because the labels are not load-bearing for the headline geomean/win-rate results, the circularity is minor and non-central, corresponding to score 2 rather than 0 or higher.
Axiom & Free-Parameter Ledger
free parameters (3)
- performance-modeling pass threshold (Kendall τ ≥ 0.6 plus executable design-sensitive model and ≥3 measured candidates) =
τ ≥ 0.6
- per-challenge verifier-attempt caps and runtime budgets =
challenge-specific (e.g., 10/1/1 or 5/5/1)
- novelty criterion (beyond recombining ≤3 known policies with parameter tuning) =
≤3 known policies
axioms (4)
- domain assumption Simulator-backed, baseline-normalized metrics are a valid proxy for architecture design quality within each challenge.
- ad hoc to paper Holding the task fixed while removing prepared harness and simulator feedback isolates architect-relevant capabilities (assisted DSE, tool use, pre-feedback judgment).
- domain assumption Lightweight challenges with bounded runtimes still require real architecture decisions rather than toy puzzles.
- domain assumption Complete agent configurations (model + harness) are the right unit of comparison, not base models alone.
invented entities (3)
-
ArchEval L1/L2/L3 evaluation settings
independent evidence
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Architecture-agent capability map (prediction, optimization, generation) with trajectory rubric dimensions
no independent evidence
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Connector-mediated multi-simulator verifier platform
independent evidence
read the original abstract
Computer architecture has long used benchmarks to make progress measurable. LLM agents create a different measurement problem: success is not merely writing code or tuning parameters. The agent must interpret workloads, choose mechanisms, use simulators, predict performance, satisfy hard constraints, and decide which feasible design is worth evaluating. This paper introduces ArchEval, a benchmark and platform for evaluating LLM agents on computer architecture design and optimization. It contains 20 challenges across CPU core mechanisms, system architecture, memory systems, accelerators, and compute-in-memory, backed by eight simulators. Each challenge is posed under three settings: L1 full harness, with repeated simulator feedback; L2 simulator-code container, where simulator source is available but the agent must assemble its own workflow; and L3 agent-only, with no runnable feedback before submission. Each run reports baseline-normalized verifier performance and records the full trajectory, connecting results to workload analysis, simulator-tool use, prediction, constraint handling, and artifact integrity. Initial results show a sharp boundary in current agents. With L1 support, all four evaluated agents reach or exceed baseline and improve real designs across diverse simulators. Removing support exposes weaknesses: many agents fail to turn simulator source into useful experiments, and L3 predictions often disagree with verifier results. In L3, only GPT-5.5 + Codex remains above baseline, reaching 1.21x geomean performance and a 65% win rate; the other three fall below baseline. Even GPT-5.5 + Codex has only a 15% performance-modeling pass rate. ArchEval frames today's agents as useful optimization assistants rather than autonomous architects, and identifies capabilities needed next: simulator-tool use, calibrated prediction, pre-feedback judgment, and useful mechanism discovery.
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Pith/arXiv arXiv 2021
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Marilyn Zhang, Tianfeng Chen, Fabián Barzuna, Ankita Rathod, and Mark E. Whiting. 2026. LEAP: Trajectory-Level Evaluation of LLMs in Iterative Scientific Design. arXiv:2605.15341 [cs.LG] https://arxiv.org/abs/2605.15341
Pith/arXiv arXiv 2026
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[56]
Zhenhua Zhu, Hanbo Sun, Tongxin Xie, Yu Zhu, Guohao Dai, Lixue Xia, Dimin Niu, Xiaoming Chen, Xiaobo Sharon Hu, Yu Cao, et al . 2023. Mnsim 2.0: A behavior-level modeling tool for processing-in-memory architectures.IEEE transactions on computer-aided design of integrated circuits and systems42, 11 (2023), 4112–4125. Appendix A The Challenge Suite Section ...
2023
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[57]
Workload:3 SPEC CPU2017 traces [6] (perlbench, gcc, xalancbmk); 3M-instr warmup + 7M-instr measure
Branch Direction Predictorbranch_predictor(CPU core, ChampSim) Objective:Implement thecandidatetaken/not-taken predictor class (BTB and pipeline fixed) to minimize average MPKI, following classic branch-prediction design practice [29]. Workload:3 SPEC CPU2017 traces [6] (perlbench, gcc, xalancbmk); 3M-instr warmup + 7M-instr measure. Metric:MPKI ↓ vs stoc...
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[58]
Workload:3 SPEC CPU2017 traces (perlbench, gcc, xalancbmk); 3M + 7M instr
Branch Target Bufferbtb(CPU core, ChampSim) Objective:Design thecandidateBTB minimizing 3-trace average MPKI under a tight metadata budget. Workload:3 SPEC CPU2017 traces (perlbench, gcc, xalancbmk); 3M + 7M instr. Metric:MPKI ↓ vs stock basic_btb.Constraint: ≤16 KB metadata; code ≤1500 lines. Deliverables:candidate.{h,cc}; three design docs; pytest surro...
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[59]
Workload:6 SPEC CPU2017 traces (sphinx3, mcf×2, omnetpp,
Cache Replacement Policycache_replacement(CPU core, ChampSim) Objective:Design an LLC replacement policy maximizing cycle-weighted IPC (geomean speedup) over six workloads. Workload:6 SPEC CPU2017 traces (sphinx3, mcf×2, omnetpp,. . .); 3M + 7M instr. Metric:IPC↑vs LRU.Constraint:≤256 B total replacement-policy metadata across the whole LLC; code≤1000 lin...
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[60]
Workload:3 memory-intensive SPEC traces (mcf, libquantum, mcf); 3M + 7M instr
L1D Prefetcherl1d_prefetcher(CPU core, ChampSim) Objective:Design the candidate L1D prefetcher maximizing average IPC on memory-intensive traces. Workload:3 memory-intensive SPEC traces (mcf, libquantum, mcf); 3M + 7M instr. Metric:IPC↑vs next-line L1D prefetcher.Constraint:no storage cap; code≤1500 lines. Deliverables:candidate.{h,cc}; three design docs;...
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[61]
Workload:3 SPEC CPU2017 traces (perlbench, gcc, xalancbmk); 3M + 7M instr
Front-End Co-Design: BP + BTBcompose_bp_btb(CPU core, ChampSim) Objective:Co-design a branch predictor and a BTB that jointly minimize average MPKI under a shared storage budget. Workload:3 SPEC CPU2017 traces (perlbench, gcc, xalancbmk); 3M + 7M instr. Metric:MPKI ↓ vs reference BP+BTB.Constraint:joint ≤32 KB storage; code≤2500 lines. Deliverables:candid...
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[62]
Workload:3 SPEC CPU2017 traces (mcf×2, omnetpp); 3M + 7M instr
LLC Co-Design: Replacement + Prefetcher compose_replacement_prefetcher(CPU core, ChampSim) Objective:Co-design the LLC replacement policy and LLC prefetcher under a single shared storage budget to maximize IPC. Workload:3 SPEC CPU2017 traces (mcf×2, omnetpp); 3M + 7M instr. Metric:IPC ↑ vs reference repl.+pf..Constraint:shared ≤64 KB storage; code≤2000 li...
2000
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[63]
Workload:Single-CPU gem5 SE-mode workload
Cache Hierarchy + Prefetchergem5_cache(System, gem5) Objective:Design the full on-die cache subsystem (L1I/L1D, optional L2/LLC) plus prefetcher for a single-CPU SE-mode system as a config.py. Workload:Single-CPU gem5 SE-mode workload. Metric:IPC ↑ vs reference config.Constraint:on-die cache area budget; code≤400 lines. Deliverables:config.py; workload/pr...
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[64]
Workload:Fixed DDR4 access trace
DDR4 Memory Controller Tuningdramsys_ddr4(Memory, DRAMSys) Objective:Design a DDR4 controller configuration maximizing sustained read+write bandwidth, subject to a latency deadline. Workload:Fixed DDR4 access trace. Metric:GB/s↑vs reference config.Constraint:latency deadline; code ≤200 lines. Deliverables:config.json, mc_config.json; three design docs. Ve...
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[65]
Workload:Fixed memory access trace
RowHammer Mitigation Overheadramulator_rowhammer (Memory, Ramulator 2.0) Objective:Pick and tune a RowHammer mitigation [20] for least performance overhead while staying provably secure at a fixed threshold. Workload:Fixed memory access trace. Metric:overhead %↓vs reference mitigation.Constraint:provably secure at𝑇 RH=100; code≤120 lines. Deliverables:con...
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[66]
Workload:All-Reduce, 8 NPUs, fixed topology + workload
Collective: All-Reduceastrasim_collective(System, ASTRA-sim) Objective:Configure ASTRA-sim’s System layer (collective algorithm + parameters) to minimize completion time on fixed hardware, following collective-communication optimization practice [42]. Workload:All-Reduce, 8 NPUs, fixed topology + workload. Metric:cycles↓vs reference algorithm+config.Const...
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[67]
Workload:All-Gather, 8 NPUs, fixed topology + workload
Collective: All-Gatherastrasim_allgather(System, ASTRA-sim) Objective:Configure the System layer to minimize All-Gather completion time on fixed hardware [42]. Workload:All-Gather, 8 NPUs, fixed topology + workload. Metric:cycles↓vs reference algorithm+config.Constraint:8 NPUs, fixed topology; code≤60 lines. Deliverables:system.json; three design docs. Ve...
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[68]
Workload:All-to-All, 8 NPUs, fixed topology + workload
Collective: All-to-All (8 NPUs) astrasim_alltoall (System, ASTRA-sim) Objective:Configure the System layer to minimize All-to-All completion time on fixed hardware [42]. Workload:All-to-All, 8 NPUs, fixed topology + workload. Metric:cycles↓vs reference algorithm+config.Constraint:8 NPUs, fixed topology; code≤60 lines. Deliverables:system.json; three desig...
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[69]
Workload:All-to-All, 16 NPUs, fixed topology + workload
Collective: All-to-All (16 NPUs)astrasim_alltoall_16 (System, ASTRA-sim) Objective:Configure the System layer to minimize All-to-All completion time at larger scale [42]. Workload:All-to-All, 16 NPUs, fixed topology + workload. Metric:cycles↓vs reference algorithm+config.Constraint:16 NPUs, fixed topology; code≤60 lines. Deliverables:system.json; three de...
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[70]
Workload:Reduce-Scatter, 8 NPUs, fixed topology + workload
Collective: Reduce-Scatterastrasim_reducescatter (System, ASTRA-sim) Objective:Configure the System layer to minimize Reduce-Scatter completion time on fixed hardware [42]. Workload:Reduce-Scatter, 8 NPUs, fixed topology + workload. Metric:cycles↓vs reference algorithm+config.Constraint:8 NPUs, fixed topology; code≤60 lines. Deliverables:system.json; thre...
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[71]
Workload:ViT-Base [8] (14 layers); 4 cores, each 128×128 PE array, 256 KB SRAMs, BW=10
Multi-Core Partitioning (128 ×128) scalesim_mc (Accelerator, SCALE-Sim v3) Objective:Design a per-layer partitioning policy for a 4-core systolic-array accelerator running ViT-Base [8]. Workload:ViT-Base [8] (14 layers); 4 cores, each 128×128 PE array, 256 KB SRAMs, BW=10. Metric:cycles↓vs reference schedule.Constraint:fixed 4×128×128 hardware; code≤2000 ...
2000
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[72]
Workload:ViT-Base [8] (14 layers); 4 cores, each 256×256 PE array, 256 KB SRAMs, BW=10
Multi-Core Partitioning (256×256)scalesim_256array (Accelerator, SCALE-Sim v3) Objective:Design a per-layer partitioning policy for a 4-core accelerator with larger arrays. Workload:ViT-Base [8] (14 layers); 4 cores, each 256×256 PE array, 256 KB SRAMs, BW=10. Metric:cycles↓vs reference schedule.Constraint:fixed 4×256×256 hardware; code≤2000 lines. Delive...
2000
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[73]
Workload:ViT-Base [8] (14 layers); 4 cores, each 64×64 PE array, 256 KB SRAMs, BW=10
Multi-Core Partitioning (64×64)scalesim_64array (Accelerator, SCALE-Sim v3) Objective:Design a per-layer partitioning policy for a 4-core accelerator with smaller arrays. Workload:ViT-Base [8] (14 layers); 4 cores, each 64×64 PE array, 256 KB SRAMs, BW=10. Metric:cycles↓vs reference schedule.Constraint:fixed 4×64×64 hardware; code≤2000 lines. Deliverables...
2000
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[74]
Workload:ResNet-50 [15] (24 unique layers) on one fixed DNN accelerator
Per-Layer Mapping (DOSA [ 16]) timeloop_dosa (Accelerator, Timeloop+Accelergy) Objective:Choose the Timeloop mapping (loop order, tiling, spatial parallelism) for every ResNet-50 layer [15], minimizing geomean EDP. Workload:ResNet-50 [15] (24 unique layers) on one fixed DNN accelerator. Metric:geomean EDP↓vs reference mapping.Constraint:fixed Gemmini-styl...
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[75]
Workload:MNSIM ReRAM CIM design point
ReRAM CIM Design Searchmnsim_pim(CIM, MNSIM 2.0) Objective:Search MNSIM’s device / crossbar / interface knobs for one ReRAM CIM accelerator (SimConfig.ini) minimizing EDP under an area cap. Workload:MNSIM ReRAM CIM design point. Metric:EDP↓vs reference design.Constraint:area cap; code≤2000 lines. Deliverables:SimConfig.ini; design_analysis, principles, ev...
2000
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[76]
We have successfully designed
NN + CIM Co-Design (Gibbon)gibbon_codesign(CIM, MNSIM 2.0) Objective:Co-design the network and the ReRAM-CIM accelerator (design.json) minimizing EDP while meeting an accuracy floor and area cap. Workload:CIFAR-10 [25] network + ReRAM-CIM accelerator. Metric:EDP↓vs Gibbon (published).Constraint:CIFAR-10 [25] accuracy floor 0.738, area cap; code≤2000 lines...
2000
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has_member
Validate the storage budget. 4. Submit and evaluate. 5. Iterate based on results.↩→ [...] Budget check for Gshare: Table: 2^14 entries * 2 bits = 4096 bytes. [...]↩→ 2^16 entries * 2 bits = 16384 bytes. (Exactly the budget). [...] The first submission (Gshare with 15-bit GHR) yielded an average MPKI of 6.37.↩→ Per-trace MPKI: 600.perlbench 2.523, 602.gcc ...
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