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TuRTLe: A Unified Evaluation of LLMs for RTL Generation

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arxiv 2504.01986 v2 pith:MGOQKWOP submitted 2025-03-31 cs.AR cs.AI

classification cs.ARcs.AI
keywords llmsevaluationtasksgenerationmodelsturtleacrossbenchmarks
verification ladder T0 review T1 audit T2 compute T3 formal
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The rapid advancements in LLMs have driven the adoption of generative AI in various domains, including Electronic Design Automation (EDA). Unlike traditional software development, EDA presents unique challenges, as generated RTL code must not only be syntactically correct and functionally accurate but also synthesizable by hardware generators while meeting performance, power, and area constraints. These additional requirements introduce complexities that existing code-generation benchmarks often fail to capture, limiting their effectiveness in evaluating LLMs for RTL generation. To address this gap, we propose TuRTLe, a unified evaluation framework designed to systematically assess LLMs across key RTL generation tasks. TuRTLe integrates multiple existing benchmarks and automates the evaluation process, enabling a comprehensive assessment of LLM performance in syntax correctness, functional correctness, synthesis, PPA optimization, and exact line completion. Using this framework, we benchmark a diverse set of open LLMs and analyze their strengths and weaknesses in EDA-specific tasks. Our results show that reasoning-based models, such as DeepSeek R1, consistently outperform others across multiple evaluation criteria, but at the cost of increased computational overhead and inference latency. Additionally, base models are better suited in module completion tasks, while instruct-tuned models perform better in specification-to-RTL tasks.

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Reviewed papers in the Pith corpus that reference this work. Sorted by Pith novelty score. Full citation record

  1. ProtocolLLM: RTL Benchmark for SystemVerilog Generation of Communication Protocols

    cs.AR 2025-06 conditional novelty 6.0 of 10

    A new benchmark, ProtocolLLM, evaluates LLM-generated SystemVerilog for SPI, I2C, UART, and AXI and finds most models fail timing-accurate functional checks.

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