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REVIEW 3 major objections 5 minor 16 references

Custom 11- and 12-bit floating-point formats for FFT cores in optical OFDM transceivers preserve bit-error-rate performance close to a 32-bit floating-point reference while reducing core power by up to 19.8% and area by up to 12.0% compared

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Custom 11-12 bit floating-point FFT cores in a 128 Gbit/s optical OFDM transceiver match 16-bit fixed-point accuracy at lower power and area for moderate QAM orders, with degradation at 4096-QAM.

T0 review reviewed 2026-08-01 challenge →

load-bearing objection Useful engineering result with real PPA savings; the accuracy headline overstates what Table II shows at high QAM. the 3 major comments →

arxiv 2607.17835 v1 pith:MLOW4X4C submitted 2026-07-20 cs.AR

New Number Formats for FFT IP Cores in Optical OFDM Transceivers

Lukas Krupp , Gustavo Magalh\~aes Gomes De Souza , Sani Nassif , Norbert Wehn This is my paper
classification cs.AR
keywords low-precision arithmeticcustom floating-point formatsFFToptical OFDMcross-layer co-designbit error ratepower-area trade-offnumber format fitting
verification ladder T0 review T1 audit T2 compute T3 formal T4 reserved

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

The paper asks whether the reduced-precision floating-point formats that proved so effective in machine-learning accelerators can also benefit classical DSP workhorses like the FFT. Its answer, from a 256-point FFT in a 128 Gbit/s optical OFDM transceiver, is yes: custom floating-point formats with 11 or 12 total bits, fit to the signal distributions seen inside the FFT, keep bit-error-rate curves almost indistinguishable from a 32-bit floating-point reference while beating fixed-point designs on power and area. This matters because FFT kernels dominate the cost of next-generation optical interconnects, so a format that is both numerically robust and cheaper to build could directly improve energy-per-bit. The paper frames the result as a cross-layer co-design methodology: choose number formats from measured value distributions, instantiate simplified arithmetic units, and validate at system level via BER.

Core claim

The central claim is that fitted custom floating-point formats with one sign bit, four exponent bits, and six or seven mantissa bits (FP11/FP12 with bias 8) can replace fixed-point arithmetic inside an FFT/IFFT pair without sacrificing communication performance. Across QAM orders 64 through 4096, FP12 tracks the FP32 reference with mean excess log10(BER) below 0.14 and worst case below 1.0, while INT16, the most accurate fixed-point variant, degrades more steeply at higher orders. The hardware payoff is structural: FP11 cuts FFT core power by 19.8% and area by 12.0% relative to INT16, and FP12 cuts power by 17.1% and area by 7.4%, with both on the Pareto-optimal frontier for accuracy versus

What carries the argument

The central object is a custom reduced-precision floating-point format, denoted FP⟨1+b_e+b_m⟩ with E⟨b_e⟩M⟨b_m⟩B⟨B⟩, where the exponent width, mantissa width, and bias are tunable and fit to the empirical value distribution at each node of an FFT represented as a directed acyclic graph. The iterative fitting sweeps these parameters against tail statistics of the distributions; the paper finds that b_e=4 and bias B=8 cover the FFT's internal dynamic range, leaving the remaining bits for mantissa precision. This fitted format is then instantiated in a radix-2^2 single-path delay feedback pipeline, synthesized and placed-and-routed in a 12 nm FinFET technology, and evaluated with a logarithmic

Load-bearing premise

The number format is fitted to the value distribution of the FFT under representative inputs at a single operating point (M=256), so if real-world channel impairments, scaling, or clipping shift the internal dynamic range, the fixed exponent range could overflow or underflow and the claimed BER and hardware advantages would not generalize.

What would settle it

Run the same FFT core with a different channel model (e.g., fiber nonlinearities or strong clipping) or a different FFT size, and check whether the intermediate values in any butterfly stage exceed the representable range of the E4M8 format; alternatively, sweep QAM orders beyond 4096 and observe whether FP12's BER floor diverges from the FP32 reference as constellation density tightens.

Watch this falsifier. Get emailed when new claim-graph text bears on it.

If this is right

  • Reduced-precision floating-point can be a drop-in replacement for fixed-point in the FFT block of optical OFDM transceivers, delivering better accuracy per milliwatt and per square-micron than conventional fixed-point when the format is fit to the application.
  • The exponent width and bias determined at one operating point (M=256) prove sufficient across a wide range of QAM orders, so one global format can serve multiple modulation targets without re-fitting.
  • FP12 offers near-FP32 BER behavior up to 4096-QAM with a 17.1% power reduction, meaning high-order constellations do not force a return to full-precision arithmetic.
  • Because the fitting method is tied to value distributions rather than to a specific kernel, the same cross-layer flow can be applied to other DSP blocks such as channel equalizers and filters, which the paper lists as future work.
  • Per-stage bit-width assignment, explicitly left for future work, is likely to yield further savings since FFT dynamic range grows across pipeline stages.

Where Pith is reading between the lines

These are editorial extensions of the paper, not claims the author makes directly.

  • A natural extension would be per-stage format fitting: the paper notes the global format uses the same width throughout the pipeline, and since dynamic range grows stage by stage, assigning a narrower exponent or mantissa early on and wider later could extract additional power savings beyond the reported 19.8%.
  • The fitting point M=256 may be conservative for lower-order constellations; the paper itself observes that re-fitting for higher QAM orders would shrink the BER gap for 1024/4096-QAM, so the method has headroom to improve worst-case accuracy at negligible hardware cost.
  • The same value-distribution fitting approach could reveal whether reduced-precision floating-point also benefits other transforms or DSP kernels where internal ranges grow super-linearly, such as large radix FFTs or iterative equalizers, but the BER sensitivity of those blocks would need separate validation.
  • The reported power and area figures come from a single SDF-FFT lane at 500 MHz; in a full transceiver with parallel lanes, the relative savings would likely persist, but the absolute power budget would scale with lane count and operating rate.
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Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit.

Referee Report

3 major / 5 minor

Summary. The paper proposes a cross-layer co-design methodology that fits custom reduced-precision floating-point formats to empirical value distributions of an FFT DAG embedded in a coherent optical OFDM transceiver. The authors implement a 256-point SDF radix-2^2 FFT in a 12nm FinFET technology, compare FP10/FP11/FP12 and INT13-INT16 variants via post-layout power/area and system-level BER, and claim that 11- and 12-bit custom formats preserve BER close to an FP32 reference while reducing power by up to 19.8% and area by up to 12.0% relative to fixed-point designs. The paper includes a concrete PPA table, BER curves for 64-4096 QAM, and acknowledges that formats were fitted at M=256 as the operating point.

Significance. If the claims were fully supported, the paper would provide a useful design methodology and a valuable data point for replacing fixed-point arithmetic with reduced-precision floating-point in a classical DSP kernel. The strengths are the concrete post-layout PPA analysis in 12nm FinFET, the explicit value-distribution-based fitting procedure, and the honest acknowledgement of several limitations (global per-pipeline assignment, M=256 fitting point). However, the central accuracy claim is materially overstated by the paper's own Table II, and the validation protocol is in-sample with respect to the fitting simulation. These issues affect the load-bearing conclusion that reduced-precision floating-point 'preserves BER close to FP32 across multiple modulation orders.' With revised claims and additional validation, the contribution is relevant to the DSP and OFDM hardware communities.

major comments (3)
  1. [Abstract, §V.B, Table II] The headline claim that FP11/FP12 'preserve BER performance close to a 32-bit floating-point reference across multiple modulation orders' is contradicted by Table II at high QAM. At M=4096, FP11 has mean excess log10(BER) 0.3141 and max 1.8921; FP12 has mean 0.1348 and max 1.0000. A maximum excess of one to two orders of magnitude in BER is not 'close to FP32' under any reasonable BER budget, especially for 4096-QAM. Even at M=64, FP11 shows Delta_max=0.7792. The admission in §V.B that the formats were fitted with M=256 and that re-fitting for higher QAM would reduce the gap is not a minor caveat; it directly limits the accuracy claim. Please rephrase the abstract/conclusion to state the claim as 'comparable to INT16 at selected operating points' or provide per-modulation BER budgets with a target threshold.
  2. [§III.A, §IV.A, §V.B] The number-format fitting and the BER validation are performed on the same simulation. The exponent width and bias are fitted to empirical value distributions from the M=256 optical OFDM case, and the same M=256 case is then included in the BER validation; no held-out data or sensitivity analysis is presented. Moreover, the channel model is AWGN only (Table I), so the effect of realistic optical channel impairments (CD, PMD, Kerr nonlinearity) that change input distributions and per-stage dynamic ranges is untested. Therefore, the 'across multiple modulation orders' claim is a selected design point rather than an out-of-sample prediction. The authors should either split the data into fitting/validation sets, perturb input scaling or channel conditions, or explicitly reframe the results as a method demonstration without generalizing beyond AWGN.
  3. [§V.B, Fig. 4] The Pareto-front analysis uses mean excess log10(BER) as the accuracy metric, but the abstract's 'preserve BER' claim depends on worst-case behavior. At 4096-QAM, FP12 has Delta_max=1.0000 while INT16 has Delta_max=0.9983, so the two are comparable in the worst case, but at 64-QAM FP12's Delta_max=0.2632 is worse than INT16's 0.0969. Reporting only the mean in the multi-objective plots obscures these differences. Please plot or tabulate Delta_max as an additional objective, or justify why the mean is the appropriate metric for communication systems with BER floors.
minor comments (5)
  1. [Fig. 3] The y-axis is labeled 'log10(BER)' with values from 3.5 down to 0.0. Since BER is a probability, log10(BER) should be negative; the axis appears to show -log10(BER) or is otherwise mislabeled. Please correct the axis label and the direction of the curves.
  2. [§V.A] The paper states that the required dynamic range fits within b_e=4 and B=8, but no quantitative details of the fitted distributions (percentiles, max absolute values, per-stage ranges) are given. Adding a small table or figure would make the fitting step reproducible and would help readers assess sensitivity.
  3. [§IV.B] The fixed-point description says that b_i is fitted so that changing W only changes fractional precision, but the fitting criterion for b_i is not specified. A sentence describing how b_i is chosen (e.g., overflow probability) would remove ambiguity.
  4. [Abstract, Table II] The power/area savings 'up to 19.8% and 12.0%' are relative to INT16. Please make this explicit in the abstract, since savings versus INT14/INT15 are smaller and the comparison baseline is the largest fixed-point design.
  5. [Conclusion] The conclusion restates the abstract's 'close to FP32' wording without the caveats from §V.B. The conclusion should be harmonized with the revised, more cautious accuracy claim.

Circularity Check

0 steps flagged

No circular derivation: the formats are fitted to value distributions as a design choice, and the BER/PPA evaluations are independent measurements; the main weakness is an overstated accuracy claim, not circularity.

full rationale

The paper's derivation chain is not circular. The custom floating-point formats are produced by a distribution-based fitting procedure (Sec. III.A and III.B) that uses intermediate FFT value distributions from the OFDM transceiver model; the BER validation (Sec. V.A, Eq. 2, Table II) is a separate system-level measurement, not an algebraic consequence of the fit. Fitting the exponent width and bias (be=4, B=8) to dynamic-range statistics does not by construction force the reported BER outcomes. The mantissa width selection (FP10/FP11/FP12) is a design-space choice informed by the BER sweeps in Fig. 3, so statements such as "FP12 consistently tracks the FP32 reference" describe a selected operating point rather than an out-of-sample prediction; this is standard design-space exploration, not a fitted parameter renamed as a prediction. No self-citation is load-bearing: the references are external prior works, and the PPA results come from post-layout synthesis in 12 nm FinFET, which is independent evidence. The paper's own Sec. V.B even admits the formats were fitted with M=256 as the operating point and that re-fitting for higher QAM would reduce the gap. Table II shows FP11 and FP12 have mean/max excess log10(BER) up to 0.314/1.892 and 0.135/1.000 at 4096-QAM, which contradicts the abstract's "close to FP32" across multiple modulation orders. That is a correctness/consistency issue, not circularity. Therefore the circularity score is 0.

Axiom & Free-Parameter Ledger

5 free parameters · 5 axioms · 0 invented entities

The central comparison rests on the fitted FP format parameters (b_e, B) and on the assumed representativeness of the QAM input distribution. The PPA numbers are independent hardware measurements, but the accuracy claim is in-sample with respect to the format-fitting loop. No new physical entities are introduced.

free parameters (5)
  • Exponent bit width b_e = 4
    Fitted to empirical dynamic range of FFT internal nodes (Sec. III-B/V).
  • Exponent bias B = 8
    Fitted with b_e to center the representable range on observed values.
  • Mantissa bit width b_m = 5, 6, 7 (FP10/FP11/FP12)
    Selected via BER design-space sweep; final candidates FP11/FP12 use 6/7.
  • Fixed-point integer bit width b_i = not reported
    Fitted to input distribution so that changing W only changes fractional bits (Sec. IV-B).
  • Fixed-point stage-wise scaling factor = 1/2
    Division by two after each butterfly stage to control dynamic range (Sec. IV-B); a design choice for the fixed-point baseline.
axioms (5)
  • standard math FFT radix-2^2 SDF pipeline correctly implements the DFT
    Standard architectural baseline (Ref. 15); no proof supplied, but accepted background.
  • domain assumption AWGN channel with pilot-based channel estimation and single-tap ZF equalization adequately represents optical OFDM for format comparison
    Used in Sec. IV-A; real fiber impairments (dispersion, nonlinearity) are not modeled.
  • domain assumption Representative QAM input distributions propagated through the DAG capture the FFT's worst-case dynamic range
    Sec. III-A/B; the fitted b_e=4, B=8 depends on this.
  • domain assumption FP32 FFT is a numerically exact reference for BER comparison
    Sec. IV-C; FP32 itself has rounding error, but it is treated as the target.
  • ad hoc to paper Global per-format assignment across all FFT pipeline stages is sufficient; per-stage bit-width assignment is not considered
    Sec. IV-B: 'The per-stage bit width assignment is not yet considered.' This simplifies the study and could understate the benefit or cost of FP formats.

reviewed 2026-08-01 · how reviews work

0 comments
Cite this review

Pith. "Pith review of New Number Formats for FFT IP Cores in Optical OFDM Transceivers." pith.science (2026). https://pith.science/paper/MLOW4X4C

@misc{pith2026260717835,
  author       = {Pith},
  title        = {Pith review of: New Number Formats for FFT IP Cores in Optical OFDM Transceivers},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/MLOW4X4C}},
  note         = {Machine review of arXiv:2607.17835}
}
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read the original abstract

Many state-of-the-art DSP implementations use fixed-point arithmetic due to its reduced hardware complexity and high throughput compared to conventional floating-point arithmetic. In contrast, machine learning accelerators exhibit substantial gains from reduced-precision floating-point formats, enabling improvements in energy efficiency and peak throughput. These advances motivate a re-evaluation of numerical representations for classical DSP workloads. A central question is whether reduced-precision floating-point formats can achieve competitive power, performance, and area compared to fixed-point implementations, while providing advantages in dynamic range and numerical robustness. This paper presents a new cross-layer co-design methodology for DSP kernels that jointly optimizes numerical representations, arithmetic units, and application-level performance. As a case study, we focus on the FFT, a fundamental DSP block across many applications. The FFT is evaluated within optical OFDM transceivers, where it dominates power consumption and silicon area as FFT size and modulation order scale to support data rates beyond 100 Gbit/s. We compare fixed-point and reduced-precision floating-point formats using post-layout power and area results in a 12nm FinFET technology and demonstrate system-level performance in terms of BER versus Eb/N0. For a 256-point FFT engine in a 128 Gbit/s transceiver, we show that 11- and 12-bit custom floating-point formats preserve BER performance close to a 32-bit floating-point reference across multiple modulation orders, while reducing FFT core power by up to 19.8% and area by up to 12.0% compared to representative fixed-point designs. To the best of our knowledge, this is the first investigation of custom reduced-precision floating-point arithmetic for FFT cores in optical OFDM transceivers.

Figures

Figures reproduced from arXiv: 2607.17835 by Gustavo Magalh\~aes Gomes De Souza, Lukas Krupp, Norbert Wehn, Sani Nassif.

Figure 1
Figure 1. Figure 1: Optical OFDM transceiver employing M-QAM mod￾ulation with N parallel data channels [PITH_FULL_IMAGE:figures/full_fig_p002_1.png] view at source ↗
Figure 2
Figure 2. Figure 2: Cross-layer co-design methodology for number formats in digital signal processing systems. [PITH_FULL_IMAGE:figures/full_fig_p003_2.png] view at source ↗
Figure 3
Figure 3. Figure 3: BER versus Eb/N0 for increasing QAM modulation orders comparing FP32, reduced-precision floating-point, and fixed-point FFT/IFFT implementations. B. Hardware Results and Trade-Off Table II reports post-P&R power and area for the fixed-point and floating-point FFT cores implemented in a 12 nm FinFET technology. In addition, the table includes the application￾level accuracy metrics introduced in Section IV-C… view at source ↗
Figure 4
Figure 4. Figure 4: Joint multi-objective visualization of arithmetic design points for the FFT core. Marker size represents total bit width. [PITH_FULL_IMAGE:figures/full_fig_p006_4.png] view at source ↗

discussion (0)

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Reference graph

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This paper was first reviewed by deepseek-v4-flash on August 1, 2026.