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arxiv: 2606.11541 · v1 · pith:MLXJVMEYnew · submitted 2026-06-10 · 💻 cs.CR

WHET: Welding Homomorphic Encryption to Accelerator Architectures

Jongmin Kim , Hyesung Ji , Wonseok Choi , Hyunah Yu , Jung Ho Ahn This is my paper

Pith reviewed 2026-06-27 09:43 UTC · model grok-4.3

classification 💻 cs.CR
keywords fully homomorphic encryptionFHE acceleratorCKKS bootstrappingmemory optimizationciphertext compressioncoefficient-to-slot mappingarchitecture-aware design
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The pith

WHET applies memory-centric transformations to shrink FHE working sets and deliver 1.38-8.74x per-area speedups plus sub-millisecond CKKS bootstrapping.

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

WHET shows that standard fully homomorphic encryption constructions generate large temporary ciphertexts and heavy off-chip traffic that limit accelerator throughput. It introduces accelerator-aware changes including fine-grained coefficient-to-slot mapping, plaintext compression, and intermediate modulus raising to cut on-chip data movement while keeping the schemes correct and secure. These reductions then allow simple hardware additions such as a dedicated buffer to improve memory efficiency further. The combined changes produce the reported performance gains and the first sub-millisecond bootstrapping latency for CKKS.

Core claim

WHET identifies conventional FHE constructions as the main sources of excessive working sets and off-chip memory traffic in accelerators. It proposes three accelerator-specific techniques—fine-grained coefficient-to-slot transformation, plaintext compression, and intermediate modulus raising—to minimize temporary ciphertexts and plaintext loads. These software changes create opportunities for lightweight hardware refinements, including a special-purpose buffer and functional-unit extensions, that together yield 1.38-8.74× per-area performance improvements over prior FHE accelerators and enable the first sub-millisecond CKKS bootstrapping.

What carries the argument

Memory-footprint reductions through coefficient-to-slot transformation, plaintext compression, and intermediate modulus raising, paired with a special-purpose on-chip buffer.

If this is right

  • Per-area throughput rises between 1.38× and 8.74× compared with existing FHE accelerators.
  • CKKS bootstrapping latency drops below one millisecond for the first time.
  • Temporary ciphertext and plaintext loads decrease enough to keep more data on-chip.
  • Specialized buffers and functional units become effective once the software data footprint shrinks.

Where Pith is reading between the lines

These are editorial extensions of the paper, not claims the author makes directly.

  • The same memory-reduction pattern could be tested on other lattice-based schemes beyond CKKS.
  • Future accelerator designs might allocate more area to buffers sized for compressed ciphertexts.
  • Co-design of crypto primitives with hardware could be applied to other privacy mechanisms such as secure multi-party computation.
  • Sub-millisecond bootstrapping may open encrypted workloads that require frequent noise refresh, such as real-time private inference.

Load-bearing premise

Conventional FHE schemes are the dominant cause of large working sets and memory traffic, and the listed transformations keep correctness and security intact when mapped to accelerators.

What would settle it

An experiment that applies the three transformations to a standard CKKS accelerator and measures either increased total on-chip data volume or a security break would falsify the central claim.

Figures

Figures reproduced from arXiv: 2606.11541 by Hyesung Ji, Hyunah Yu, Jongmin Kim, Jung Ho Ahn, Wonseok Choi.

Figure 1
Figure 1. Figure 1: (a) KS computational cost breakdown and (b) data size by level. Computational costs are weighted sums of in￾teger multiplication and modular reduction counts [1]. A random seed replaces half of an evk [85]. Higher levels are reserved for CtS, EvalMod, and StC, which comprise Boot. expensive for practical use. For instance, convolutional neural net￾work (CNN) inference that takes a fraction of a second on C… view at source ↗
Figure 2
Figure 2. Figure 2: CtS/StC matrix decomposition [39] and plaintext compression simplified for 𝑁 = 32. The original dense CtS/StC matrix, composed of powers of 𝜁 = 𝑒 𝜋𝑖/𝑁 , is decomposed into two sparse matrices with reduced #diag (16 → 4 & 7). Empty slots in each matrix represent zero values. The rightmost matrix contains diagonals with repetitions, allowing plaintext compression. [⟨u≪2⟩]. Thus, Min-KS enables evaluating the… view at source ↗
Figure 3
Figure 3. Figure 3: Boot modulus change across ModRaise methods. compression of its corresponding plaintext. As shown in [PITH_FULL_IMAGE:figures/full_fig_p006_3.png] view at source ↗
Figure 4
Figure 4. Figure 4: Applying WHET to an accelerator with eight clus [PITH_FULL_IMAGE:figures/full_fig_p007_4.png] view at source ↗
Figure 5
Figure 5. Figure 5: Breakdown of the NTTU idle cycles during [PITH_FULL_IMAGE:figures/full_fig_p007_5.png] view at source ↗
Figure 6
Figure 6. Figure 6: (Left) Delay, energy, energy-delay product (EDP), [PITH_FULL_IMAGE:figures/full_fig_p009_6.png] view at source ↗
Figure 7
Figure 7. Figure 7: Execution time, energy consumption, and energy-delay product (EDP) of (a) [PITH_FULL_IMAGE:figures/full_fig_p010_7.png] view at source ↗
Figure 8
Figure 8. Figure 8: Execution time, energy, and energy-delay product (EDP) under varying (a) cluster count (total on-chip memory [PITH_FULL_IMAGE:figures/full_fig_p010_8.png] view at source ↗
read the original abstract

Fully homomorphic encryption (FHE) enables computations on encrypted data without decryption, offering strong data privacy at the expense of substantial computational and memory overheads. Prior efforts have steadily improved FHE performance through cryptographic and algorithmic enhancements or hardware acceleration, yet these two directions have progressed largely in isolation, hindering the full exploitation of available hardware capabilities. This work presents WHET, which introduces memory-centric, architecture-aware optimizations to better align cryptographic and algorithmic constructions with FHE accelerator architectures. We identify conventional FHE constructions as major sources of excessive working sets and heavy off-chip memory traffic. We propose accelerator-specific techniques, including fine-grained coefficient-to-slot transformation, plaintext compression, and intermediate modulus raising, to reduce the on-chip data footprint by minimizing temporary ciphertexts and plaintext loads. With these techniques applied, we observe additional opportunities to improve on-chip memory efficiency; hence, we introduce lightweight architectural refinements, including a special-purpose buffer and functional unit extensions. With these optimizations, WHET achieves 1.38-8.74$\times$ per-area performance improvements over state-of-the-art FHE accelerators and the first-ever sub-millisecond CKKS bootstrapping.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit. Tearing a paper down is the easy half of reading it; the pith above is the substance, this is the friction.

Referee Report

1 major / 2 minor

Summary. The paper presents WHET, which applies memory-centric, architecture-aware optimizations to FHE accelerators. It identifies conventional FHE constructions as sources of excessive working sets and off-chip traffic, and proposes accelerator-specific techniques including fine-grained coefficient-to-slot transformation, plaintext compression, and intermediate modulus raising to minimize temporary ciphertexts and plaintext loads. These are paired with lightweight architectural refinements such as a special-purpose buffer and functional unit extensions. The claimed outcomes are 1.38-8.74× per-area performance improvements over state-of-the-art FHE accelerators and the first sub-millisecond CKKS bootstrapping.

Significance. If the results hold, the work is significant for demonstrating the value of co-design between cryptographic constructions and accelerator architectures in FHE, a domain where these efforts have largely remained separate. The explicit parameter sets, area-normalized comparisons, and focus on reducing on-chip data footprint address a key practical bottleneck. The empirical results on accelerator models with implementation-level arguments for the transformations constitute a strength.

major comments (1)
  1. [Evaluation] Evaluation section: while the manuscript supplies implementation-level arguments and empirical results with explicit parameter sets for the performance claims, the abstract (and any corresponding high-level summary) does not detail the evaluation methodology, baseline accelerator configurations, error bars, or verification steps for the reported speedups and sub-millisecond bootstrapping latency; this detail is load-bearing for assessing the central quantitative claims.
minor comments (2)
  1. [Optimizations] The description of the coefficient-to-slot transformation in the optimizations section would benefit from an explicit small example showing before/after data layout to clarify the fine-grained aspect.
  2. [Architecture] Figure captions for the architectural diagrams should explicitly state the area and power models used for the per-area normalization.

Simulated Author's Rebuttal

1 responses · 0 unresolved

We thank the referee for the constructive feedback and positive assessment of the work. We address the single major comment below.

read point-by-point responses

  1. Referee: [Evaluation] Evaluation section: while the manuscript supplies implementation-level arguments and empirical results with explicit parameter sets for the performance claims, the abstract (and any corresponding high-level summary) does not detail the evaluation methodology, baseline accelerator configurations, error bars, or verification steps for the reported speedups and sub-millisecond bootstrapping latency; this detail is load-bearing for assessing the central quantitative claims.

    Authors: We agree that the abstract would benefit from a concise statement of the evaluation methodology to better support the central claims. In the revised version we will expand the abstract to briefly note the accelerator models and baselines used, the explicit parameter sets, the area-normalized comparison methodology, and the verification approach (cycle-accurate simulation cross-checked against RTL-level estimates) employed for the reported speedups and sub-millisecond CKKS bootstrapping latency. The detailed evaluation section already contains these elements; the change is limited to surfacing a high-level summary in the abstract. revision: yes

Circularity Check

0 steps flagged

No significant circularity

full rationale

The manuscript describes memory-centric optimizations (coefficient-to-slot transformation, plaintext compression, intermediate modulus raising) and lightweight architectural refinements for FHE accelerators, then reports measured per-area speedups (1.38-8.74×) and sub-millisecond CKKS bootstrapping as empirical outcomes of those techniques on explicit parameter sets. No derivation chain, fitted-parameter prediction, or first-principles result is claimed; the central claims rest on implementation-level arguments and area-normalized comparisons against prior accelerators rather than any self-referential reduction or self-citation load-bearing step. The evaluation methodology is self-contained against external benchmarks.

Axiom & Free-Parameter Ledger

0 free parameters · 1 axioms · 0 invented entities

The work rests on standard FHE security and correctness assumptions plus conventional accelerator memory models; no new free parameters, axioms, or invented entities are introduced in the abstract.

axioms (1)
  • domain assumption The listed transformations preserve the homomorphic properties and security of CKKS and similar schemes
    Implicit when applying the optimizations to standard FHE constructions on accelerators.

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