Paper Citation Record · LEDGER

STI-SNN: A 0.14 GOPS/W/PE Single-Timestep Inference FPGA-based SNN Accelerator with Algorithm and Hardware Co-Design

As of 7 August 2026, this Paper Citation Record lists 42 of 42 outbound references and 0 inbound Pith citation observations for arXiv:2506.08842.

A citation records a reference. It does not transfer a finding from one paper to another.

pith.paper-citation-record.v1
2506.08842 v1

Coverage vector

measured 42 of 42 reference resolution

Typed states for the displayed outbound observations.

Source: paper_references, paper_reference_links, observed 2026-08-07T05:07:11.578113Z

measured 42 of 42 standing notices

One-hop event checks from named stored sources.

Source: scholarly_work_events, retraction_status_cache, observed 2026-08-07T06:34:17.273281+00:00

measured 0 of 0 inbound itemization

Pith citing papers itemized under the disclosed page cap.

Source: paper_references, paper_reference_links

measured 0 of 1 external citation measurements

A source-named dated measurement, never combined with another source.

Source: cited_works

Reference resolution

42 of 42 outbound references displayed

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External citation measurements

No source-named external measurement is stored.

Outbound references

Observation afda0a83-7c9e-4389-bec4-e8024fd75538 · outbound

This paper cites Truenorth: Design and tool flow of a 65 mw 1 million neuron programmable neurosynaptic chip,.

STI-SNN: A 0.14 GOPS/W/PE Single-Timestep Inference FPGA-based SNN Accelerator with Algorithm and Hardware Co-Design Truenorth: Design and tool flow of a 65 mw 1 million neuron programmable neurosynaptic chip,

Reference 1

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T05:07:12.012704Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.

Observation 5256863a-ad8f-4b5b-8976-46825229f209 · outbound

This paper cites Loihi: A neuromorphic manycore processor with on-chip learning,.

STI-SNN: A 0.14 GOPS/W/PE Single-Timestep Inference FPGA-based SNN Accelerator with Algorithm and Hardware Co-Design Loihi: A neuromorphic manycore processor with on-chip learning,

Reference 2

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T05:07:12.002821Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.

Observation ba652d5b-8b58-44e2-8d9d-3417bbab1f2b · outbound

This paper cites S2n2: A fpga accelerator for streaming spiking neural networks,.

STI-SNN: A 0.14 GOPS/W/PE Single-Timestep Inference FPGA-based SNN Accelerator with Algorithm and Hardware Co-Design S2n2: A fpga accelerator for streaming spiking neural networks,

Reference 3

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T05:07:11.992024Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.

Observation 2a193455-f0dc-4720-83c8-b6b31159ba42 · outbound

This paper cites Neurogrid: A mixed-analog-digital multichip system for large-scale neural simulations,.

STI-SNN: A 0.14 GOPS/W/PE Single-Timestep Inference FPGA-based SNN Accelerator with Algorithm and Hardware Co-Design Neurogrid: A mixed-analog-digital multichip system for large-scale neural simulations,

Reference 4

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T05:07:11.981044Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.

Observation f42adea2-5697-430b-a4b4-3711176c8df4 · outbound

This paper cites Towards artificial general intelligence with hybrid tianjic chip architecture,.

STI-SNN: A 0.14 GOPS/W/PE Single-Timestep Inference FPGA-based SNN Accelerator with Algorithm and Hardware Co-Design Towards artificial general intelligence with hybrid tianjic chip architecture,

Reference 5

Resolution: unresolved; no resolver link, observed 2026-08-07T05:07:11.012571Z

Source-reported events for the cited work

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Observation d9e4740d-d73f-4c9a-a9c7-9c842ebab6d7 · outbound

This paper cites An energy-efficient spiking neural network accelerator based on spatio-temporal redundancy reduction,.

STI-SNN: A 0.14 GOPS/W/PE Single-Timestep Inference FPGA-based SNN Accelerator with Algorithm and Hardware Co-Design An energy-efficient spiking neural network accelerator based on spatio-temporal redundancy reduction,

Reference 6

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T05:07:11.963095Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.

Observation 1f191340-2d98-4796-a79f-63ece324cd2a · outbound

This paper cites Seenn: Towards temporal spiking early exit neural networks,.

STI-SNN: A 0.14 GOPS/W/PE Single-Timestep Inference FPGA-based SNN Accelerator with Algorithm and Hardware Co-Design Seenn: Towards temporal spiking early exit neural networks,

Reference 7

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T05:07:11.953164Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.

Observation 1ba9bab4-e933-4b60-b560-015dbd2c0854 · outbound

This paper cites Unleashing the potential of spik- ing neural networks with dynamic confidence,.

STI-SNN: A 0.14 GOPS/W/PE Single-Timestep Inference FPGA-based SNN Accelerator with Algorithm and Hardware Co-Design Unleashing the potential of spik- ing neural networks with dynamic confidence,

Reference 8

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T05:07:11.943693Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.

Observation 8e0ecea5-e1e1-461e-b62c-be21943473a7 · outbound

This paper cites Input-aware dynamic timestep spiking neural networks for efficient in-memory computing,.

STI-SNN: A 0.14 GOPS/W/PE Single-Timestep Inference FPGA-based SNN Accelerator with Algorithm and Hardware Co-Design Input-aware dynamic timestep spiking neural networks for efficient in-memory computing,

Reference 9

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T05:07:11.932769Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.

Observation ab05781a-5f88-4121-97e9-4f52297c4f95 · outbound

This paper cites Topspark: a timestep optimiza- tion methodology for energy-efficient spiking neural networks on au- tonomous mobile agents,.

STI-SNN: A 0.14 GOPS/W/PE Single-Timestep Inference FPGA-based SNN Accelerator with Algorithm and Hardware Co-Design Topspark: a timestep optimiza- tion methodology for energy-efficient spiking neural networks on au- tonomous mobile agents,

Reference 10

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T05:07:11.920484Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.

Observation 1d68b551-4384-4c7e-8c8a-8603121777d2 · outbound

This paper cites Diet-snn: A low-latency spiking neural network with direct input encoding and leakage and threshold optimization,.

STI-SNN: A 0.14 GOPS/W/PE Single-Timestep Inference FPGA-based SNN Accelerator with Algorithm and Hardware Co-Design Diet-snn: A low-latency spiking neural network with direct input encoding and leakage and threshold optimization,

Reference 11

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T05:07:11.908805Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.

Observation 3544fbbc-aced-43a0-88aa-292bef54c0b1 · outbound

This paper cites One Timestep is All You Need: Training Spiking Neural Networks with Ultra Low Latency.

STI-SNN: A 0.14 GOPS/W/PE Single-Timestep Inference FPGA-based SNN Accelerator with Algorithm and Hardware Co-Design One Timestep is All You Need: Training Spiking Neural Networks with Ultra Low Latency

Reference 12

Resolution: unresolved; no resolver link, observed 2026-08-07T05:07:11.461775Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 92b09b23-cee9-4b44-8f5f-49373dd2b1b8 · outbound

This paper cites an unresolved cited work.

STI-SNN: A 0.14 GOPS/W/PE Single-Timestep Inference FPGA-based SNN Accelerator with Algorithm and Hardware Co-Design Unresolved cited work

Reference 13

Resolution: unresolved; raw_fallback, observed 2026-08-07T05:07:11.897908Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.

Observation 3c89cc0d-eded-4344-b2bf-c7e8aaeeee1b · outbound

This paper cites Spikeconverter: An efficient conversion framework zipping the gap between artificial neural networks and spiking neural networks,.

STI-SNN: A 0.14 GOPS/W/PE Single-Timestep Inference FPGA-based SNN Accelerator with Algorithm and Hardware Co-Design Spikeconverter: An efficient conversion framework zipping the gap between artificial neural networks and spiking neural networks,

Reference 14

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T05:07:11.885317Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.

Observation 954337ea-ef75-4d44-b421-eb9181784cce · outbound

This paper cites Differen- tiable spike: Rethinking gradient-descent for training spiking neural networks,.

STI-SNN: A 0.14 GOPS/W/PE Single-Timestep Inference FPGA-based SNN Accelerator with Algorithm and Hardware Co-Design Differen- tiable spike: Rethinking gradient-descent for training spiking neural networks,

Reference 15

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T05:07:11.873376Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.

Observation e7db562b-022c-45c0-8a39-1e5a2f5bf0cc · outbound

This paper cites Rethinking the performance comparison between snns and anns,.

STI-SNN: A 0.14 GOPS/W/PE Single-Timestep Inference FPGA-based SNN Accelerator with Algorithm and Hardware Co-Design Rethinking the performance comparison between snns and anns,

Reference 16

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T05:07:11.861754Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.

Observation fa20b879-1c73-4994-99fa-9130ea75f734 · outbound

This paper cites Towards spike-based machine intelligence with neuromorphic computing,.

STI-SNN: A 0.14 GOPS/W/PE Single-Timestep Inference FPGA-based SNN Accelerator with Algorithm and Hardware Co-Design Towards spike-based machine intelligence with neuromorphic computing,

Reference 17

Resolution: unresolved; no resolver link, observed 2026-08-07T05:07:11.498432Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 3d73fc6d-0fb5-4b2f-b87d-3b79b96023fc · outbound

This paper cites Parallel time batching: Systolic- array acceleration of sparse spiking neural computation,.

STI-SNN: A 0.14 GOPS/W/PE Single-Timestep Inference FPGA-based SNN Accelerator with Algorithm and Hardware Co-Design Parallel time batching: Systolic- array acceleration of sparse spiking neural computation,

Reference 18

Resolution: unresolved; no resolver link, observed 2026-08-07T05:07:11.501312Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation af1a2db1-9d2c-4a77-9804-9959146caf1c · outbound

This paper cites Skydiver: A spiking neural network accelerator exploiting spatio-temporal workload balance,.

STI-SNN: A 0.14 GOPS/W/PE Single-Timestep Inference FPGA-based SNN Accelerator with Algorithm and Hardware Co-Design Skydiver: A spiking neural network accelerator exploiting spatio-temporal workload balance,

Reference 19

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T05:07:11.836992Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.

Observation c2c01892-3c81-4632-98f5-18e30f948b44 · outbound

This paper cites Sato: spiking neural network acceleration via temporal- oriented dataflow and architecture,.

STI-SNN: A 0.14 GOPS/W/PE Single-Timestep Inference FPGA-based SNN Accelerator with Algorithm and Hardware Co-Design Sato: spiking neural network acceleration via temporal- oriented dataflow and architecture,

Reference 20

Resolution: unresolved; no resolver link, observed 2026-08-07T05:07:11.507323Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation e9c986ec-c010-4894-aa80-cefd253b86a3 · outbound

This paper cites Spinalflow: An architecture and dataflow tailored for spiking neural networks,.

STI-SNN: A 0.14 GOPS/W/PE Single-Timestep Inference FPGA-based SNN Accelerator with Algorithm and Hardware Co-Design Spinalflow: An architecture and dataflow tailored for spiking neural networks,

Reference 21

Resolution: unresolved; no resolver link, observed 2026-08-07T05:07:11.510646Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation bb30473e-d3d6-48af-a665-01370b9f1596 · outbound

This paper cites Eyeriss: A spatial architecture for energy-efficient dataflow for convolutional neural networks,.

STI-SNN: A 0.14 GOPS/W/PE Single-Timestep Inference FPGA-based SNN Accelerator with Algorithm and Hardware Co-Design Eyeriss: A spatial architecture for energy-efficient dataflow for convolutional neural networks,

Reference 22

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T05:07:11.812435Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.

Observation 7fc47fd2-bc39-4f0a-88fe-3eb193813db4 · outbound

This paper cites Temporal Efficient Training of Spiking Neural Network via Gradient Re-weighting.

STI-SNN: A 0.14 GOPS/W/PE Single-Timestep Inference FPGA-based SNN Accelerator with Algorithm and Hardware Co-Design Temporal Efficient Training of Spiking Neural Network via Gradient Re-weighting

Reference 23

Resolution: unresolved; no resolver link, observed 2026-08-07T05:07:11.516763Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation aed45caa-fd32-4cd5-be65-5b62c5178c50 · outbound

This paper cites Dayan and L.

STI-SNN: A 0.14 GOPS/W/PE Single-Timestep Inference FPGA-based SNN Accelerator with Algorithm and Hardware Co-Design Dayan and L

Reference 24

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T05:07:11.802451Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.

Observation eeaecaf9-9d8e-4d4b-8565-c83eb270721a · outbound

This paper cites Spatio-temporal backpropa- gation for training high-performance spiking neural networks,.

STI-SNN: A 0.14 GOPS/W/PE Single-Timestep Inference FPGA-based SNN Accelerator with Algorithm and Hardware Co-Design Spatio-temporal backpropa- gation for training high-performance spiking neural networks,

Reference 25

Resolution: unresolved; no resolver link, observed 2026-08-07T05:07:11.523106Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 071e52d9-b613-47fb-bb1d-7c3ad7153c79 · outbound

This paper cites Training deep spiking neural networks using backpropagation,.

STI-SNN: A 0.14 GOPS/W/PE Single-Timestep Inference FPGA-based SNN Accelerator with Algorithm and Hardware Co-Design Training deep spiking neural networks using backpropagation,

Reference 26

Resolution: unresolved; no resolver link, observed 2026-08-07T05:07:11.526068Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 52ab12a5-1535-4c94-8118-c25442320695 · outbound

This paper cites Spikingjelly: An open-source machine learning infrastructure platform for spike-based intelligence,.

STI-SNN: A 0.14 GOPS/W/PE Single-Timestep Inference FPGA-based SNN Accelerator with Algorithm and Hardware Co-Design Spikingjelly: An open-source machine learning infrastructure platform for spike-based intelligence,

Reference 27

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T05:07:11.778713Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.

Observation fe629907-df55-49d5-aa81-d150e2446d91 · outbound

This paper cites Adaptive smoothing gradient learning for spiking neural networks,.

STI-SNN: A 0.14 GOPS/W/PE Single-Timestep Inference FPGA-based SNN Accelerator with Algorithm and Hardware Co-Design Adaptive smoothing gradient learning for spiking neural networks,

Reference 28

Resolution: unresolved; no resolver link, observed 2026-08-07T05:07:11.532043Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 68f507c3-60b0-49b4-bb5e-6009a7f31524 · outbound

This paper cites Learning multiple layers of features from tiny images,.

STI-SNN: A 0.14 GOPS/W/PE Single-Timestep Inference FPGA-based SNN Accelerator with Algorithm and Hardware Co-Design Learning multiple layers of features from tiny images,

Reference 29

Resolution: unresolved; no resolver link, observed 2026-08-07T05:07:11.535164Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation b1d5a7eb-5577-4a6e-a5b7-d37d29e76031 · outbound

This paper cites Tiny imagenet visual recognition challenge,.

STI-SNN: A 0.14 GOPS/W/PE Single-Timestep Inference FPGA-based SNN Accelerator with Algorithm and Hardware Co-Design Tiny imagenet visual recognition challenge,

Reference 30

Resolution: unresolved; no resolver link, observed 2026-08-07T05:07:11.538400Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 2d8d55bb-9597-44b1-8f62-66fe44d0ab7f · outbound

This paper cites Very Deep Convolutional Networks for Large-Scale Image Recognition.

STI-SNN: A 0.14 GOPS/W/PE Single-Timestep Inference FPGA-based SNN Accelerator with Algorithm and Hardware Co-Design Very Deep Convolutional Networks for Large-Scale Image Recognition

Reference 31

Resolution: unresolved; no resolver link, observed 2026-08-07T05:07:11.541521Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 499c7f89-8ae2-4099-8f20-faf2fcd2f7b1 · outbound

This paper cites Deep residual learning for image recognition,.

STI-SNN: A 0.14 GOPS/W/PE Single-Timestep Inference FPGA-based SNN Accelerator with Algorithm and Hardware Co-Design Deep residual learning for image recognition,

Reference 32

Resolution: unresolved; no resolver link, observed 2026-08-07T05:07:11.544910Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 567ddd2d-f091-4ce5-a037-06abae58c4c0 · outbound

This paper cites Going deeper with directly-trained larger spiking neural networks,.

STI-SNN: A 0.14 GOPS/W/PE Single-Timestep Inference FPGA-based SNN Accelerator with Algorithm and Hardware Co-Design Going deeper with directly-trained larger spiking neural networks,

Reference 33

Resolution: unresolved; no resolver link, observed 2026-08-07T05:07:11.548028Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation af039db7-25a9-4ee3-975b-14f1b89780da · outbound

This paper cites Optimal ANN-SNN Conversion for High-accuracy and Ultra-low-latency Spiking Neural Networks.

STI-SNN: A 0.14 GOPS/W/PE Single-Timestep Inference FPGA-based SNN Accelerator with Algorithm and Hardware Co-Design Optimal ANN-SNN Conversion for High-accuracy and Ultra-low-latency Spiking Neural Networks

Reference 34

Resolution: unresolved; no resolver link, observed 2026-08-07T05:07:11.551183Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 96b7a740-e0d8-4109-9942-1932d73fd712 · outbound

This paper cites Spike-thrift: Towards energy-efficient deep spiking neural networks by limiting spiking activity via attention-guided compression,.

STI-SNN: A 0.14 GOPS/W/PE Single-Timestep Inference FPGA-based SNN Accelerator with Algorithm and Hardware Co-Design Spike-thrift: Towards energy-efficient deep spiking neural networks by limiting spiking activity via attention-guided compression,

Reference 35

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T05:07:11.733437Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.

Observation be6ca48c-1496-4833-b668-5e614d05c0db · outbound

This paper cites Temporal effective batch normalization in spiking neural networks,.

STI-SNN: A 0.14 GOPS/W/PE Single-Timestep Inference FPGA-based SNN Accelerator with Algorithm and Hardware Co-Design Temporal effective batch normalization in spiking neural networks,

Reference 36

Resolution: unresolved; no resolver link, observed 2026-08-07T05:07:11.558177Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 325cfbd8-f160-431d-b252-d41a325ce8c5 · outbound

This paper cites SNN2ANN: A Fast and Memory-Efficient Training Framework for Spiking Neural Networks.

STI-SNN: A 0.14 GOPS/W/PE Single-Timestep Inference FPGA-based SNN Accelerator with Algorithm and Hardware Co-Design SNN2ANN: A Fast and Memory-Efficient Training Framework for Spiking Neural Networks

Reference 37

Resolution: verified exact; local_arxiv, observed 2026-08-07T05:07:11.616467Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.

Observation 626c470a-9047-41c5-84e0-6aea1b485278 · outbound

This paper cites Encoding, model, and architecture: Systematic optimization for spiking neural network in fpgas,.

STI-SNN: A 0.14 GOPS/W/PE Single-Timestep Inference FPGA-based SNN Accelerator with Algorithm and Hardware Co-Design Encoding, model, and architecture: Systematic optimization for spiking neural network in fpgas,

Reference 38

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T05:07:11.715229Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.

Observation 8f10a9f2-9d73-41bb-b536-43ef34b9c09d · outbound

This paper cites The implementation and optimization of neuromorphic hardware for supporting spiking neural networks with mlp and cnn topologies,.

STI-SNN: A 0.14 GOPS/W/PE Single-Timestep Inference FPGA-based SNN Accelerator with Algorithm and Hardware Co-Design The implementation and optimization of neuromorphic hardware for supporting spiking neural networks with mlp and cnn topologies,

Reference 39

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T05:07:11.704404Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.

Observation 545038dd-5e02-4890-a7e6-b6c10618473f · outbound

This paper cites An fpga implementation of deep spiking neural networks for low-power and fast classification,.

STI-SNN: A 0.14 GOPS/W/PE Single-Timestep Inference FPGA-based SNN Accelerator with Algorithm and Hardware Co-Design An fpga implementation of deep spiking neural networks for low-power and fast classification,

Reference 40

Resolution: unresolved; no resolver link, observed 2026-08-07T05:07:11.571507Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 6bc946a2-680a-40be-a42a-cab3173f781e · outbound

This paper cites Cerebron: A reconfigurable architecture for spatiotemporal sparse spiking neural networks,.

STI-SNN: A 0.14 GOPS/W/PE Single-Timestep Inference FPGA-based SNN Accelerator with Algorithm and Hardware Co-Design Cerebron: A reconfigurable architecture for spatiotemporal sparse spiking neural networks,

Reference 41

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T05:07:11.685924Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.

Observation a9047b19-dfe1-4b67-bbde-b222fd7456ea · outbound

This paper cites Firefly: A high- throughput hardware accelerator for spiking neural networks with effi- cient dsp and memory optimization,.

STI-SNN: A 0.14 GOPS/W/PE Single-Timestep Inference FPGA-based SNN Accelerator with Algorithm and Hardware Co-Design Firefly: A high- throughput hardware accelerator for spiking neural networks with effi- cient dsp and memory optimization,

Reference 42

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T05:07:11.670196Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.

Pith citing papers

No inbound Pith citation observations are available.