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REVIEW 3 major objections 4 minor 56 references

Do Not Let CNOTs Overwhelm the Decoder: Scheduling Transversal Gates for Fast FTQC

T0 review · 3 major / 4 minor · reviewed 2026-08-16 · deepseek-v4-flash

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Pith's one-line read PACE claims that scheduling transversal CNOTs around classical decoder capacity speeds quantum execution up to 7.86x over the All-d baseline while keeping real-time decoding feasible.

desk verdict PACE is a legitimate systems contribution, but its headline speedup claims rest on a decoder model that the authors themselves flag as an approximation, so take them as conditional. read the letter →

arxiv 2608.11719 v1 pith:MNA7TQKX submitted 2026-08-12 quant-ph cs.AR

Shota Ikari , Yuga Hirai , Yasunari Suzuki , Hiroshi Nakamura , Yosuke Ueno This is my paper · ORCID
classification quant-phcs.AR
keywords transversalCNOTgatessurfacecodesreal-timedecodingdecoder-awareschedulingwindowjust-in-timedetectorerrormodelsfault-tolerantquantumcomputingneutral-atomarchitectures
verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

Transversal CNOT gates can cut the syndrome-extraction rounds between logical operations from $O(d)$ to $O(1)$, but this paper argues that the real bottleneck is the classical decoder: correlated errors across patches inflate decoding volume, schedule-dependent detector error models can no longer all be precomputed, and dense schedules outgrow decoder memory and latency. PACE is a scheduling framework that attacks these three costs with per-window choice between matchable and unmatchable decoders, just-in-time assembly of window detector error models from reusable templates, and sub-window parallel decoding that decomposes large windows. Its scheduler then packs TCNOTs as densely as the modeled decoder resources permit, converting spare decoding capacity into quantum execution speedup. On ten benchmark circuits, the selected schedules run up to 7.86x faster than the conservative All-d baseline at the largest evaluated decoder capacity, while currently configured unmatchable decoders would not reach even the All-d schedule's minimum capacity. The paper's contribution is to reframe the promise of transversal gates from a hardware question into a scheduling and decoder-resource question.

What carries the argument

The carrying object is the decoding volume $V=qw/W$, a scalar for a decoding task covering $q$ logical patches over a window length $w$ normalized by the standard window height $W$. PACE models each decoder-side cost, DEM preparation latency, working memory, and decoding latency, as a power law $\alpha V^\gamma$ of this volume, and the feasibility constraints in Eq. (4) bound both the largest per-sub-window volume and the accumulated latency of the colored decoding layers. The three techniques act on this machinery directly: Hybrid Window Decoding shrinks the set of tasks needing unmatchable decoders, DEM Stitch cuts the prefactor of DEM-preparation cost through reusable templates, and Sub-window Parallel Decoding replaces one large window with colored sub-windows so the volume constraints are checked at sub-window granularity.

What would settle it

Hold decoding volume fixed on multi-patch TCNOT windows while varying only hyperedge density and topology, measuring the unmatchable decoders' latency and memory; if these grow faster than the fitted $V^\gamma$ power laws, then Eq. (4) is optimistic and PACE-selected schedules could miss their real-time deadlines.

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Extended reading notes

Core claim

On its own terms, PACE establishes that the decoder-side costs of TCNOTs can be controlled by three mechanisms and that, once controlled, TCNOT density becomes a schedulable quantity. Hybrid Window Decoding routes each decoding window to a cheap matchable decoder when its detector error model is graphlike and to an unmatchable decoder otherwise, with a window-wise correction step that lets different decoder types coexist in one pipeline. DEM Stitch precompiles reusable local fault templates and stitches them into schedule-specific window detector error models just in time, avoiding exponential precompilation. Sub-window Parallel Decoding forms sub-windows from a TCNOT-event graph and colors the resulting conflict graph so that non-conflicting sub-windows decode in parallel. The scheduler searches a bounded family of spacing policies and selects the shortest schedule whose windows satisfy the capacity constraints in Eq. (4), yielding geometric-mean speedups over All-d from 1.06x at $V_{dec}=4$ to 7.86x at $V_{dec}=64$, with current decoder systems still unable to reach even the All-d feasibility point.

Load-bearing premise

The load-bearing premise is that a single number, the decoding volume $V=qw/W$, predicts DEM preparation time, decoder memory, and decoding latency through fixed power laws even for multi-patch TCNOT windows, and the paper itself notes that this ignores hyperedge density and topology.

Editorial extensions

If this is right

  • Under PACE's model, decoder capacity becomes a first-class scheduling resource: raising $V_{dec}$ or $V_{unit}$ shortens the selected TCNOT schedule without any change to the quantum hardware.
  • The exponential diversity of window-level detector error models means online DEM compilation is unavoidable for aggressive TCNOT scheduling, so template-based just-in-time assembly is a necessary system component.
  • Because current unmatchable-decoder configurations do not reach the minimum capacities of even the All-d schedule at $d=23$, TCNOT-based FTQC needs faster unmatchable decoding, larger decoder memory, or a longer syndrome-extraction period.
  • Even at the highest evaluated decoder capacity, more than half of the decoding volume on average remains graphlike, so hybrid routing to matchable decoders continues to matter.
  • Workloads with higher data-loading parallelism place more correlated TCNOTs in each decoding window and therefore need larger decoder capacity before dense schedules become feasible.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

  • The volume-only power-law model is the weakest point to test first: a direct measurement on multi-patch TCNOT windows with constant volume but varying hyperedge density would show whether Eq. (4) needs a topology-dependent term before these speedups can be trusted on hardware.
  • The same capacity-versus-schedule tradeoff could be applied to other classical resources, such as magic-state distillation throughput or network bandwidth, by expressing them as similar per-window constraints.
  • Since PACE still produces beneficial schedules when non-graphlike tasks are converted to graphlike decoding, decoder-aware scheduling and fast correlated decoding are likely complementary and could be combined into one pipeline.
  • A concrete extension would be to replace $V=qw/W$ with an effective volume that weights hyperedges and then rerun the capacity sweeps; the gap between the two results would quantify how much the hyperedge approximation matters.
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Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Referee Report

3 major / 4 minor

Summary. This paper proposes PACE, a decoder-aware scheduling framework for fault-tolerant quantum computation that uses transversal CNOT (TCNOT) gates on surface-code patches. PACE combines three decoder-side techniques: hybrid window decoding, which routes graphlike windows to fast matchable decoders and non-graphlike windows to unmatchable decoders; DEM Stitch, a template-based just-in-time method for constructing schedule-specific detector error models; and sub-window parallel decoding (SPD), which decomposes large decoding windows into smaller sub-windows via graph coloring. The scheduler then searches a bounded family of spacing policies to find the densest TCNOT schedule that satisfies power-law feasibility constraints on DEM-preparation latency, decoder memory, and decoding latency (Eqs. (4)-(5)). The evaluation shows that hybrid decoding preserves logical error rates, DEM Stitch reduces DEM compilation time by 108.4x for a d=23 memory window, SPD reduces peak decoding volume, and PACE achieves speedups over the All-d baseline up to 7.86x at normalized capacity V_dec=64. A case study concludes that current unmatchable-decoder configurations do not meet even the minimum capacities required for the All-d schedule.

Significance. If the central capacity-model extrapolation is validated, PACE would fill a real gap by making decoder capacity an explicit, schedulable resource for TCNOT-based FTQC. The three component techniques are individually well motivated and each has a concrete experiment supporting its component claim: hybrid decoding matches BP-LSD error rates, DEM Stitch shows a large compilation speedup, and SPD reduces decoding volume. The paper is also honest about many of its assumptions, and the sensitivity analysis with respect to gamma_dec is a useful addition. The concern that the scheduler is circular because it optimizes against the same model used for feasibility is not, in my reading, a defect: this is standard co-design, not hidden circularity. The real risk is external validity: the feasibility model in Sec. 5.1 and the headline speedups in Sec. 7.4 are built on a volume-only power-law scaling of decoder cost, fitted in Sec. 7.6 to single-patch memory windows and then applied to multi-patch TCNOT windows whose DEMs contain hyperedges. The paper itself concedes in Sec. 7.6 that this approximation does not model hyperedge density or topology.

major comments (3)
  1. [Sec. 5.1 / Table 1 / Eq. (4) / Sec. 7.6] The load-bearing feasibility model defines decoding volume as V=qw/W and models DEM-preparation latency, decoder working memory, and decoding latency as power-law functions of V. The exponents and constants are fitted in Sec. 7.6 to one-patch memory windows (q=1, d<=w<=3d) and then applied to multi-patch TCNOT windows whose DEMs contain hyperedges. The paper itself states in Sec. 7.6 that this volume-only approximation 'does not model additional dependence on hyperedge density or topology.' For unmatchable decoders such as BP-LSD and Relay-BP, the number and structure of hyperedges can significantly affect both runtime and memory usage; a single fault that propagates across k patches can appear as a k-way hyperedge, and decoder cost need not scale with detector count alone. If multi-patch TCNOT tasks scale worse than the fitted volume-only power law, Eq. (4) understates decoder load, the schedules selected in Sec. 7.4 could miss real-time deadlines, and the infeasibility conclusion for current decoders in Sec. 7.6 could shift. I ask the authors to provide direct measurements or a validated model of decoding latency and memory on multi-patch TCNOT windows (e.g., two- and four-patch windows spanning the relevant code distances) and to re-run the Sec. 7.4 and Sec. 7.6 analyses with that data. Until then, the quantitative speedup and infeasibility claims are contingent on an untested extrapolation.
  2. [Sec. 4.2 / Algorithm 1 / Sec. 7.2] The correctness of the JIT DEM pipeline rests on the claim that DEM Stitch produces a window-level DEM equivalent to full-circuit construction. The evaluation in Sec. 7.2 measures only compilation latency and template-cache footprint; it does not verify that the stitched DEM and the full Stim DEM have identical detector check matrix H, logical action matrix A, and fault probabilities p for any TCNOT window. If stitching introduces errors in detector indexing, logical-observable propagation, or temporal-port resolution, then schedules deemed feasible by Eq. (4) could be decoded incorrectly even when latency and memory constraints are met. I ask the authors to add an equivalence test that compares syndrome and logical-observable predictions of stitched versus full-circuit DEMs across randomized schedules, and to report the result for at least one multi-patch TCNOT window.
  3. [Sec. 7.4 / Sec. 7.6] The speedups reported in Fig. 14 (up to 7.86x at V_dec=64) are computed under normalized decoder capacities that, according to the paper's own Sec. 7.6 case study, are not met by any of the evaluated current unmatchable-decoder configurations: none reaches even the minimum capacities required for the All-d schedule (V_dec>=2 and V_unit>=2). Consequently, the headline speedup numbers do not represent what PACE would deliver with a decoder characterized in this paper; at feasible current capacities the selected schedules are close to All-d (1.06x at V_dec=4). The manuscript should state this distinction prominently in the abstract and in Sec. 7.4, and should frame the current-hardware result as 'PACE identifies infeasibility and required capacity improvements' rather than as a realized speedup. This does not invalidate the framework, but the current presentation overstates the practical benefit that the paper can support.
minor comments (4)
  1. [Sec. 5.3 / Algorithm 2] The paper states that PACE 'schedules TCNOTs as densely as the available decoder resources permit,' but the scheduler restricts the search to a bounded family of period-p spacing policies and selects the shortest candidate in that family. The manuscript should phrase the objective as finding the best schedule within the evaluated policy family, not as unconstrained densest scheduling.
  2. [Sec. 7.2 / Fig. 12] Figure 12(b) reports preparation time versus number of patches, but the text does not specify whether all data points share the same code distance and window height; please state these parameters in the caption and the text.
  3. [Sec. 7.6 / Table 3] The Relay-BP FPGA projection assumes linear scaling of decoding latency with decoding volume based on a quoted 24 ns per iteration. Since this linearity is not measured for the multi-patch structures considered, please explicitly label it as an assumption and discuss how a superlinear scaling would affect the conclusions.
  4. [Sec. 8.1] The finite-decoder-pool discussion is useful but should be cross-referenced from Sec. 5.2, where the feasibility constraints assume sufficient concurrent DEM preparation and decoder instances; otherwise readers may mistake this assumption for a demonstrated architectural requirement.

Circularity Check

0 steps flagged · score 0.0 of 10

No circularity: PACE's decoder-aware scheduling is a transparent co-design loop with externally fitted capacity parameters, not a hidden reduction of inputs to outputs.

full rationale

The paper's derivation chain is self-contained with respect to circularity. The feasibility model in Table 1 and Eq. (4) defines decoder capacity using power-law functions of decoding volume V = q w / W, and the coefficients and exponents are fit in Sec. 7.6 to independent one-patch memory-window measurements for BP-LSD, Relay-BP, and PyMatching, plus DEM Stitch timings from Sec. 7.2. Algorithm 2 then retains only schedules satisfying Eq. (4), so a schedule's 'feasible' status is defined relative to that model; however, the model parameters are not derived from the reported speedups. The speedups in Fig. 14 are outputs of sweeping V_dec and V_unit and selecting the shortest satisfying schedule, not fitted values renamed as predictions. The paper explicitly labels Sec. 7.6 as a case study and concedes that the volume-only approximation 'does not model additional dependence on hyperedge density or topology', which is a validity limitation for extrapolating single-patch fits to multi-patch TCNOT tasks, not a circular step. Self-citations to [2] and [53] are background and benchmark-generation methodology, respectively, and neither is load-bearing for the central scheduling or speedup claims. No equation is defined in terms of its own output, and no fitted parameter is presented as an independent prediction.

Assumptions & free parameters 4 free parameters · 7 assumptions · 0 invented entities

No invented physical entities. The framework's abstractions (temporal ports, sub-windows, templates) are algorithmic constructs, not new degrees of freedom in the model. The free parameters are dominated by the assumed power-law capacity model; the main speedup claim is conditional on gamma_dec=1.25 and the swept capacities V_dec and V_unit. The axioms are a mix of standard surface-code/window-decoding assumptions and ad-hoc-to-paper modeling choices that should be validated in follow-up work.

free parameters (4)
  • decoding-latency exponent gamma_dec = 1.25 in the main sweep (Sec 7.4); swept from 0.75 to 2.5 in Sec 7.5
    The power-law exponent for decoder latency versus decoding volume is assumed, not measured, in the central speedup evaluation. The headline speedups in Fig 14 are conditional on gamma_dec=1.25.
  • normalized decoder capacities V_dec and V_unit = swept over {4, 8, 16, 32, 64}; V_dec=2 and infinity serve as All-d and ASAP references
    These are model inputs representing hypothetical decoder resources in the main sweep, not measured system capacities. Speedup claims are parameterized by these values.
  • syndrome extraction period tau_SE = 1 ms, following reference [54]
    Sets the real-time deadline Delta = d * tau_SE in Eq. (4). The feasibility conclusions scale linearly with tau_SE.
  • power-law scaling constants and exponents for BP-LSD, Relay-BP, and PyMatching = not reported in the text; fitted in Sec 7.6 to one-patch memory windows
    Used in the case study (Fig 18) and extrapolated to multi-patch TCNOT tasks despite the volume-only approximation. The fitted values are not released, hindering replication.
assumptions (7)
  • domain assumption Transversal CNOT gates require only O(1) syndrome-extraction rounds between logical operations under suitable decoding assumptions.
    Sec 2.2, taken from refs [54,55]. This is the entire quantum-side acceleration premise on which the scheduling tradeoff rests.
  • domain assumption A buffer region of W_B=d rounds is sufficient to preserve code distance across the commit region in sliding-window decoding.
    Sec 2.4. Sub-window parallel decoding relies on this buffer rule to split windows into variable-height overlapping pieces.
  • ad hoc to paper Decoder performance components (DEM preparation latency, working memory, decoding latency) scale as power-law functions of decoding volume V=q w / W.
    Sec 5.1, Table 1. The exponents are fitted to one-patch data in Sec 7.6 and extrapolated to multi-patch TCNOT windows; the authors concede the model ignores hyperedge density and topology.
  • domain assumption Sufficient decoder instances exist to process all sub-windows in the same layer in parallel and to prepare all sub-window DEMs concurrently.
    Sec 5.2 and Sec 8.1. The feasibility conditions in Eq. (4) use per-layer maxima rather than a finite decoder pool; the authors flag this as a limitation.
  • ad hoc to paper DEM Stitch, by assembling local templates with temporal ports, produces a detector error model equivalent to full-circuit construction.
    Sec 4.2. The evaluation in Sec 7.2 measures only preparation time and memory footprint, not decoding equivalence on multi-TCNOT windows.
  • domain assumption The instruction set with magic-state teleportation for S and T gates, with |Y> and |T> states always available and worst-case conditional S corrections, is the correct logical-gate model.
    Sec 2.6 and Sec 6.3. This determines the prevalence of TCNOTs in benchmarks and the instruction mix in Fig 5.
  • standard math Graphlike DEMs are exactly those in which every fault flips at most two detectors, and matchable versus unmatchable decoder capabilities align with this distinction.
    Sec 2.3. This standard definition underpins Hybrid Window Decoding's per-window decoder assignment.

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Pith. "Pith review of Do Not Let CNOTs Overwhelm the Decoder: Scheduling Transversal Gates for Fast FTQC." pith.science (2026). https://pith.science/paper/MNA7TQKX

@misc{pith2026260811719,
  author       = {Pith},
  title        = {Pith review of: Do Not Let CNOTs Overwhelm the Decoder: Scheduling Transversal Gates for Fast FTQC},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/MNA7TQKX}},
  note         = {Machine review of arXiv:2608.11719}
}
abstract

Transversal CNOT (TCNOT) gates can accelerate fault-tolerant quantum computation (FTQC) in the surface code by reducing the number of syndrome extraction rounds required between logical operations from $O(d)$ to $O(1)$. This is particularly attractive for quantum platforms with long-range connectivity, such as neutral atoms. However, dense TCNOT schedules substantially increase the classical decoding workload. TCNOTs propagate errors across multiple surface-code patches, enlarging the spatiotemporal region that must be decoded jointly. Consequently, denser TCNOT schedules increase decoding latency and memory requirements and potentially exceed available decoder capacity. Moreover, because the detector error model (DEM) of each decoding window depends on the TCNOT schedule, exhaustively precomputing all possible window-level DEMs is infeasible, requiring just-in-time (JIT) DEM compilation. Thus, the practical benefit of TCNOT gates is limited not only by quantum hardware performance but also by classical decoding and DEM-compilation capacity. We introduce PACE, a decoder-aware scheduling framework for TCNOT-based FTQC. PACE first mitigates the decoder-side costs of aggressive TCNOT scheduling through three complementary techniques. Hybrid Window Decoding assigns different decoders for each decoding window according to its DEM structure. DEM Stitch generates schedule-specific window-level DEMs just in time by assembling reusable precompiled fragments. Sub-window Parallel Decoding decomposes large windows into smaller sub-windows with graph-coloring formulation. Building on these techniques, PACE then performs decoder-aware scheduling to maximize TCNOT concurrency within the available decoder resources. Our evaluation shows the trade-off between quantum acceleration and classical decoding cost, revealing the limitations of current decoding systems for TCNOT-based FTQC.

Figures

Figures reproduced from arXiv: 2608.11719 by the authors.

Figure 1
Figure 1. Motivation of PACE. (a) Dense TCNOT scheduling enlarges the decoding window, rapidly increasing decoder workload. [PITH_FULL_IMAGE:figures/full_fig_p002_1.png] view at source ↗
Figure 2
Figure 2. (a) A distance-three rotated surface code. (b) A DEM for a memory experiment. (c) A TCNOT can flip more than two [PITH_FULL_IMAGE:figures/full_fig_p003_2.png] view at source ↗
Figure 3
Figure 3. Execution pipeline of the FTQC system considered [PITH_FULL_IMAGE:figures/full_fig_p003_3.png] view at source ↗
Figures from the paper (13 more)
Figure 5
Figure 5. Figure 5: Instruction breakdown of the benchmark circuits [PITH_FULL_IMAGE:figures/full_fig_p004_5.png]
Figure 6
Figure 6. Figure 6: The memory footprint of DEM construction and [PITH_FULL_IMAGE:figures/full_fig_p004_6.png]
Figure 8
Figure 8. Figure 8: Per-window decoder selection in Hybrid window. [PITH_FULL_IMAGE:figures/full_fig_p005_8.png]
Figure 9
Figure 9. Figure 9: Overview of DEM Stitch: (a) an example of a local template, (b) stitching local templates along the time dimension, (c) [PITH_FULL_IMAGE:figures/full_fig_p006_9.png]
Figure 10
Figure 10. Figure 10: (a) Example of a height-2𝑑 window with TCNOTs. SPD decomposes the window into smaller sub-windows when #SE ≥ 𝑑 between consecutive TCNOT events on the same logical qubit. Sub-windows with the same color are decoded in parallel. (b) Graph construction for SPD. Short-ed…
Figure 11
Figure 11. Figure 11: (a): Hybrid window decoding experiment using Bell-pair preparation with TCNOT. (b): Logical error rates for Hybrid [PITH_FULL_IMAGE:figures/full_fig_p010_11.png]
Figure 12
Figure 12. Figure 12: Online construction of schedule-specific DEMs. (a) Preparation time for a [PITH_FULL_IMAGE:figures/full_fig_p010_12.png]
Figure 13
Figure 13. Figure 13: Peak decoding volume for fixed TCNOT spacing [PITH_FULL_IMAGE:figures/full_fig_p011_13.png]
Figure 14
Figure 14. Figure 14: Quantum-execution speedup of schedules adaptively selected by PACE under independent capacity sweeps. Each [PITH_FULL_IMAGE:figures/full_fig_p011_14.png]
Figure 15
Figure 15. Figure 15: Per-workload ratio of graphlike to total decoding volume for the schedules selected by the [PITH_FULL_IMAGE:figures/full_fig_p011_15.png]
Figure 16
Figure 16. Figure 16: Effect of the decoding-time scaling exponent [PITH_FULL_IMAGE:figures/full_fig_p013_16.png]
Figure 17
Figure 17. Figure 17: Memory-side capacity 𝑉mem derived from the measured working-memory scaling of 𝑊 = 2𝑑 decoding windows. 10 −1 10 1 10 3 10 5 d = 15 10 −1 10 1 10 3 10 5 D e c o din g v olu m e V d = 19 PyMatching/CPU BP-LSD/CPU Relay-BP/FPGA 10 −1 10 1 10 3 10 5 d = 23 10 0 10 2 10 4 …
Figure 18
Figure 18. Figure 18: Capacities of the representative decoder configurations. (a) DEM preparation, working-memory, and decoding latency [PITH_FULL_IMAGE:figures/full_fig_p013_18.png]

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Pith tools

Reviewed August 16, 2026 · model on record in the stance chip above.