Pith. sign in

REVIEW 3 major objections 6 minor 69 references

AWB-GCN: A Graph Convolutional Network Accelerator with Runtime Workload Rebalancing

T0 review · 3 major / 6 minor · reviewed 2026-08-14 · deepseek-v4-flash

Challenge this review Re-run · record.json Download PDF Read on arXiv ↗ Review JSON

Pith's one-line read A GCN accelerator that autotunes workload distribution at runtime can lift processing-element utilization on power-law graphs from about 7 percent to 88 percent and outperform CPUs, GPUs, and prior GCN accelerators by large margins.

desk verdict Real FPGA GCN accelerator with credible utilization gains from runtime rebalancing, but the autotuner convergence story is under-specified and the headline CPU/GPU speedups rest on a thin baseline. read the letter →

arxiv 1908.10834 v10 pith:MZU4SVOT submitted 2019-08-23 cs.DC cs.LG

Tong Geng , Ang Li , Runbin Shi , Chunshu Wu , Tianqi Wang , Yanfei Li , Pouya Haghi , Antonino Tumeo
show 3 more authors
Shuai Che Steve Reinhardt Martin Herbordt
This is my paper · ORCID
classification cs.DCcs.LG
keywords graphconvolutionalnetworkhardwareacceleratorworkloadbalancingpower-lawgraphssparsematrixmultiplicationFPGAautotuningGCNinference
verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

AWB-GCN is a hardware accelerator for graph convolutional network (GCN) inference whose central claim is that runtime hardware autotuning can eliminate the workload imbalance that cripples massively parallel processors on power-law graph matrices. The paper proposes three rebalancing techniques—distribution smoothing, remote switching, and evil row remapping—that together raise processing-element utilization from about 7 percent to 88 percent on the most skewed dataset and deliver average speedups of 3255x over CPU, 80.3x over GPU, and 5.1x over a prior GCN accelerator. If correct, this means dedicated GCN hardware can operate near its theoretical peak despite extremely sparse, highly clustered adjacency matrices.

What carries the argument

The load-bearing mechanism is a hardware autotuning loop wrapped around column-wise-product sparse-matrix–dense-matrix multiplication. The PE status monitor reads task-queue occupancy to identify overloaded and underloaded PEs; the utilization-gap tracker estimates execution-cycle gaps and, via a table lookup, computes switch fractions; and the workload distribution controller updates shuffle-switch routing so rows or row fractions land on the new PEs next round. Distribution smoothing handles local fluctuation, remote switching handles regionally clustered non-zeros, and evil row remapping handles the few extremely dense rows that dominate time. This three-level rebalancing is what lets the architecture reuse one converged configuration over many rounds.

What would settle it

One concrete test would be to run the same accelerator on a power-law graph whose edge set changes every few rounds, or on a synthetic matrix where the autotuner needs more rounds than the computation has output columns; if utilization collapses back toward baseline levels, the convergence-and-reuse assumption is what failed.

Watch

Extended reading notes

Core claim

The paper's central discovery is that workload imbalance on power-law graphs is best treated as a runtime hardware control problem rather than a preprocessing or static-mapping problem. AWB-GCN continuously profiles how many tasks each processing element (PE) has pending, and within each round (one output column of $A(XW)$) applies three rebalancing moves: distribution smoothing shifts tasks from busy PEs to less-busy neighbors, remote switching exchanges row-fraction workloads between utilization peaks and troughs, and evil row remapping splits rows that are too dense to be balanced and spreads them across underloaded labor PEs. After about ten rounds the autotuner converges and the winning distribution is reused for the rest of inference. Across five standard datasets the 4096-PE design raises average PE utilization from 7–56 percent in the baseline to 77–99 percent, and the paper reports average speedups of 3255x over CPU, 80.3x over GPU, and 5.1x over a prior GCN accelerator.

Load-bearing premise

The load-bearing premise is that the runtime profiler converges to a near-optimal workload distribution within a few rounds and that the graph matrix stays fixed so the reused configuration remains optimal for all remaining rounds.

Editorial extensions

If this is right

  • Average processing-element utilization rises from 7–56 percent in the baseline to 77–99 percent across the five datasets, and the reported speedups reach 3255x over CPU, 80.3x over GPU, and 5.1x over a prior GCN accelerator.
  • Utilization stays high as PE count grows from 512 to 4096, so performance scales nearly linearly instead of degrading as rows per PE shrink.
  • The added rebalancing logic is cheap: distribution smoothing costs 3.5–6.7 percent ALM-area on average and remote switching plus row remapping costs about 0.9 percent, while the more balanced queues actually reduce on-chip storage needs.
  • Because the same $A(XW)$ kernel underlies many graph neural networks, the accelerator design is claimed to extend to other GNN variants with the core sparse-matrix multiplication unchanged.
  • The autotuner reaches a converged strategy within about ten rounds, so most rounds run under the near-optimal configuration.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

  • The same three-level rebalancing scheme could be applied to other irregular sparse workloads—sparse attention, SpMV, graph sampling—wherever work is partitionable by rows and the sparse structure is reused over many iterations.
  • If the graph changes during inference, the convergence-and-reuse strategy would need an incremental re-tuning loop; a natural extension is to retrigger autotuning on matrix snapshots and measure how many rounds are needed before utilization recovers.
  • The headline CPU/GPU multiples compare a purpose-built low-frequency accelerator to general-purpose processors running a general-purpose software stack, so part of the gap is architectural specialization; an area- or energy-normalized comparison would isolate the workload-balancing contribution.
Share X Bluesky LinkedIn Reddit HN

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Referee Report

3 major / 6 minor

Summary. The paper proposes AWB-GCN, an FPGA-based accelerator for Graph Convolutional Network inference, and addresses the workload imbalance that arises when multiplying a power-law sparse adjacency matrix by a dense feature matrix. The architecture combines a baseline SpMM engine with three runtime, hardware-implemented rebalancing techniques: distribution smoothing, remote switching, and evil row remapping. The authors report that the complete design raises average PE utilization from baseline values of 7--82% to 88--99% across five datasets, and claim end-to-end speedups of 3255x over a PyG-based CPU implementation, 80.3x over a PyG-based GPU implementation, and 5.1x over the HyGCN accelerator. The evaluation is performed on an Intel D5005 FPGA with Cora, Citeseer, Pubmed, Nell, and Reddit datasets, and includes utilization traces, scalability studies, resource usage, and cross-platform comparisons.

Significance. If the results hold, the paper makes a useful contribution to the growing area of GCN accelerators: it identifies workload imbalance as the key bottleneck for power-law graph SpMM, and proposes a hardware-level autotuning mechanism that is more fine-grained than prior block-wise scheduling. The work is strengthened by a real FPGA implementation with hardware counters for utilization, a comparison against a prior GCN accelerator, and a clear decomposition of the design choices (Baseline, Designs A--D). The reported utilization improvements are internally consistent with the baseline measurements, and the per-round traces in Figure 17 provide direct evidence that the implemented system converges. The main risk is that the published update rule for remote switching, Eq. (6), does not, as written, guarantee the convergence on which the headline utilization and speedup numbers rest. The absolute CPU/GPU speedup figures also need clearer reporting, because the abstract numbers do not match the per-benchmark-set numbers in Section V.D.

major comments (3)
  1. [Section IV.B, Eq. (6) and Fig. 17] The update rule in Eq. (6) adds a positive term proportional to the current gap in every update, with no sign, damping, or clipping term. If a switch overshoots, the overloaded and underloaded PEs in a tuple swap roles, and the same additive update would then move the switch fraction further in that direction, so the recurrence as written is not guaranteed to converge. The text says the system is 'highly likely to converge' and that the converged configuration is reused for the remainder of the computation, and Figure 17 shows convergence in the implemented design, but the published algorithm omits the details needed to verify this behavior (Section IV.B states 'More details are omitted due to space limitations'). Because the 88--99% utilization and the derived speedups depend on convergence within a few rounds, please provide a corrected signed/damped update, a stability analysis, or a measured trace from the implemented controller that shows the actual update values used.
  2. [Section V.D, Tables III--IV and Abstract] The abstract and conclusion report average speedups of 3255x over CPU and 80.3x over GPU, but Section V.D reports 2622x and 136x for the standard networks (Table III) and 3888x and 25.3x for the HyGCN networks (Table IV). The abstract numbers appear to be the average of the two benchmark-set averages, which is not a well-defined speedup statistic and makes the GPU figure look larger than either per-set result. Please report the per-set averages in the abstract and conclusion, or explain the aggregation. In addition, the CPU/GPU comparisons use PyG as the sole software baseline; the absolute speedups should be framed as being against PyG on these specific platforms, with the relevant configuration details (batch size, threads, model configuration) stated.
  3. [Section V.D, Table IV] The comparison with HyGCN uses a different network configuration (128 hidden channels) and averages over only the datasets for which HyGCN reports latency (Nell is marked NA). The comparison also contrasts a 330 MHz FPGA implementation with a 1 GHz 12 nm ASIC using fixed-point arithmetic. The paper notes the energy-efficiency limitation of the FPGA implementation but does not discuss how the clock and technology asymmetry affects the 5.1x performance claim. Please add a sensitivity discussion, normalize the comparison by frequency or technology, and explicitly state how many datasets are included in the reported average.
minor comments (6)
  1. [Section III.D] The 459 Gbps bandwidth requirement is reported as 'based on our experiments' without a formula or measurement description; please specify how this number is derived and whether it is a peak or average demand.
  2. [Section V.A] For Nell, the paper uses 2-hop and 3-hop distribution smoothing instead of the 1-hop and 2-hop settings used for the other datasets; this per-dataset configuration is a free parameter that should be reported in a sensitivity analysis or acknowledged as a limitation in the cross-dataset comparison.
  3. [Section IV.A and Fig. 12] The phrase 'sparsity < 75%' in the description of TDQ-1 is confusing because the paper elsewhere uses 'sparsity' to mean the fraction of zeros, while the design here stores the matrix in a dense format; please clarify the storage-format condition.
  4. [Section II.B and Table I] The introduction says Reddit has a '23K x 23K adjacency matrix' but Table I lists 232,965 nodes; please correct this typo.
  5. [Section IV.B] The text uses 'optimal balanced status' in Section IV, but the analysis only demonstrates near-optimal behavior; please use 'converged' or 'near-optimal' unless optimality is formally proven.
  6. [Figure 16] The caption states that hardware usage is 'normalized to the number of ALMs' while DSP slices are normalized to ALMs in the text; please describe this normalization in the caption or figure so that the area breakdown is unambiguous.

Circularity Check

0 steps flagged · score 2.0 of 10

No circularity found: the central utilization and speedup claims are direct measurements against external baselines; only minor, non-load-bearing self-citations are present.

full rationale

The paper's derivation chain is self-contained at the level that matters for circularity. The headline numbers (7.7x PE utilization, 3255x/80.3x/5.1x speedups) are measured end-to-end latencies and utilization counters from an Intel D5005 FPGA implementation, compared with the same AWB-GCN design without rebalancing, with PyG on CPU/GPU, with SCNN, and with HyGCN. No parameter is fitted to a subset of the data and then reported as a prediction: the autotuner switch fractions in Eqs. (5)-(6) are updated online from measured utilization gaps, and the utilization improvement is the directly observed difference between designs. The 459 Gbps off-chip bandwidth statement in Section III.D is an extrapolation from the measured designs, not a confirming test of the model. The self-citations in the paper ([5]-[10]) are prior CNN/BNN accelerator papers used as background; they do not justify the load-balancing mechanism or the speedup claims, so they are not load-bearing. The only potentially concerning passage is the convergence claim in Section IV.B: the text says the additive update is 'highly likely to converge to the optimal distribution' and that 'more details are omitted due to space limitations', and Section IV says 'After several rounds, the system converges to optimal balanced status; this is then used for the remainder of the computation.' As written, Eq. (6) is a sign-free additive recurrence, so the paper does not establish convergence analytically; this is a correctness/reproducibility gap, not a circularity. The FPGA measurements are direct evidence that the implemented controller worked for the five datasets, and no claim is defined in terms of the result it is supposed to establish. Hence no circular step is exhibited; the score reflects only minor, non-load-bearing self-citations.

Assumptions & free parameters 4 free parameters · 4 assumptions · 0 invented entities

The paper introduces no new physical or mathematical entities. The free parameters listed are architectural tunables, several of which are adjusted per dataset or left unspecified, and the axioms are standard GCN definitions plus domain assumptions about power-law graphs and static adjacency. The central empirical claim depends on the convergence and reuse assumption, which is not formally proved.

free parameters (4)
  • Hop distance for distribution smoothing = 1-hop and 2-hop for most datasets; 2-hop and 3-hop for Nell
    Section V.B states Nell is the only exception, indicating a per-workload tuning choice rather than a fixed design parameter.
  • Number of PE tuples for remote switching = 4 (customizable)
    Section IV.B says four tuples of the most over- and under-loaded PEs are selected each round; the number can be customized as an area/performance tradeoff.
  • Threshold granularity g for division approximation = not specified numerically
    Section IV.B uses a right-shift by g bits to approximate Gi/G1; g affects switch-fraction accuracy but its value is not given.
  • Evil row trigger threshold = not specified
    Row remapping is triggered when the utilization gap is 'too big for remote switching to handle'; the threshold is not quantified in the paper.
assumptions (4)
  • domain assumption Real-world graphs follow a power-law degree distribution.
    This motivates the entire rebalancing design and is stated in Section II.B; the five datasets are assumed representative of this distribution.
  • domain assumption The adjacency matrix A remains constant during GCN inference.
    Stated in Section II.A; required for the converged rebalancing strategy to be reused across all rounds.
  • domain assumption Column-wise-product SpMM is the right computation order for GCN.
    Adopted from cited works [41]-[43] and justified by profiling (Table II), but it is an architectural choice that the evaluation depends on.
  • standard math GCN layer propagation follows X^(l+1) = sigma(A X^l W^l).
    Standard GCN formulation from Kipf and Welling [29], used throughout the paper without further proof.

how reviews work

0 comments
Cite this review

Pith. "Pith review of AWB-GCN: A Graph Convolutional Network Accelerator with Runtime Workload Rebalancing." pith.science (2026). https://pith.science/paper/MZU4SVOT

@misc{pith2026190810834,
  author       = {Pith},
  title        = {Pith review of: AWB-GCN: A Graph Convolutional Network Accelerator with Runtime Workload Rebalancing},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/MZU4SVOT}},
  note         = {Machine review of arXiv:1908.10834}
}
read the original abstract

Deep learning systems have been successfully applied to Euclidean data such as images, video, and audio. In many applications, however, information and their relationships are better expressed with graphs. Graph Convolutional Networks (GCNs) appear to be a promising approach to efficiently learn from graph data structures, having shown advantages in many critical applications. As with other deep learning modalities, hardware acceleration is critical. The challenge is that real-world graphs are often extremely large and unbalanced; this poses significant performance demands and design challenges. In this paper, we propose Autotuning-Workload-Balancing GCN (AWB-GCN) to accelerate GCN inference. To address the issue of workload imbalance in processing real-world graphs, three hardware-based autotuning techniques are proposed: dynamic distribution smoothing, remote switching, and row remapping. In particular, AWB-GCN continuously monitors the sparse graph pattern, dynamically adjusts the workload distribution among a large number of processing elements (up to 4K PEs), and, after converging, reuses the ideal configuration. Evaluation is performed using an Intel D5005 FPGA with five commonly-used datasets. Results show that 4K-PE AWB-GCN can significantly elevate PE utilization by 7.7x on average and demonstrate considerable performance speedups over CPUs (3255x), GPUs (80.3x), and a prior GCN accelerator (5.1x).

Figures

Figures reproduced from arXiv: 1908.10834 by the authors.

Figure 1
Figure 1. Histograms show ordered non-zero per-row density. Left: Adjacency [PITH_FULL_IMAGE:figures/full_fig_p002_1.png] view at source ↗
Figure 2
Figure 2. Adjacency matrix of NELL following power-law distribution: elements [PITH_FULL_IMAGE:figures/full_fig_p002_2.png] view at source ↗
Figure 4
Figure 4. Illustration of a GCONV layer in GCNs. A is the graph adjacency matrix with each row delineating the connection of a vertex with all the other vertices in the graph. X (l) is the matrix of input features in layer-l; each column of X represents a feature while each row denotes a node. Wl is the weight matrix of layer-l. σ(.) denotes the non￾linear activation function, e.g., ReLU [1]. In general A needs to be normaliz… view at source ↗
Figures from the paper (11 more)
Figure 5
Figure 5. Figure 5: Non-zero distribution imbalance of Adjacency matrices in Cora, Citeseer, Pubmed, Nell and Reddit datasets. [PITH_FULL_IMAGE:figures/full_fig_p004_5.png]
Figure 6
Figure 6. Figure 6: (A) SpMM computation order: Column-wise-product; (B) Matrix [PITH_FULL_IMAGE:figures/full_fig_p004_6.png]
Figure 7
Figure 7. Figure 7: Architecture of the proposed baseline SpMM engine. [PITH_FULL_IMAGE:figures/full_fig_p005_7.png]
Figure 8
Figure 8. Figure 8: Pipelined SpMMs: data production and consumption rates match [PITH_FULL_IMAGE:figures/full_fig_p006_8.png]
Figure 12
Figure 12. Figure 12: Simplified architecture of distribution smoothing. [PITH_FULL_IMAGE:figures/full_fig_p007_12.png]
Figure 13
Figure 13. Figure 13: Overall architecture of SpMM engine in AWB-GCN with three rebalancing techniques: distribution smoothing, remote switching (red bordered) and [PITH_FULL_IMAGE:figures/full_fig_p009_13.png]
Figure 14
Figure 14. Figure 14: Overall performance and PE utilization of 1K-PE AWB-GCN with five design choices. [PITH_FULL_IMAGE:figures/full_fig_p010_14.png]
Figure 15
Figure 15. Figure 15: Per-SpMM performance and PE utilization of 1K-PE AWB-GCN with five design choices. [PITH_FULL_IMAGE:figures/full_fig_p010_15.png]
Figure 16
Figure 16. Figure 16: (A) Hardware resource consumption normalized to the number of [PITH_FULL_IMAGE:figures/full_fig_p010_16.png]
Figure 17
Figure 17. Figure 17: AWB-GCN PE (1K) average utilization per round of workload autotuning. [PITH_FULL_IMAGE:figures/full_fig_p011_17.png]
Figure 18
Figure 18. Figure 18: Scalability evaluation: PE utilization and overall performance of Baseline, Design(B) and Design(D) of AWB-GCNs with 512, 1K, 2K and 4K PEs. [PITH_FULL_IMAGE:figures/full_fig_p011_18.png]

Discussion (0). Continue with ORCID to comment.

Reference graph

Works this paper leans on

69 extracted references · 52 canonical work pages

  1. [1]

    Imagenet classification with deep convolutional neural networks,

    A. Krizhevsky, I. Sutskever, and G. E. Hinton, “Imagenet classification with deep convolutional neural networks,” in Advances in neural infor- mation processing systems , pp. 1097–1105, 2012

    2012

  2. [2]

    Recurrent neural network based language model,

    T. Mikolov, M. Karafi ´at, L. Burget, J. ˇCernock`y, and S. Khudanpur, “Recurrent neural network based language model,” in The 11st Annual Conference of the International Speech Communication Association , 2010

    work page 2010

  3. [3]

    Understanding reuse, performance, and hardware cost of dnn dataflow: A data-centric approach,

    H. Kwon, P. Chatarasi, M. Pellauer, A. Parashar, V . Sarkar, and T. Kr- ishna, “Understanding reuse, performance, and hardware cost of dnn dataflow: A data-centric approach,” in Proceedings of the 52nd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO) , pp. 754–768, 2019

    work page 2019

  4. [4]

    MAESTRO: A data-centric approach to understand reuse, performance, and hardware cost of dnn mappings,

    H. Kwon, P. Chatarasi, V . Sarkar, T. Krishna, M. Pellauer, and A. Parashar, “MAESTRO: A data-centric approach to understand reuse, performance, and hardware cost of dnn mappings,” IEEE Micro, vol. 40, no. 3, pp. 20–29, 2020

    work page 2020

  5. [5]

    O3BNN: An out-of-order architecture for high-performance binarized neural network inference with fine-grained pruning,

    T. Geng, T. Wang, C. Wu, C. Yang, W. Wu, A. Li, and M. Herbordt, “O3BNN: An out-of-order architecture for high-performance binarized neural network inference with fine-grained pruning,” in ACM Interna- tional Conference on Supercomputing (ICS) , vol. 2160, pp. 461–472,

    work page

  6. [6]

    FPDeep: Acceleration and load balancing of CNN training on FPGA clusters,

    T. Geng, T. Wang, A. Sanaullah, C. Yang, R. Xuy, R. Patel, and M. Her- bordt, “FPDeep: Acceleration and load balancing of CNN training on FPGA clusters,” in 2018 IEEE 26th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM) , p. 8184,

    work page 2018

  7. [7]

    BSTC: A novel binarized-soft-tensor-core design for accelerating bit- based approximated neural nets,

    A. Li, T. Geng, T. Wang, M. Herbordt, S. Song, and K. Barker, “BSTC: A novel binarized-soft-tensor-core design for accelerating bit- based approximated neural nets,” in International Conference for High Performance Computing, Networking, Storage and Analysis (SC) , 2019. doi: 10.1145/ 3295500.3356169

    arXiv 2019

  8. [8]

    A comprehensive survey on graph neural networks,

    Z. Wu, S. Pan, F. Chen, G. Long, C. Zhang, and S. Y . Philip, “A comprehensive survey on graph neural networks,” IEEE Transactions on Neural Networks and Learning Systems , 2020

    2020

Show all 69 references
  1. [9]

    FPDeep: Scalable acceleration of CNN training on deeply-pipelined FPGA clusters,

    T. Wang, T.Geng, A. Li, X. Jin, and M. Herbordt, “FPDeep: Scalable acceleration of CNN training on deeply-pipelined FPGA clusters,” IEEE Transactions on Computers, vol. C-69, no. 8, pp. 1143–1158, 2020. doi: 10.1109/TC.2020.3000118

    2020

  2. [10]

    O3BNN-R: An out-of-order architecture for high-performance and regularized BNN inference,

    T. Geng, T. Wang, C. Wu, Y . Li, C. Yang, W. Wu, A. Li, and M. Her- bordt, “O3BNN-R: An out-of-order architecture for high-performance and regularized BNN inference,” IEEE Transactions on Parallel and Distributed Systems, 2021. doi: 10.1109/TPDS.2020.3013637. 14

    2021

  3. [11]

    Pow- erGraph: Distributed graph-parallel computation on natural graphs,

    J. E. Gonzalez, Y . Low, H. Gu, D. Bickson, and C. Guestrin, “Pow- erGraph: Distributed graph-parallel computation on natural graphs,” in Presented as part of the 10th USENIX Symposium on Operating Systems Design and Implementation (OSDI) , pp. 17–30, 2012

    2012

  4. [12]

    Multilevel algorithms for partitioning power-law graphs,

    A. Abou-Rjeili and G. Karypis, “Multilevel algorithms for partitioning power-law graphs,” in Proceedings 20th IEEE International Parallel & Distributed Processing Symposium (IPDPS) , pp. 10–pp, IEEE, 2006

    2006

  5. [13]

    Main-memory triangle computations for very large (sparse (power-law)) graphs,

    M. Latapy, “Main-memory triangle computations for very large (sparse (power-law)) graphs,” Theoretical Computer Science , vol. 407, no. 1-3, pp. 458–473, 2008

    2008

  6. [14]

    Distributed power-law graph computing: Theoretical and empirical analysis,

    C. Xie, L. Yan, W.-J. Li, and Z. Zhang, “Distributed power-law graph computing: Theoretical and empirical analysis,” in Advances in Neural Information Processing Systems , pp. 1673–1681, 2014

    2014

  7. [15]

    A random graph model for power law graphs,

    W. Aiello, F. Chung, and L. Lu, “A random graph model for power law graphs,” Experimental Mathematics, vol. 10, no. 1, pp. 53–66, 2001

    2001

  8. [16]

    The spectra of random graphs with given expected degrees,

    F. Chung, L. Lu, and V . Vu, “The spectra of random graphs with given expected degrees,” Internet Mathematics , vol. 1, no. 3, pp. 257–275, 2004

    2004

  9. [17]

    Search in power-law networks,

    L. A. Adamic, R. M. Lukose, A. R. Puniyani, and B. A. Huberman, “Search in power-law networks,” Physical Review E , vol. 64, no. 4, p. 046135, 2001

    2001

  10. [18]

    A new model for learning in graph domains,

    M. Gori, G. Monfardini, and F. Scarselli, “A new model for learning in graph domains,” in Proceedings. 2005 IEEE International Joint Conference on Neural Networks, 2005., vol. 2, pp. 729–734, IEEE, 2005

    2005

  11. [19]

    Neural network for graphs: A contextual constructive approach,

    A. Micheli, “Neural network for graphs: A contextual constructive approach,” IEEE Transactions on Neural Networks , vol. 20, no. 3, pp. 498–511, 2009

    2009

  12. [20]

    The graph neural network model,

    F. Scarselli, M. Gori, A. C. Tsoi, M. Hagenbuchner, and G. Monfardini, “The graph neural network model,” IEEE Transactions on Neural Networks, vol. 20, no. 1, pp. 61–80, 2008

    2008

  13. [21]

    Gated graph sequence neural networks,

    Y . Li, D. Tarlow, M. Brockschmidt, and R. Zemel, “Gated graph sequence neural networks,” arXiv:1511.05493, 2015

    2015 arXiv

  14. [22]

    Learning steady- states of iterative algorithms over graphs,

    H. Dai, Z. Kozareva, B. Dai, A. Smola, and L. Song, “Learning steady- states of iterative algorithms over graphs,” in International Conference on Machine Learning , pp. 1114–1122, 2018

    2018

  15. [23]

    GraphRNN: A deep generative model for graphs,

    J. You, R. Ying, X. Ren, W. L. Hamilton, and J. Leskovec, “GraphRNN: A deep generative model for graphs,” arXiv:1802.08773, 2018

    2018 arXiv

  16. [24]

    Watch your step: Learning node embeddings via graph attention,

    S. Abu-El-Haija, B. Perozzi, R. Al-Rfou, and A. A. Alemi, “Watch your step: Learning node embeddings via graph attention,” in Advances in Neural Information Processing Systems , pp. 9180–9190, 2018

    2018

  17. [25]

    Large-scale learnable graph convolutional networks,

    H. Gao, Z. Wang, and S. Ji, “Large-scale learnable graph convolutional networks,” in Proceedings of the 24th ACM SIGKDD International Conference on Knowledge Discovery & Data Mining , pp. 1416–1424, ACM, 2018

    2018

  18. [26]

    Deep convolutional networks on graph-structured data,

    M. Henaff, J. Bruna, and Y . LeCun, “Deep convolutional networks on graph-structured data,” arXiv:1506.05163, 2015

    2015 arXiv

  19. [27]

    Spectral networks and locally connected networks on graphs,

    J. Bruna, W. Zaremba, A. Szlam, and Y . LeCun, “Spectral networks and locally connected networks on graphs,” arXiv:1312.6203, 2013

    2013 arXiv

  20. [28]

    Convolutional neural networks on graphs with fast localized spectral filtering,

    M. Defferrard, X. Bresson, and P. Vandergheynst, “Convolutional neural networks on graphs with fast localized spectral filtering,” in Advances in neural information processing systems , pp. 3844–3852, 2016

    2016

  21. [29]

    Semi-supervised classification with graph convolutional networks,

    T. N. Kipf and M. Welling, “Semi-supervised classification with graph convolutional networks,” arXiv:1609.02907, 2016

    2016 arXiv

  22. [30]

    Graph transformer networks,

    S. Yun, M. Jeong, R. Kim, J. Kang, and H. J. Kim, “Graph transformer networks,” in Advances in Neural Information Processing Systems , pp. 11960–11970, 2019

    2019

  23. [31]

    HyGCN: A GCN accelerator with hybrid architecture,

    M. Yan, L. Deng, X. Hu, L. Liang, Y . Feng, X. Ye, Z. Zhang, D. Fan, and Y . Xie, “HyGCN: A GCN accelerator with hybrid architecture,” in 2020 IEEE International Symposium on High Performance Computer Architecture (HPCA), pp. 15–29, IEEE, 2020

    2020

  24. [32]

    Guiding cascading failure search with interpretable graph convolutional network,

    Y . Liu, N. Zhang, D. Wu, A. Botterud, R. Yao, and C. Kang, “Guiding cascading failure search with interpretable graph convolutional network,” arXiv:2001.11553, 2020

    2001 arXiv

  25. [33]

    A graph-convolutional neural network model for the prediction of chemical reactivity,

    C. W. Coley, W. Jin, L. Rogers, T. F. Jamison, T. S. Jaakkola, W. H. Green, R. Barzilay, and K. F. Jensen, “A graph-convolutional neural network model for the prediction of chemical reactivity,” Chemical Science, vol. 10, no. 2, pp. 370–377, 2019

    2019

  26. [34]

    Crystal graph convolutional neural networks for an accurate and interpretable prediction of material properties,

    T. Xie and J. C. Grossman, “Crystal graph convolutional neural networks for an accurate and interpretable prediction of material properties,” Physical Review Letters , vol. 120, no. 14, p. 145301, 2018

    2018

  27. [35]

    Modeling polypharmacy side effects with graph convolutional networks,

    M. Zitnik, M. Agrawal, and J. Leskovec, “Modeling polypharmacy side effects with graph convolutional networks,” Bioinformatics, vol. 34, no. 13, pp. i457–i466, 2018

    2018

  28. [36]

    AliGraph: A comprehensive graph neural network platform,

    H. Yang, “AliGraph: A comprehensive graph neural network platform,” in Proceedings of the 25th ACM SIGKDD International Conference on Knowledge Discovery & Data Mining , pp. 3165–3166, ACM, 2019

    2019

  29. [37]

    IoT botnet detection approach based on PSI graph and DGCNN classifier,

    H.-T. Nguyen, Q.-D. Ngo, and V .-H. Le, “IoT botnet detection approach based on PSI graph and DGCNN classifier,” in 2018 IEEE International Conference on Information Communication and Signal Processing (ICI- CSP), pp. 118–122, IEEE, 2018

    2018

  30. [38]

    EIE: efficient inference engine on compressed deep neural network,

    S. Han, X. Liu, H. Mao, J. Pu, A. Pedram, M. A. Horowitz, and W. J. Dally, “EIE: efficient inference engine on compressed deep neural network,” in 2016 ACM/IEEE 43rd Annual International Symposium on Computer Architecture (ISCA), pp. 243–254, IEEE, 2016

    2016

  31. [39]

    Cambricon-X: An accelerator for sparse neural networks,

    S. Zhang, Z. Du, L. Zhang, H. Lan, S. Liu, L. Li, Q. Guo, T. Chen, and Y . Chen, “Cambricon-X: An accelerator for sparse neural networks,” in The 49th Annual IEEE/ACM International Symposium on Microarchi- tecture (MICRO), p. 20, IEEE Press, 2016

    2016

  32. [40]

    A novel zero weight/activation-aware hardware architecture of convolutional neural network,

    D. Kim, J. Ahn, and S. Yoo, “A novel zero weight/activation-aware hardware architecture of convolutional neural network,” in Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017 , pp. 1462–1467, IEEE, 2017

    2017

  33. [41]

    A systematic survey of general sparse matrix-matrix multiplication,

    J. Gao, W. Ji, Z. Tan, and Y . Zhao, “A systematic survey of general sparse matrix-matrix multiplication,” arXiv:2002.11273, 2020

    2002 arXiv

  34. [42]

    Performance-portable sparse matrix-matrix multiplication for many-core architectures,

    M. Deveci, C. Trott, and S. Rajamanickam, “Performance-portable sparse matrix-matrix multiplication for many-core architectures,” in 2017 IEEE International Parallel and Distributed Processing Sympo- sium Workshops (IPDPSW), pp. 693–702, IEEE, 2017

    2017

  35. [43]

    Performance-aware model for sparse matrix-matrix multiplication on the sunway taihulight supercomputer,

    Y . Chen, K. Li, W. Yang, G. Xiao, X. Xie, and T. Li, “Performance-aware model for sparse matrix-matrix multiplication on the sunway taihulight supercomputer,”IEEE Transactions on Parallel and Distributed Systems, vol. 30, no. 4, pp. 923–938, 2018

    2018

  36. [44]

    Fast graph representation learning with PyTorch geometric,

    M. Fey and J. E. Lenssen, “Fast graph representation learning with PyTorch geometric,” arXiv:1903.02428, 2019

    1903 arXiv

  37. [45]

    SCNN: An accelerator for compressed-sparse convolutional neural networks,

    A. Parashar, M. Rhu, A. Mukkara, A. Puglielli, R. Venkatesan, B. Khailany, J. Emer, S. W. Keckler, and W. J. Dally, “SCNN: An accelerator for compressed-sparse convolutional neural networks,” in 2017 ACM/IEEE 44th Annual International Symposium on Computer Architecture (ISCA),...

    2017

  38. [46]

    Dual graph convolutional networks for graph- based semi-supervised classification,

    C. Zhuang and Q. Ma, “Dual graph convolutional networks for graph- based semi-supervised classification,” in Proceedings of the 2018 World Wide Web Conference, pp. 499–508, 2018

    2018

  39. [47]

    Stochastic training of graph convolutional networks with variance reduction,

    J. Chen, J. Zhu, and L. Song, “Stochastic training of graph convolutional networks with variance reduction,” arXiv:1710.10568, 2017

    2017 arXiv

  40. [48]

    Measuring the gap between FPGAs and ASICs,

    I. Kuon and J. Rose, “Measuring the gap between FPGAs and ASICs,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 26, no. 2, pp. 203–215, 2007

    2007

  41. [49]

    Cnvlutin: Ineffectual-neuron-free deep neural network computing,

    J. Albericio, P. Judd, T. Hetherington, T. Aamodt, N. E. Jerger, and A. Moshovos, “Cnvlutin: Ineffectual-neuron-free deep neural network computing,” ACM SIGARCH Computer Architecture News , vol. 44, no. 3, pp. 1–13, 2016

    2016

  42. [50]

    Packing sparse convolutional neural networks for efficient systolic array implementations: Column combining under joint optimization,

    H. Kung, B. McDanel, and S. Q. Zhang, “Packing sparse convolutional neural networks for efficient systolic array implementations: Column combining under joint optimization,” in Proceedings of the Twenty- Fourth International Conference on Architectural Support for Program- ming...

    2019

  43. [51]

    Eyeriss: An energy- efficient reconfigurable accelerator for deep convolutional neural net- works,

    Y .-H. Chen, T. Krishna, J. S. Emer, and V . Sze, “Eyeriss: An energy- efficient reconfigurable accelerator for deep convolutional neural net- works,” IEEE Journal of Solid-State Circuits , vol. 52, no. 1, pp. 127– 138, 2016

    2016

  44. [52]

    CirCNN: accelerating and compressing deep neural networks using block-circulant weight matrices,

    C. Ding, S. Liao, Y . Wang, Z. Li, N. Liu, Y . Zhuo, C. Wang, X. Qian, Y . Bai, G. Yuan, et al. , “CirCNN: accelerating and compressing deep neural networks using block-circulant weight matrices,” in Proceedings of the 50th Annual IEEE/ACM International Symposium on Microarchi...

    2017

  45. [53]

    Sparse matrix-vector multiplication on fpgas,

    L. Zhuo and V . K. Prasanna, “Sparse matrix-vector multiplication on fpgas,” in Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field-programmable gate arrays, pp. 63–74, ACM, 2005

    2005

  46. [54]

    OuterSPACE: An outer product based sparse matrix multiplication accelerator,

    S. Pal, J. Beaumont, D.-H. Park, A. Amarnath, S. Feng, C. Chakrabarti, H.-S. Kim, D. Blaauw, T. Mudge, and R. Dreslinski, “OuterSPACE: An outer product based sparse matrix multiplication accelerator,” in 2018 IEEE International Symposium on High Performance Computer Architectu...

    2018

  47. [55]

    SIGMA: A sparse and irregular gemm accelerator with flexible interconnects for dnn training,

    E. Qin, A. Samajdar, H. Kwon, V . Nadella, S. Srinivasan, D. Das, B. Kaul, and T. Krishna, “SIGMA: A sparse and irregular gemm accelerator with flexible interconnects for dnn training,” in 2020 IEEE 15 International Symposium on High Performance Computer Architecture (HPCA), pp...

    2020

  48. [56]

    ALRESCHA: A lightweight reconfigurable sparse-computation accel- erator,

    B. Asgari, R. Hadidi, T. Krishna, H. Kim, and S. Yalamanchili, “ALRESCHA: A lightweight reconfigurable sparse-computation accel- erator,” in 2020 IEEE International Symposium on High Performance Computer Architecture (HPCA), pp. 249–260, IEEE, 2020

    2020

  49. [57]

    GraphR: Accelerating graph processing using ReRAM,

    L. Song, Y . Zhuo, X. Qian, H. Li, and Y . Chen, “GraphR: Accelerating graph processing using ReRAM,” in 2018 IEEE International Sympo- sium on High Performance Computer Architecture (HPCA) , pp. 531– 543, IEEE, 2018

    2018

  50. [58]

    GraphP: Reducing communication for pim-based graph processing with efficient data partition,

    M. Zhang, Y . Zhuo, C. Wang, M. Gao, Y . Wu, K. Chen, C. Kozyrakis, and X. Qian, “GraphP: Reducing communication for pim-based graph processing with efficient data partition,” in 2018 IEEE International Symposium on High Performance Computer Architecture (HPCA) , pp. 544–557, I...

    2018

  51. [59]

    Graphi- cionado: A high-performance and energy-efficient accelerator for graph analytics,

    T. J. Ham, L. Wu, N. Sundaram, N. Satish, and M. Martonosi, “Graphi- cionado: A high-performance and energy-efficient accelerator for graph analytics,” in 2016 49th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO), pp. 1–13, IEEE, 2016

    2016

  52. [60]

    Energy efficient architecture for graph analytics acceler- ators,

    M. M. Ozdal, S. Yesil, T. Kim, A. Ayupov, J. Greth, S. Burns, and O. Ozturk, “Energy efficient architecture for graph analytics acceler- ators,” ACM SIGARCH Computer Architecture News , vol. 44, no. 3, pp. 166–177, 2016

    2016

  53. [61]

    Efficient sparse matrix-vector multipli- cation on GPUs using the CSR storage format,

    J. L. Greathouse and M. Daga, “Efficient sparse matrix-vector multipli- cation on GPUs using the CSR storage format,” in Proceedings of the International Conference for High Performance Computing, Networking, Storage and Analysis (SC) , pp. 769–780, 2014

    2014

  54. [62]

    An efficient GPU general sparse matrix-matrix multiplication for irregular data,

    W. Liu and B. Vinter, “An efficient GPU general sparse matrix-matrix multiplication for irregular data,” in 2014 IEEE 28th International Parallel and Distributed Processing Symposium (IPDPS) , pp. 370–381, IEEE, 2014

    2014

  55. [63]

    Fast sparse matrix-vector multiplication on GPUs for graph appli- cations,

    A. Ashari, N. Sedaghati, J. Eisenlohr, S. Parthasarathy, and P. Sadayap- pan, “Fast sparse matrix-vector multiplication on GPUs for graph appli- cations,” inProceedings of the International Conference for High Perfor- mance Computing, Networking, Storage and Analysis (SC), pp....

    2014

  56. [64]

    Efficient sparse matrix-vector multiplication on CUDA,

    N. Bell and M. Garland, “Efficient sparse matrix-vector multiplication on CUDA,” tech. rep., Nvidia Technical Report NVR-2008-004, Nvidia Corporation, 2008

    2008

  57. [65]

    Implementing sparse matrix-vector mul- tiplication on throughput-oriented processors,

    N. Bell and M. Garland, “Implementing sparse matrix-vector mul- tiplication on throughput-oriented processors,” in Proceedings of the International Conference for High Performance Computing, Networking, Storage and Analysis (SC) , p. 18, ACM, 2009

    2009

  58. [66]

    Inductive representation learning on large graphs,

    W. Hamilton, Z. Ying, and J. Leskovec, “Inductive representation learning on large graphs,” in Advances in Neural Information Processing Systems, pp. 1024–1034, 2017

    2017

  59. [67]

    How powerful are graph neural networks?,

    K. Xu, W. Hu, J. Leskovec, and S. Jegelka, “How powerful are graph neural networks?,” arXiv:1810.00826, 2018. 16

    2018 arXiv

  60. [2018]

    doi: 10.1109/ FCCM.2018. 00021

    2018

  61. [2019]

    doi: 10.1145/ 3330345. 3330386

Pith tools

Reviewed August 14, 2026 · model on record in the stance chip above.