REVIEW 7 cited by
SpecLLM: Exploring Generation and Review of VLSI Design Specification with Large Language Model
Not yet reviewed by Pith; the record is open.
This paper has not been read by Pith yet. Machine review is queued; the pith claim, tier, and objections will appear here once it completes.
SPECIMEN: schema-true, not a live event
T0 review · schema-true
One-sentence machine reading of the paper's core claim.
pith:XXXXXXXX · record.json · timestamp
read the original abstract
The development of architecture specifications is an initial and fundamental stage of the integrated circuit (IC) design process. Traditionally, architecture specifications are crafted by experienced chip architects, a process that is not only time-consuming but also error-prone. Mistakes in these specifications may significantly affect subsequent stages of chip design. Despite the presence of advanced electronic design automation (EDA) tools, effective solutions to these specification-related challenges remain scarce. Since writing architecture specifications is naturally a natural language processing (NLP) task, this paper pioneers the automation of architecture specification development with the advanced capabilities of large language models (LLMs). Leveraging our definition and dataset, we explore the application of LLMs in two key aspects of architecture specification development: (1) Generating architecture specifications, which includes both writing specifications from scratch and converting RTL code into detailed specifications. (2) Reviewing existing architecture specifications. We got promising results indicating that LLMs may revolutionize how these critical specification documents are developed in IC design nowadays. By reducing the effort required, LLMs open up new possibilities for efficiency and accuracy in this crucial aspect of chip design.
Forward citations
Cited by 7 Pith papers
-
DiffAxE: Diffusion-driven Hardware Accelerator Generation and Design Space Exploration
DiffAxE uses conditional diffusion models to generate hardware accelerator designs directly from target performance, achieving orders-of-magnitude faster design space exploration with lower error than existing optimiz...
-
RealBench: Benchmarking Verilog Generation Models with Real-World IP Designs
RealBench measures LLM Verilog generation on complex open-source IP cores with formal verification, and all tested models score near zero on full system designs.
-
Automated HEMT Model Construction from Datasheets via Multi-Modal Intelligence and Prior-Knowledge-Free Optimization
An AI pipeline combining document parsing, curve digitization, and an iterative Bayesian optimizer converts PDF datasheets into ASM-HEMT SPICE models automatically, with reported fitting errors of 1.2 to 4.9 percent o...
-
Leveraging LLMs for Formal Software Requirements -- Challenges and Prospects
LLM-based formalisation of software requirements is promising but faces five persistent challenges; the proposed VERIFAI framework plans to address them with human-in-the-loop and tool-neutral pipelines.
-
Large Language Models (LLMs) for Electronic Design Automation (EDA)
A review of LLM applications in EDA, summarizing prior work and three case studies on hardware design, testing, and optimization.
-
A Short Survey on Formalising Software Requirements using Large Language Models
A survey summarizing 35 papers on using LLMs to formalize software requirements, but it contains no new experimental results and its classification tables have errors.
-
Formalising Software Requirements using Large Language Models
A short project-position paper describing VERIFAI, a planned system for automatic formalisation and traceability of natural language requirements, with no experimental results yet.
Discussion (0). Sign in to comment.