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arxiv: 2406.07318 · v3 · pith:O5PYO5H3new · submitted 2024-06-11 · 💻 cs.CV · cs.AR· eess.IV

Embedded Graph Convolutional Networks for Real-Time Event Data Processing on SoC FPGAs

classification 💻 cs.CV cs.AReess.IV
keywords eventgraphprocessingclassificationconvolutionalevent-basedlatencyreal-time
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The utilisation of event cameras represents an important and swiftly evolving trend aimed at addressing the constraints of traditional video systems. Particularly within the automotive domain, these cameras find significant relevance for their integration into embedded real-time systems due to lower latency and power consumption. One effective approach to ensure the necessary throughput and latency for event processing is through the utilisation of graph convolutional networks (GCNs). In this study, we introduce a custom EFGCN (Event-based FPGA-accelerated Graph Convolutional Network) designed with a series of hardware-aware optimisations tailored for PointNetConv,a graph convolution designed for point cloud processing. The proposed techniques result in up to 100-fold reduction in model size compared to Asynchronous Event-based GNN (AEGNN), one of the most recent works in the field, with a relatively small decrease in accuracy (2.9% for the N-Caltech101 classification task, 2.2% for the N-Cars classification task), thus following the TinyML trend. We implemented EFGCN on a ZCU104 SoC FPGA platform without any off-chip external memory resources, achieving a throughput of 13.3 million events per second (MEPS) and real-time partially asynchronous processing with low latency. Across multiple event-based classification benchmarks, our approach achieves competitive accuracy while providing state-of-the-art computational efficiency per event, small model size, and high scalability, customisability and resource efficiency. We publish both software and hardware source code in an open repository: https://github.com/vision-agh/gcnn-dvs-fpga.

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  1. Hardware-Accelerated Event-Graph Neural Networks for Low-Latency Time-Series Classification on SoC FPGA

    cs.LG 2025-03 unverdicted novelty 5.0

    FPGA hardware for event-graph NN achieves 92.7% accuracy on SHD dataset with fewer parameters than SOTA while outperforming prior FPGA SNNs.