Pith. sign in

REVIEW 2 major objections 6 minor 27 references

A two-stage spiking neural network pipeline reduces ePIC dRICH data by at least five times while keeping more than 94 percent of real Cherenkov signals across the full dark-count range.

Reviewed by Pith at T0; open to challenge. T0 means a machine referee read the full paper against a public rubric. the ladder, T0–T4 →

Challenge this review Re-run · record.json Download PDF Read on arXiv ↗

T0 review · grok-4.5

2026-07-12 02:06 UTC pith:ONQSECI5

load-bearing objection Solid first end-to-end SNN data-reduction pipeline for a real HEP detector: software targets met on simulation, honest 1.7 MHz FPGA sub-sector demo, ~60 imes gap to 100 MHz still open. the 2 major comments →

arxiv 2607.03492 v1 pith:ONQSECI5 submitted 2026-07-03 physics.ins-det

Online Data Reduction with Spiking Neural Networks: A Temporal-Coincidence Encoder and Distributed SNN for the ePIC dRICH Detector

Pierpaolo Perticaroli , Roberto Ammendola , Andrea Biagioni , Ottorino Frezza , Francesca Lo Cicero , Michele Martinelli , Pier Stanislao Paolucci , Elena Pastorelli
show 5 more authors
Luca Pontisso Cristian Rossi Francesco Simula Piero Vicini Alessandro Lonardo
This is my paper
classification physics.ins-det
keywords spiking neural networksonline data reductionRing Imaging CherenkovSiPMtemporal coincidenceneuromorphic computingePICElectron-Ion Collider
verification ladder T0 review T1 audit T2 compute T3 formal T4 reserved

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The ePIC dRICH detector will read out roughly 320,000 SiPM channels at 100 MHz, but rising dark counts threaten to overwhelm the available bandwidth, so at least a five-fold online reduction is required. This paper shows that the problem is fundamentally temporal: genuine Cherenkov hits cluster inside about 2 ns while dark counts are uniform across the 10 ns crossing. A per-photodetection-unit leaky-integrate-and-fire encoder first turns raw hits into a sparse spike stream, discarding more than 90 percent of the data before any learned network runs. A distributed spiking classifier then labels each crossing Noise-Only or Signal+Noise, reaching true-positive rate above 94 percent at true-negative rate of at least 80 percent on simulated events. A single-sub-sector FPGA prototype already runs at 1.7 MHz, with a clear optimization path toward the full 100 MHz rate, offering a practical template for other high-rate timing detectors.

Core claim

On simulated ePIC events a two-stage pipeline—per-photodetection-unit LIF temporal-coincidence encoder plus a distributed two-tier SNN classifier mapped onto the existing DAM and Trigger Processor FPGAs—classifies each bunch crossing as Noise-Only or Signal+Noise with true-positive rate above 94 percent and true-negative rate at least 80 percent across dark-count rates from 25 to 300 kHz, thereby meeting the online reduction factor of five required to stay inside the detector’s egress bandwidth.

What carries the argument

The LIF temporal-coincidence encoder: one leaky-integrate-and-fire neuron per 256-channel photodetection unit that integrates hits with uniform weights and emits at most one spike per bunch crossing. It exploits the ~2 ns Cherenkov burst against uniform dark noise, achieving >90 percent sparsification before the learned classifier sees any data.

Load-bearing premise

The simulated timing structure—Cherenkov photons tightly clustered within about 2 ns while dark counts are uniform—and the injected dark-count model remain faithful enough to real irradiated SiPMs and beam backgrounds that the chosen encoder settings and trained classifier will still hit their performance targets on actual detector data.

What would settle it

Deploy the identical encoder-plus-classifier pipeline on real beam-test or early-commissioning data from irradiated SiPM arrays at known dark-count and background rates; if true-positive rate drops below roughly 90 percent or true-negative rate below 80 percent at 300 kHz dark count, the claim that the method meets the online reduction requirement is falsified.

Watch this falsifier — get emailed when new claim-graph text bears on it.

If this is right

  • The required ≥5× online data reduction is achievable while preserving >94 percent of signal crossings across the full operational dark-count range.
  • Early-exit inference reduces average classification latency to about 2 algorithmic timesteps with only a few-point loss in accuracy metrics.
  • A single-sub-sector FPGA implementation already sustains ~1.7 MHz throughput at under 2 percent resource utilization, leaving headroom for the rest of the DAM firmware.
  • Few-bit fixed-point quantization (down to 4 bits) preserves classification performance, keeping per-neuron hardware cost low.
  • The same encoder-plus-distributed-SNN pattern may transfer to other high-rate timing detectors whose signal is carried by fine temporal structure against uncorrelated noise.

Where Pith is reading between the lines

These are editorial extensions of the paper, not claims the author makes directly.

  • Because the chosen encoder operating point is essentially a same-bin coincidence detector, simpler non-neural digital logic might deliver comparable front-end sparsification; the residual gain of the learned SNN classifier can then be measured in isolation.
  • Evolving the inference fabric from timestep-driven to fully event-driven execution is likely the decisive step needed to close the remaining gap from 1.7 MHz to the full 100 MHz bunch-crossing rate.
  • Placing the LIF encoder closer to the front-end ASICs could cut optical-link traffic even earlier in the readout chain, an option the paper notes but does not quantify.
  • The same temporal-coincidence principle could serve as a first-stage filter for other SiPM- or MCP-PMT-based RICH and TOF systems at future colliders facing similar dark-count pressure.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit.

Referee Report

2 major / 6 minor

Summary. The manuscript presents a two-stage online data-reduction pipeline for the ePIC dRICH detector based on spiking neural networks. Stage 1 is a per-PDU LIF temporal-coincidence encoder (uniform weights, single-spike-per-BC) that exploits the ~2 ns clustering of Cherenkov hits against uniform DCR to achieve >90% sparsification. Stage 2 is a distributed two-tier SNN (30 Sub-sector networks of 42 o16 o4 LIF neurons plus an Aggregation network) that classifies each 10 ns bunch crossing as Noise-Only or Signal+Noise. On a balanced 80 k-event simulated sample spanning DCR = 25–300 kHz the system reports TPR >94% at TNR ≥80%; early-exit reduces average latency to ~2 timesteps. A single-sub-sector FPGA testbed on Versal Premium integrating the encoder with AIGOR measures ~1.7 MHz throughput, with an explicit optimization path toward the 100 MHz BC rate.

Significance. If the reported TPR/TNR hold under realistic irradiated-SiPM and beam-background conditions, the work supplies a concrete, hardware-matched template for SNN-based online reduction in a high-rate HEP DAQ: a transparent temporal filter that itself delivers most of the sparsification, a topology that mirrors the existing FELIX-155 sectorization, and a measured single-sub-sector proof-of-concept rather than a pure software study. The Pareto scan over encoder hyperparameters, the fixed-point robustness down to Q2.2, and the explicit acknowledgment of the remaining ~60× throughput gap are strengths that make the result usable by other timing-driven detector groups. The concurrent AIGOR architecture paper is appropriately cited as companion work.

major comments (2)
  1. Sections 2.3–2.4 and 5 (Figs. 1, 6, 7): the central claim that the chosen operating point (1.27 ns bin, θ=2, k=1) plus trained classifier will deliver TPR>94%/TNR≥80% on the real detector rests on the fidelity of the simulated ~2 ns Cherenkov clustering and uniform DCR model. The paper should either (a) quantify residual timing-structure mismatch against available irradiated-SiPM or beam-test data, or (b) state clearly that the performance numbers are simulation-only and that a validation campaign on real data is required before claiming readiness for the ePIC DAQ. Without one of these, the load-bearing transfer claim remains untested.
  2. Section 6.4 and Table 1: the measured ~1.7 MHz is for a single Sub-sector pipeline on a synthetic/semi-realistic trace; the Aggregation SNN, inter-FPGA AER transport of the 30×4 feature vectors, and GTU round-trip are not exercised. The manuscript should bound the additional latency and bandwidth cost of the full 30-DAM + TP system (or mark the 100 MHz target as contingent on those unmeasured stages) so that the system-level reduction claim is not overstated by the single-sub-sector result.
minor comments (6)
  1. Section 5.1: state the absolute numbers of Signal+Noise and Noise-Only events retained after zero-hit removal and the exact train/val/test counts, not only the 80/10/10 percentages.
  2. Figure 5: the percentage annotations for empty crossings are useful; add a short sentence in the caption clarifying that the Signal+Noise empty fraction is a hard floor on the false-negative rate.
  3. Section 4.2 / Eq. (2): the reduction from the general LIF (Eq. 1) to the uniform-weight encoder is clear, but a one-line statement that w is absorbed into θ would remove any ambiguity about free parameters.
  4. Section 6.1: the claim that the serializer cost (~2.3 cycles/BC average) fits inside a 10 ns BC at 250 MHz is plausible; a short table or sentence giving the measured serializer latency distribution on the testbed would strengthen it.
  5. References [10] and [11] are listed as “in preparation” / “doi pending”; ensure final bibliographic details are supplied at proof stage.
  6. Typographical: abstract and §1 use both “~320 000” and “∼320,000”; standardize spacing and separators.

Circularity Check

0 steps flagged

No significant circularity: empirical systems paper whose TPR/TNR and sparsification are measured on held-out simulation after a discrete hyperparameter scan and standard surrogate-gradient training, not forced by construction or by load-bearing self-citation.

full rationale

The paper is a design-and-characterization work for a two-stage SNN data-reduction pipeline (per-PDU LIF temporal-coincidence encoder + distributed classifier). The encoder hyperparameters (Δt, k, θ) are not co-trained by gradient descent; they are selected from a discrete scan by end-to-end evaluation of the downstream classifier (Section 5.2–5.3, Figs. 5–6). The classifier itself is trained by standard surrogate-gradient BPTT on the encoder spike streams with an 80/10/10 train/val/test split; reported TPR >94 % / TNR ≥80 % (Fig. 7) and >90 % sparsification are therefore ordinary empirical measurements on held-out simulated events, not quantities that reduce by definition to fitted inputs. Early-exit is an optional inference policy whose latency/accuracy trade-off is likewise measured, not derived tautologically. Self-citations to the authors’ AIGOR architecture ([10]) and the concurrent MLP baseline ([11]) supply the inference fabric and a comparison point; they do not define or force the claimed performance numbers. No uniqueness theorem, ansatz smuggled via citation, or renaming of a known result appears. The derivation chain is therefore self-contained against the paper’s own simulation benchmark; the only soft point is the usual simulation-to-reality gap, which is outside the circularity criterion.

Axiom & Free-Parameter Ledger

5 free parameters · 5 axioms · 2 invented entities

The central claim rests on standard LIF dynamics, the physical timing asymmetry of Cherenkov vs DCR hits, the simulated event sample, a small set of hand-chosen encoder hyperparameters selected by Pareto scan, and the AIGOR execution model. No new physical entities are postulated; free parameters are the discrete encoder configuration and early-exit threshold.

free parameters (5)
  • encoder time bin Δt = 1.27 ns
    Chosen from a discrete scan; deployed value 1.27 ns sits at the accuracy/latency knee (Section 5.3).
  • encoder threshold θ = 2
    Selected jointly with leak and bin size; deployed θ=2 realizes the single-bit coincidence limit.
  • encoder leak shift k = 1
    Integer right-shift amount; k=1 chosen for hardware simplicity and Pareto performance.
  • early-exit threshold ET = 1 (optional)
    Configurable spike-count threshold that trades a few points of TPR/TNR for ~2-timestep average latency.
  • classifier fixed-point format = Q12.20 (HW) / down to Q2.2 (SW)
    Quantization width for membrane and weights; software shows robustness down to Q2.2, hardware currently uses conservative Q12.20.
axioms (5)
  • standard math LIF membrane update V(t+Δt)=αV(t)+Σ w_j x_j(t) with spike-and-reset when V>θ
    Standard leaky-integrate-and-fire model (Eq. 1); used for both encoder and classifier.
  • domain assumption Genuine Cherenkov hits cluster within ~2 ns while DCR is approximately uniform across the 10 ns BC
    Core physical premise stated in Section 2.3 and illustrated in Figure 1; the entire temporal-coincidence strategy rests on it.
  • domain assumption Simulated ePIC events with post-processed DCR injection are representative of real detector occupancy and timing
    All TPR/TNR numbers are obtained on this sample (Sections 2.4, 5); no real-data validation is shown.
  • ad hoc to paper Single-spike-per-BC policy is sufficient for the encoder
    Enables the single-cycle cascade datapath (Section 6.1); justified by the sparsification goal but is a design choice, not a physical necessity.
  • ad hoc to paper Timestep-driven AER synchronization cost dominates current throughput and can be reduced by the listed optimizations
    Explains the 1.7 MHz vs 100 MHz gap (Sections 3.2, 6.4, 7); the claim that the optimizations will close the gap is prospective.
invented entities (2)
  • per-PDU LIF temporal-coincidence encoder (single-bit, same-bin limit) no independent evidence
    purpose: Convert raw multi-hit SiPM words into a sparse ≤1-spike-per-BC stream with >90% sparsification before the learned classifier.
    A specialized, heavily approximated LIF realized in dedicated firmware; not a new physical particle or force, but a new architectural block introduced for this pipeline.
  • distributed two-tier SNN (30 Sub-sector + Aggregation) mapped to FELIX-155 / AIGOR no independent evidence
    purpose: Classify each BC as Signal+Noise vs Noise-Only while respecting the physical sectorization of the readout.
    Topology and mapping are co-designed for the dRICH DAQ; the underlying LIF neurons are standard.

pith-pipeline@v1.1.0-grok45 · 20222 in / 3861 out tokens · 26327 ms · 2026-07-12T02:06:54.271081+00:00 · methodology

0 comments
read the original abstract

The dual-radiator Ring Imaging Cherenkov (dRICH) detector of the ePIC experiment at the Electron-Ion Collider (EIC) will read out $\sim$320,000 silicon photomultiplier (SiPM) channels at a bunch-crossing rate of 100 MHz. The dark count rate (DCR) of the SiPMs is expected to rise up to 300 kHz per channel over the experiment lifetime, saturating the output bandwidth and requiring an online data reduction factor of at least five. Most crossings contain only uncorrelated DCR hits, while genuine Cherenkov hits cluster within $\sim$2 ns of the 10 ns crossing window: an intrinsically temporal discrimination problem. We present a two-stage online data reduction pipeline based on spiking neural networks (SNNs). The first stage is a per-photodetection-unit leaky-integrate-and-fire (LIF) temporal coincidence encoder that converts raw SiPM hits into a sparse spike stream, achieving over 90% data sparsification before any learned classifier is applied. The second stage is a distributed SNN (30 sub-sector networks plus an aggregation network) deployed on FELIX-155 DAM boards and a dedicated Trigger Processor board, classifying each crossing as Noise-Only or Signal+Noise. On simulated ePIC events the system reaches a true positive rate above 94% at a true negative rate of at least 80% across the full DCR range; an optional early-exit strategy reduces the average classification latency to $\sim$2 algorithmic timesteps at the cost of a few percentage points on both metrics. A hardware proof-of-concept on an AMD Versal Premium FPGA, integrating the LIF encoder with the AIGOR multi-core neuromorphic architecture, validates a single sub-sector pipeline at $\sim$1.7 MHz throughput; ongoing work targets 100 MHz through an identified set of optimizations of the inference fabric. The methodology may be relevant to other timing-driven detector applications at high rate.

Figures

Figures reproduced from arXiv: 2607.03492 by Alessandro Lonardo, Andrea Biagioni, Cristian Rossi, Elena Pastorelli, Francesca Lo Cicero, Francesco Simula, Luca Pontisso, Michele Martinelli, Ottorino Frezza, Piero Vicini, Pierpaolo Perticaroli, Pier Stanislao Paolucci, Roberto Ammendola.

Figure 1
Figure 1. Figure 1: Time distribution of SiPM hits within a single [PITH_FULL_IMAGE:figures/full_fig_p005_1.png] view at source ↗
Figure 2
Figure 2. Figure 2: Per-bunch-crossing raw hit multiplicity across the full dRICH at [PITH_FULL_IMAGE:figures/full_fig_p006_2.png] view at source ↗
Figure 3
Figure 3. Figure 3: Two-stage pipeline. Stage 1: per-PDU LIF temporal-coincidence [PITH_FULL_IMAGE:figures/full_fig_p009_3.png] view at source ↗
Figure 4
Figure 4. Figure 4: Two views of the distributed two-tier SNN. (a) Algorithmic flow: [PITH_FULL_IMAGE:figures/full_fig_p011_4.png] view at source ↗
Figure 5
Figure 5. Figure 5: Encoder output spike load for a representative subset of the [PITH_FULL_IMAGE:figures/full_fig_p014_5.png] view at source ↗
Figure 6
Figure 6. Figure 6: Pareto frontier of TPR versus average signal latency (in algorithmic [PITH_FULL_IMAGE:figures/full_fig_p015_6.png] view at source ↗
Figure 7
Figure 7. Figure 7: Classification performance of the full system as a function of SiPM [PITH_FULL_IMAGE:figures/full_fig_p016_7.png] view at source ↗
Figure 8
Figure 8. Figure 8: Classification performance under fixed-point quantization at the [PITH_FULL_IMAGE:figures/full_fig_p016_8.png] view at source ↗
Figure 9
Figure 9. Figure 9: Schematic view of the dRICH online data reduction system de [PITH_FULL_IMAGE:figures/full_fig_p018_9.png] view at source ↗
Figure 10
Figure 10. Figure 10: Overview of a single dRICH sector: each DAM handles 42 data [PITH_FULL_IMAGE:figures/full_fig_p019_10.png] view at source ↗
Figure 11
Figure 11. Figure 11: Per-PDU encoder datapath. The up to four hits of an input word [PITH_FULL_IMAGE:figures/full_fig_p020_11.png] view at source ↗
Figure 12
Figure 12. Figure 12: Single-sub-sector hardware testbed on AMD Versal Premium [PITH_FULL_IMAGE:figures/full_fig_p021_12.png] view at source ↗

discussion (0)

Sign in with ORCID, Apple, or X to comment. Anyone can read and Pith papers without signing in.

Reference graph

Works this paper leans on

27 extracted references · 2 canonical work pages

  1. [1]

    Abdul Khalek et al.,Science Requirements and Detector Concepts for the Electron-Ion Collider: EIC Yellow Report, Nucl

    R. Abdul Khalek et al.,Science Requirements and Detector Concepts for the Electron-Ion Collider: EIC Yellow Report, Nucl. Phys. A 1026 (2022) 122447

    2022

  2. [2]

    Dalla Torre,The Electron-Ion Collider and the ePIC experiment, Nuovo Cim

    S. Dalla Torre,The Electron-Ion Collider and the ePIC experiment, Nuovo Cim. C 47 (2024) 205

    2024

  3. [3]

    Vallarino et al.,Prototype of a dual-radiator RICH detector for the Electron-Ion Collider, Nucl

    S. Vallarino et al.,Prototype of a dual-radiator RICH detector for the Electron-Ion Collider, Nucl. Instrum. Meth. A 1058 (2024) 168834

    2024

  4. [4]

    Rubini et al.,The SiPM readout plane for the ePIC-dRICH detector at the EIC: Overview and beam test results, Nucl

    N. Rubini et al.,The SiPM readout plane for the ePIC-dRICH detector at the EIC: Overview and beam test results, Nucl. Instrum. Meth. A 1082 (2026) 170890

    2026

  5. [5]

    Preghenella et al.,SiPM photosensors for the ePIC dual-radiator RICH detector at the EIC, PoS EPS-HEP2023 (2024) 515

    R. Preghenella et al.,SiPM photosensors for the ePIC dual-radiator RICH detector at the EIC, PoS EPS-HEP2023 (2024) 515

    2024

  6. [6]

    Anderson et al.,FELIX: a high-throughput network approach for interfacing to front-end electronics for ATLAS experiments, J

    J. Anderson et al.,FELIX: a high-throughput network approach for interfacing to front-end electronics for ATLAS experiments, J. Phys.: Conf. Ser. 664 (2015) 082050

    2015

  7. [7]

    Cossio et al.,ALCOR: A mixed-signal ASIC for the dRICH detector of the ePIC experiment at the EIC, Nucl

    F. Cossio et al.,ALCOR: A mixed-signal ASIC for the dRICH detector of the ePIC experiment at the EIC, Nucl. Instrum. Meth. A 1069 (2024) 169817. 24

    2024

  8. [8]

    Boahen,Point-to-point connectivity between neuromorphic chips using address events, IEEE Trans

    K.A. Boahen,Point-to-point connectivity between neuromorphic chips using address events, IEEE Trans. Circuits Syst. II 47 (2000) 416

    2000

  9. [9]

    Ammendola et al.,APEIRON: composing smart TDAQ systems for high energy physics experiments, J

    R. Ammendola et al.,APEIRON: composing smart TDAQ systems for high energy physics experiments, J. Phys.: Conf. Ser. 3206 (2026) 012064, arXiv:2607.02429

    Pith/arXiv arXiv 2026

  10. [10]

    Perticaroli et al.,AIGOR: A Modular, Event-Driven Neuromorphic Architecture for Configurable SNN Inference, arXiv preprint (2026)

    P. Perticaroli et al.,AIGOR: A Modular, Event-Driven Neuromorphic Architecture for Configurable SNN Inference, arXiv preprint (2026). In preparation

    2026

  11. [11]

    Rossi et al.,Online AI-based distributed data reduction for the dual- radiator RICH detector in the ePIC experiment, Nucl

    C. Rossi et al.,Online AI-based distributed data reduction for the dual- radiator RICH detector in the ePIC experiment, Nucl. Instr. Meth. A (2026), doi:10.1016/j.nima.2026.171416

    work page doi:10.1016/j.nima.2026.171416 2026

  12. [12]

    Duarte et al.,Fast inference of deep neural networks in FPGAs for particle physics, JINST 13 (2018) P07027

    J. Duarte et al.,Fast inference of deep neural networks in FPGAs for particle physics, JINST 13 (2018) P07027

    2018

  13. [13]

    Aarrestad et al.,Fast convolutional neural networks on FPGAs with hls4ml, Mach

    T. Aarrestad et al.,Fast convolutional neural networks on FPGAs with hls4ml, Mach. Learn.: Sci. Technol. 2 (2021) 045015

    2021

  14. [14]

    Govorkova et al.,Autoencoders on field-programmable gate arrays for real-time, unsupervised new physics detection at 40 MHz at the Large Hadron Collider, Nat

    E. Govorkova et al.,Autoencoders on field-programmable gate arrays for real-time, unsupervised new physics detection at 40 MHz at the Large Hadron Collider, Nat. Mach. Intell. 4 (2022) 154

    2022

  15. [15]

    CMS Collaboration,The Phase-2 Upgrade of the CMS Level-1 Trigger, CERN-LHCC-2020-004, CMS-TDR-021 (2020)

    2020

  16. [16]

    Aaij et al.,Allen: A High-Level Trigger on GPUs for LHCb, Comput

    R. Aaij et al.,Allen: A High-Level Trigger on GPUs for LHCb, Comput. Softw. Big Sci. 4 (2020) 7

    2020

  17. [17]

    P. Perticaroli et al.,Achieving Low-Latency, High-Throughput Online Partial Particle Identification for the NA62 Experiment Using FPGAs and Machine Learning, Electronics 14 (2025) 1892

    2025

  18. [18]

    Maass,Networks of spiking neurons: The third generation of neural network models, Neural Networks 10 (1997) 1659

    W. Maass,Networks of spiking neurons: The third generation of neural network models, Neural Networks 10 (1997) 1659

    1997

  19. [19]

    Gerstner, W.M

    W. Gerstner, W.M. Kistler, R. Naud, L. Paninski,Neuronal Dynamics: From Single Neurons to Networks and Models of Cognition, Cambridge University Press, 2014

    2014

  20. [20]

    K. Roy, A. Jaiswal, P. Panda,Towards spike-based machine intelligence with neuromorphic computing, Nature 575 (2019) 607

    2019

  21. [21]

    Schuman, S.R

    C.D. Schuman, S.R. Kulkarni, M. Parsa, J.P. Mitchell, P. Date, B. Kay, Opportunities for neuromorphic computing algorithms and applications, Nat. Comput. Sci. 2 (2022) 10. 25

    2022

  22. [22]

    Davies et al.,Loihi: A neuromorphic manycore processor with on- chip learning, IEEE Micro 38 (2018) 82

    M. Davies et al.,Loihi: A neuromorphic manycore processor with on- chip learning, IEEE Micro 38 (2018) 82

    2018

  23. [23]

    S. Deng, D. Yu, C. Lv, X. Du, L. Jiang, X. Zhao, W. Tong, X. Zheng, W. Fang, P. Zhao, G. Pan, S. Dustdar, A.Y. Zomaya,Edge Intelligence with Spiking Neural Networks, arXiv:2507.14069 (2025)

    Pith/arXiv arXiv 2025

  24. [24]

    Neftci, H

    E.O. Neftci, H. Mostafa, F. Zenke,Surrogate Gradient Learning in Spik- ing Neural Networks, IEEE Signal Processing Magazine 36 (2019) 51

    2019

  25. [25]

    Eshraghian, M

    J.K. Eshraghian, M. Ward, E.O. Neftci, X. Wang, G. Lenz, G. Dwivedi, M. Bennamoun, D.S. Jeong, W.D. Lu,Training Spiking Neural Net- works Using Lessons from Deep Learning, Proceedings of the IEEE 111 (2023) 1016

    2023

  26. [26]

    S.R. Kulkarni et al.,On-Sensor Data Filtering using Neuromorphic Computing for High Energy Physics Experiments, in Proceedings of the 2023 International Conference on Neuromorphic Systems (ICONS ’23), doi:10.1145/3589737.3605976

    work page doi:10.1145/3589737.3605976 2023

  27. [27]

    Coradin et al.,Unsupervised Particle Tracking with Neuromorphic Computing, Particles 8 (2025) 40, arXiv:2502.06771

    E. Coradin et al.,Unsupervised Particle Tracking with Neuromorphic Computing, Particles 8 (2025) 40, arXiv:2502.06771. 26

    arXiv 2025