End-to-End Modeling of a Volatile TiO2 Memristor for Neuromorphic Circuit Simulation

Hannes T\"opfer; Hauke Honig; Lukas Endres; Michaela Blum; Peter Schaaf

REVIEW 4 major objections 6 minor 14 references

End-to-End Modeling of a Volatile TiO2 Memristor for Neuromorphic Circuit Simulation

T0 review · 4 major / 6 minor · reviewed 2026-07-30 · grok-4.5

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Pith's one-line read A leakage-extended Yakopcic SPICE model fitted to a volatile TiO2 memristor reproduces its measured switching and runs a leaky integrate-and-fire neuron.

desk verdict Solid local engineering: a fitted, leakage-extended Yakopcic SPICE subcircuit for one volatile TiO2 stack, useful if you co-design with similar devices, not a modeling breakthrough. read the letter →

arxiv 2607.26815 v1 pith:P7CYL3AW submitted 2026-07-29 cond-mat.mtrl-sci eess.SP

Lukas Endres , Hannes Töpfer , Michaela Blum , Hauke Honig , Peter Schaaf This is my paper · ORCID

classification cond-mat.mtrl-scieess.SP

keywords memristorTiO2volatileswitchingYakopcicmodelSPICEneuromorphiccomputingleakyintegrate-and-fireparameterfitting

verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

Circuit designers need device models that match real memristor measurements under both slow voltage sweeps and short pulses if they want trustworthy neuromorphic simulations. This paper takes experimental data from a fabricated volatile Pt/TiO2/Ag memristor, confirms its pinched hysteresis and second-scale resistance relaxation, and fits an extended Yakopcic model whose parameters are optimized to those traces. The fitted equations are packaged as a reusable SPICE subcircuit and shown to reproduce the main features of the measured I–V loops and pulse decay. The same subcircuit is dropped into a leaky integrate-and-fire neuron, where the leakage term lets the device recover and fire repeatedly. The result is a practical end-to-end path from lab data to circuit-level neuromorphic simulation for this class of volatile devices.

What carries the argument

The leakage-extended Yakopcic model: a hyperbolic-sine I–V relation coupled to a thresholded state ODE that includes a Biolek window and the relaxation term l(x)=−(x−x_eq)/τ, realized as two behavioral sources plus a 1 F integrator capacitor in a SPICE subcircuit.

What would settle it

Build the same leaky-integrate-and-fire circuit with the physical TiO2 devices and check whether the measured spike timing and recovery match the SPICE prediction under identical current-pulse trains; systematic mismatch in inter-spike intervals or failure to recover would falsify the claim that the fitted model is adequate for neuromorphic simulation.

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Extended reading notes

Core claim

The authors show that a Yakopcic memristor model extended by a Biolek window and a simple exponential leakage term, with parameters optimized to their TiO2 device data, reproduces the measured pinched hysteresis below compliance and the volatile resistance relaxation under pulsed excitation well enough to serve as a SPICE subcircuit for neuromorphic circuit simulation, as demonstrated by repeated spiking in a memristor-based leaky integrate-and-fire neuron.

Load-bearing premise

A single deterministic state variable that always relaxes exponentially toward a fixed equilibrium is enough to stand in for the device’s real, noisy, cycle-to-cycle filament dynamics.

Editorial extensions

If this is right

Volatile TiO2 memristors characterized at low compliance current can be dropped directly into SPICE netlists for neuromorphic design.
The leakage term is what enables repetitive spiking; without it the neuron would lock into a low-resistance state after the first fire.
The same five-stage workflow (data assessment, model selection, parameter fit, SPICE packaging, validation) can be reused for other volatile memristor technologies.
Circuit-level studies of larger memristive networks become possible once each device is represented by this parameterized subcircuit.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

Because the paper already flags metastable intermediate states and cycle-to-cycle scatter, the next natural model upgrade is a stochastic x_eq or a multi-state filament description rather than a finer deterministic fit.
The very low compliance current that produces volatility also caps the ON/OFF ratio; the same modeling pipeline could quantify how raising compliance trades volatility for retention and thereby maps the usable design space for synaptic versus memory use.
Once the SPICE subcircuit is public, standard oscillator and network-stability tools can be applied to memristor LIF arrays without re-deriving device physics each time.

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Signed reviews

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Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Desk Editor's Note

read the letter

This is a clean end-to-end device-to-SPICE pipeline on a lateral Pt/TiO2/Ag volatile memristor. What is actually new is the artifact: parameters (Table 1), the leakage-extended Yakopcic/Biolek equations in SPICE (Fig. 9), and a working LIF demo that needs the leak term for repeated spikes. The pieces themselves are known—Yakopcic I–V and thresholds, Biolek window, Chen-style forgetting—and the paper is honest about that.

What it does well is the workflow. They check the pinched loop, strip compliance artifacts, fit with NMSE coordinate descent, extract τ≈4.2 s from READ decay under x_eq=0, translate to a reusable subcircuit, and overlay sim vs measure for both triangle and pulse. The limitations section is unusually straight: low CC, ON/OFF ~35, cycle scatter 40–100 MΩ, metastable states the leak term misses, and stochastic filament jitter the deterministic ODE cannot capture. That candor helps.

The soft spots are real but proportionate. Validation is same-distribution visual agreement on the traces used for fitting; no held-out protocol, no multi-device stats, no quantitative error beyond NMSE on preprocessed I–V. An is negative to match the observed polarity, which is fine empirically but undersells mechanism. The LIF runs on ~28 ms pulses while τ came from 15 s averages—illustrative, not a fidelity proof. The stress-test concern lands: if metastability and cycle variance dominate under repeated subthreshold integration, average-trace match does not guarantee neuromorphic usefulness. The paper already flags this for future stochastic work, so it is not hidden.

Math and citations look fine; no invented entities, no load-bearing contradiction. Reproducibility is mid: full SPICE text in-paper, no data/code release.

Who it is for: groups already building circuits around similar volatile oxide devices who need a drop-in subcircuit. Not for people hunting new switching physics or general memristor theory. I would send it to peer review—method is coherent, claims are checkable, limitations are owned. Engage if the device class matches your stack; otherwise skim the SPICE and move on.

Referee Report

4 major / 6 minor

Summary. The manuscript develops an end-to-end workflow for a volatile lateral Pt/TiO2/Ag memristor: experimental I–V and pulse characterization, selection of a Yakopcic-type model with Biolek window and an added exponential leakage term, coordinate-descent NMSE fitting of parameters (plus algebraic extraction of τ from READ decay), translation into a SPICE subcircuit, qualitative comparison of simulated vs. measured traces, and a purely simulated leaky integrate-and-fire neuron in which the memristor replaces the MOSFET threshold element. The central claim is that the fitted leakage-extended model reproduces the device’s pinched hysteresis (below compliance) and volatile relaxation well enough for circuit-level neuromorphic simulation.

Significance. If the fitted SPICE model is reliable under the excitation regimes of interest, the work supplies a practical, reusable subcircuit and a clear measurement-to-model pipeline for volatile TiO2 devices, which is useful for neuromorphic circuit designers who need device-level models rather than idealized non-volatile memristors. Strengths include the explicit leakage extension needed for repetitive spiking, the open SPICE listing, and the side-by-side measurement/simulation figures. Novelty is incremental: Yakopcic, Biolek, and forgetting/leakage terms are established; the contribution is primarily engineering integration and device-specific parameterization rather than a new physical model or multi-device statistical validation.

major comments (4)

[§VI.B–D, §VIII.B] §VI.B–D and §VIII.B: Parameter identification (NMSE coordinate descent on compliance-stripped, filtered I–V conductance; τ from averaged READ decay via Eqs. 9–11 with x_eq=0) and ‘validation’ use the same device traces and protocols. No held-out pulse protocol, no quantitative error (e.g., per-cycle NMSE or resistance RMSE on unseen sequences), and no multi-device statistics are reported. The Abstract and §VIII claim of suitability for neuromorphic circuit simulation therefore rests on qualitative visual agreement with the fitting data. A minimum fix is a quantitative held-out comparison and explicit error bars or cycle statistics.
[§VI.C, Eq. (6), Table 1] §VI.C–D, §III.D, §VIII.B, §IX: The model assumes deterministic single-exponential leakage l(x)=−(x−x_eq)/τ with fixed x_eq=0 (Eq. 6, Table 1). The paper itself documents cycle-to-cycle READ scatter (40–100 MΩ), metastable intermediate states ‘not captured by the leakage term,’ and stochastic filament fluctuations. These are load-bearing for retention and for any circuit that integrates subthreshold activity over many cycles. Either demonstrate that average-trace fidelity still yields acceptable LIF/network statistics under the observed variance, or treat x_eq (or τ) as stochastic as the authors themselves propose only in future work.
[§VIII.C, §VI.C] §VIII.C vs §VI.C: The LIF demonstration uses ~28 ms pulse periods and produces repetitive spikes that explicitly require the leakage term, while τ≈4.2 s was extracted from 15 s READ averages. On the LIF timescale the leakage is almost frozen (Δx/x ~ few percent per cycle unless the state is driven near threshold every cycle). The manuscript should quantify how sensitive spike rate and threshold crossing are to τ and to the unmodeled metastability, and justify that a τ fitted on 15 s decays remains appropriate for tens-of-ms neuromorphic operation.
[Table 1, Eq. (4), §VI.D] Table 1 and §VI.D: An is negative (−0.0012), which inverts the usual polarity of the negative-threshold branch of g(u) (Eq. 4). The text notes this reflects decreasing memristance under negative bias, but does not show that the resulting dx/dt remains consistent with the window and with 0≤x≤1 under bipolar sweeps, nor that the fit is unique under coordinate descent. A short sensitivity or sign-constraint check is needed so that the SPICE subcircuit does not rely on an accidental local minimum.

minor comments (6)

[Fig. 9, Eq. (6)] Fig. 9 / Leakage func: SPICE code implements Leakage(x)=−(x+x_eq)/tau while Eq. (6) is −(x−x_eq)/τ. With the fitted x_eq=0 the two coincide, but the listing is inconsistent with the equation and will be wrong if x_eq≠0 is used later.
[§VI.C] §VI.C: τ is reported as τ̄≈−4.2 s then used as τ=4.2 s in Table 1. Clarify that the minus sign is an artifact of the log formula and that the physical time constant is positive.
[§IV–VI] Notation: g(t) is used both for conductance and for the threshold function g(u); rename one to avoid confusion in §IV–VI.
[Fig. 1b] Fig. 1b and related plots: ‘normalized’ u(t), i(t), g(t) lack stated normalization constants; add them for reproducibility.
[§V, References] References: Biolek window and Yakopcic are appropriately cited; a brief pointer to other volatile/diffusive memristor SPICE models would help position the leakage extension.
Minor typos: ‘Y akopcic’ spacing, ‘Indigital’ → ‘In digital’, ‘memristance’ vs resistance consistency, and arXiv date stamp ‘29 Jul 2026’ looks like a metadata error.

Circularity Check

2 steps flagged · score 5.0 of 10

Parameters (incl. τ) are fitted to the same I–V/pulse traces that the SPICE ‘validation’ then replays; agreement is largely by construction, not an independent prediction.

fitted input called prediction [§VI.B Eq. (8); Table 1; §VIII.B; Abstract/§IX]
"The parameter optimization aims to minimize the error between the simulated and measured I-V-curves. As an objective function, the Normalized Mean Squared Error (NMSE) is used... Using the optimized parameter set from Table 1, the SPICE model was simulated under the same excitation conditions as the measurements... the SPICE implementation captures the main qualitative features of the measured device behavior... Comparison with experimental measurements demonstrated that the proposed model accurately reproduces the electrical behavior of the investigated device."

Coefficients are explicitly optimized so simulated conductance matches the preprocessed measured I–V set. The subsequent SPICE ‘validation’ replays the same class of triangular/pulse excitations on that fitted parameter vector and treats visual/qualitative agreement as evidence the model reproduces the device. That agreement is the objective of the fit, not an out-of-sample prediction; the Abstract/Conclusion wording elevates the training match to independent confirmation.
fitted input called prediction [§VI.C Eqs. (9)–(11); Fig. 2b; §VIII.B pulsed validation]
"For the experimental data (see Figure 2b), x_eq = 0 was assumed, and the read interval corresponds to t1−t0 = t_read = 15 s. Using the averaged resistance values M̄(t0)=3 MΩ and M̄(t1)=108 MΩ, the mean time constant is obtained as τ̄≈4.2 s... For pulsed excitation, the simulation captures the volatile switching behavior of the device, including the resistance increase during the write pulse and the subsequent relaxation during the read pulse."

τ is not predicted; it is solved from the measured READ conductance decay by inverting the analytical leakage solution that the model already assumes (with x_eq fixed to 0). The pulsed SPICE comparison then cites the same relaxation behavior as validation of volatility. The decay timescale used to claim the model captures volatile retention is the fitted input itself.

full rationale

This is a standard phenomenological device-modeling paper (select Yakopcic+Biolek+leakage, fit coefficients, drop into SPICE). The model structure and leakage ansatz are imported from external literature, and the LIF neuron is only a simulated application demo—so there is real engineering content and no self-citation uniqueness chain. Circularity is limited to the validation claim: a1,a2,b,Vp,Vn,Ap,An are chosen by coordinate-descent NMSE on preprocessed measured conductance (Eq. 8, §VI.B; Fig. 8), and τ≈4.2 s is algebraically read off the same device’s READ decay under the assumed exponential leakage solution (Eqs. 9–11, §VI.C). Section VIII.B then excites the fitted SPICE subcircuit with triangular/pulsed waveforms of the same character and reports ‘good agreement’ with those measurements. That match is statistically forced by the fit; there is no held-out protocol, multi-device set, or independent observable. Score 5 reflects partial fitted-input-as-prediction on the central reproducibility claim, not a fully tautological derivation.

Assumptions & free parameters 10 free parameters · 7 assumptions · 0 invented entities

The central claim rests on accepting the Yakopcic-style two-equation memristor template, Biolek boundary handling, and a linear relaxation leak, then treating ~10 scalar parameters as free and identifying them from one device’s preprocessed traces. No new physical entity is postulated; the load is almost entirely free parameters plus standard domain modeling choices. Independent evidence for the functional forms is inherited from citations, not re-derived here.

free parameters (10)

a1 (positive-bias sinh prefactor) = 2.6e-6
Fitted coefficient in the I–V relation for u≥0; sets scale of conductance with state x.
a2 (negative-bias sinh prefactor) = 1.2e-6
Independent prefactor for u<0 to allow I–V asymmetry; fitted to data.
b (sinh nonlinearity) = 0.85
Controls voltage nonlinearity of the hyperbolic-sine conduction model; fitted.
Vp, Vn (threshold voltages) = 1.5 V, 1.0 V
Positive/negative voltages below which g(u)=0; chosen/fitted to match onset of switching.
Ap, An (threshold rate scales) = 0.0055, -0.0012
Exponential threshold gain factors; An fitted negative to capture decreasing memristance under negative bias.
p (Biolek window exponent) = 1
Integer shaping boundary soft-clipping of dx/dt; paper notes unreliable identification from coarse Δt.
tau (leakage time constant) = 4.2 s
Extracted from READ-interval conductance decay assuming pure exponential relaxation; load-bearing for volatility and LIF recovery.
x_eq (equilibrium state) = 0
Assumed 0 so device fully relaxes to initial HRS; simplifies τ formula but conflicts with noted metastable states.
eta, x0 = eta=1, x0=0
Polarity factor and initial state for integration; set by convention for the fits/simulations.
compliance current / CC-removal mask = 1 µA
Experimental 1 µA limit defines which I–V points enter the fit and the lowest R state; not a model parameter but a free experimental choice that shapes all extracted values.

assumptions (7)

domain assumption Memristive behavior is identified with a pinched I–V hysteresis through the origin (Chua phenomenological definition).
Used in §III.A/D to justify that the TiO2 device is memristive and therefore modelable by the two-equation framework.
domain assumption Device dynamics obey i=G(x,u)u and dx/dt = η g(x,u) f(x,u) + l(x) with 0≤x≤1.
§IV general template taken as given for all subsequent modeling.
domain assumption Yakopcic sinh I–V plus exponential threshold g(u) is an adequate conduction/switching skeleton for this oxide device.
§V adopts [9] because it ‘can be fitted to a wide variety of memristors,’ without independent mechanism derivation for TiO2 filaments.
domain assumption Biolek window f(x,u,p) correctly enforces state boundaries for this device.
§V.C substitutes Biolek [10] for Yakopcic’s window to reduce parameter count.
ad hoc to paper Voltage-free relaxation is a single-exponential leak l(x)=−(x−x_eq)/τ toward a fixed equilibrium.
§V.D imports form from [11]; paper later notes metastable intermediates not captured by this term (§VI.C).
ad hoc to paper Coordinate-descent minimization of conductance NMSE on compliance-stripped, low-pass-filtered traces yields parameters that generalize to circuit operation.
§VI.A–B defines the fitting objective and preprocessing; central to claiming model suitability.
standard math Standard circuit calculus / SPICE behavioral sources and a 1 F integrator capacitor correctly realize the state ODE.
§VII implementation technique; mathematically standard.

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Cite this review

Pith. "Pith review of End-to-End Modeling of a Volatile TiO2 Memristor for Neuromorphic Circuit Simulation." pith.science (2026). https://pith.science/paper/P7CYL3AW

@misc{pith2026260726815,
  author       = {Pith},
  title        = {Pith review of: End-to-End Modeling of a Volatile TiO2 Memristor for Neuromorphic Circuit Simulation},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/P7CYL3AW}},
  note         = {Machine review of arXiv:2607.26815}
}

read the original abstract

Memristors are promising devices for applications such as non-volatile memory, neuromorphic computing, logic circuits, and analog signal processing. The development of such systems requires accurate simulations based on models that reproduce the electrical behavior of real devices under both continuous and pulsed excitation. This work presents the development of a simulation environment for a volatile TiO2-based memristor. Experimental measurement data are analyzed to verify the memristive behavior of the device and to identify a suitable model. The model parameters are then optimized to match the measured characteristics. The resulting model is implemented in SPICE and validated by comparing simulation results with measurement data. The comparison shows a good agreement between simulation and experiment, demonstrating that the developed model is suitable for reproducing the electrical behavior of the investigated memristor and can be applied in circuit-level simulations, as demonstrated by a leaky integrate-and-fire neuron.

Figures

Figures reproduced from arXiv: 2607.26815 by the authors.

**Figure 1.** a shows the measured I–V characteristics of the device under a triangular voltage sweep from 0 V to 6 V, down to −6 V, and back to 0 V (total measurement duration 1.2 min), with arrows indicating the sweep direction. Figure 1b presents the corresponding normalized signals u(t), i(t), and g(t). (a) (b) [PITH_FULL_IMAGE:figures/full_fig_p002_1.png] view at source ↗

**Figure 3.** Simulation results of the selected memris [PITH_FULL_IMAGE:figures/full_fig_p003_3.png] view at source ↗

**Figure 4.** Functions defining the state dynamics of [PITH_FULL_IMAGE:figures/full_fig_p004_4.png] view at source ↗

Figures from the paper (8 more)

**Figure 5.** Figure 5: Simulated leakage dynamics of the state variable x(t) for different time constants τ . Parameters: x0 = 0.9 and xeq = 0.2. B. Threshold Function The threshold function (Figure 4a) g(u) =    Ap [PITH_FULL_IMAGE:figures/full_fig_p005_5.png]

**Figure 6.** Figure 6: Simulation results of the Yakopcic model [PITH_FULL_IMAGE:figures/full_fig_p005_6.png]

**Figure 7.** Figure 7: Preprocessing of the measured I–V data: (a) after compliance current removal, (b) after additional low-pass filtering. ment data from a TiO2-based memristor. For this purpose, the model was implemented in Python, allowing efficient simulation, data processing, and pa…

**Figure 8.** Figure 8: Fitted Measurement to the proposed model. [PITH_FULL_IMAGE:figures/full_fig_p006_8.png]

**Figure 9.** Figure 9: Translating the proposed memristor model [PITH_FULL_IMAGE:figures/full_fig_p007_9.png]

**Figure 10.** Figure 10: SPICE subcircuit of the memristor model. [PITH_FULL_IMAGE:figures/full_fig_p008_10.png]

**Figure 12.** Figure 12: SPICE-Simulation results of the proposed [PITH_FULL_IMAGE:figures/full_fig_p008_12.png]

**Figure 13.** Figure 13: Example application of the proposed memristor model in a leaky integrate-and-fire neuron based on [12]: (a) Modified SPICE circuit in which the original MOSFET is replaced by the proposed memristor model, (b) applied input current pulses, (c) simulated output voltag…

Discussion (0). Continue with ORCID to comment.

Reference graph

Works this paper leans on

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Pith tools

Reviewed July 30, 2026 · model on record in the stance chip above.

[1] [1]

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D. B. Strukov, G. S. Snider, D. R. Stewart, and R. S. Williams, “The missing memristor found,” 9 nature, vol. 453, no. 7191, pp. 80–83, 2008. DOI:10.1038/nature06932

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[2] [2]

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L. Chua, “Memristor-the missing circuit ele- ment,”IEEE Transactions on circuit theory, vol. 18, no. 5, pp. 507–519, 1971.DOI:10 . 1109/tct.1971.1083337

arXiv 1971

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I. Abraham, “The case for rejecting the mem- ristor as a fundamental circuit element,”Scien- tific reports, vol. 8, no. 1, p. 10 972, 2018,ISSN: 2045-2322.DOI:10.1038/s41598-018-29394- 7

work page doi:10.1038/s41598-018-29394- 2018

[4] [4]

Memristor spice modeling,

C. Y akopcic, T. M. Taha, G. Subramanyam, and R. E. Pino, “Memristor spice modeling,” in Advances in Neuromorphic Memristor Science and Applications, R. Kozma, R. E. Pino, and G. E. Pazienza, Eds., Springer, 2012, ch. 12, pp. 211–244.DOI:10 . 1007 / 978 - 94 - 007 - 4491-2_12

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[5] [5]

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L. Chua, “Everything you wish to know about memristors but are afraid to ask,” inHandbook of Memristor Networks, Springer, 2019, pp. 89– 157.DOI:10.1007/978-3-319-76375-0_3

work page doi:10.1007/978-3-319-76375-0_3 2019

[6] [6]

Current compliance impact on the variability of hfo 2-based rram devices,

M. Zhang, S. Long, Y . Li, Q. Liu, H. Lv, and M. Liu, “Current compliance impact on the variability of hfo 2-based rram devices,” in 2016 IEEE Silicon Nanoelectronics Workshop (SNW), IEEE, IEEE, 2016, pp. 96–97.DOI: https : / / doi . org / 10 . 1109 / SNW . 2016 . 7578002

2016

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K. Humood, S. Saylan, B. Mohammad, and M. Abi Jaoude, “Effect of the compliance current on the retention time of cu/hfo2-based mem- ristive devices,”Journal of Electronic Materials, vol. 50, no. 8, pp. 4397–4406, 2021.DOI:10. 1007/s11664-021-08995-5

2021

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Memristive devices for computing,

J. J. Y ang, D. B. Strukov, and D. R. Stew- art, “Memristive devices for computing,”Nature nanotechnology, vol. 8, no. 1, pp. 13–24, Dec. 2013,ISSN: 1748-3395.DOI:10.1038/nnano. 2012.240

doi:10.1038/nnano 2013