REVIEW 3 cited by
SpiNNaker 2: A 10 Million Core Processor System for Brain Simulation and Machine Learning
Not yet reviewed by Pith; the record is open.
This paper has not been read by Pith yet. Machine review is queued; the pith claim, tier, and objections will appear here once it completes.
SPECIMEN: schema-true, not a live event
T0 review · schema-true
One-sentence machine reading of the paper's core claim.
pith:XXXXXXXX · record.json · timestamp
abstract
SpiNNaker is an ARM-based processor platform optimized for the simulation of spiking neural networks. This brief describes the roadmap in going from the current SPINNaker1 system, a 1 Million core machine in 130nm CMOS, to SpiNNaker2, a 10 Million core machine in 22nm FDSOI. Apart from pure scaling, we will take advantage of specific technology features, such as runtime adaptive body biasing, to deliver cutting-edge power consumption. Power management of the cores allows a wide range of workload adaptivity, i.e. processor power scales with the complexity and activity of the spiking network. Additional numerical accelerators will enhance the utility of SpiNNaker2 for simulation of spiking neural networks as well as for executing conventional deep neural networks. These measures should increase the simulation capacity of the machine by a factor $>$50. The interplay between the two domains, i.e. spiking and rate based, will provide an interesting field for algorithm exploration on SpiNNaker2. Apart from the platforms' traditional usage as a neuroscience exploration tool, the extended functionality opens up new application areas such as automotive AI, tactile internet, industry 4.0 and biomedical processing.
Forward citations
Cited by 3 Pith papers
-
Dynamic neural manifolds for flexible closed-loop control on neuromorphic hardware
A spiking ring-network model with dynamically controllable manifold geometry is deployed on SpiNNaker 2 hardware to drive closed-loop robotic maze navigation.
-
AIGOR: A Modular, Event-Driven Neuromorphic Architecture for Configurable SNN Inference
AIGOR generates modular, timestep-synchronized FPGA SNN cores from a declarative spec and matches snnTorch accuracy and NEST spike patterns on the same Versal cores across two FPGAs.
-
SENMAP: Multi-objective data-flow mapping and synthesis for hybrid scalable neuromorphic systems
SENMap, a multi-objective mapping tool for the SENECA neuromorphic architecture, claims 40% energy savings in simulation by jointly optimizing network placement and event rate.
Discussion (0). Continue with ORCID to comment.