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SpiNNaker 2: A 10 Million Core Processor System for Brain Simulation and Machine Learning

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arxiv 1911.02385 v1 pith:PA7ISL25 submitted 2019-11-06 cs.ET

Christian Mayr , Sebastian Hoeppner , Steve Furber This is my paper · ORCID
classification cs.ET
keywords machinesimulationspikingcoremillionnetworksneuralpower
verification ladder T0 review T1 audit T2 compute T3 formal

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abstract

SpiNNaker is an ARM-based processor platform optimized for the simulation of spiking neural networks. This brief describes the roadmap in going from the current SPINNaker1 system, a 1 Million core machine in 130nm CMOS, to SpiNNaker2, a 10 Million core machine in 22nm FDSOI. Apart from pure scaling, we will take advantage of specific technology features, such as runtime adaptive body biasing, to deliver cutting-edge power consumption. Power management of the cores allows a wide range of workload adaptivity, i.e. processor power scales with the complexity and activity of the spiking network. Additional numerical accelerators will enhance the utility of SpiNNaker2 for simulation of spiking neural networks as well as for executing conventional deep neural networks. These measures should increase the simulation capacity of the machine by a factor $>$50. The interplay between the two domains, i.e. spiking and rate based, will provide an interesting field for algorithm exploration on SpiNNaker2. Apart from the platforms' traditional usage as a neuroscience exploration tool, the extended functionality opens up new application areas such as automotive AI, tactile internet, industry 4.0 and biomedical processing.

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Forward citations

Cited by 11 Pith papers

Reviewed papers in the Pith corpus that reference this work. Sorted by Pith novelty score. OpenAlex reports about 89 citations worldwide. Full citation record

  1. SpikeX: Exploring Accelerator Architecture and Network-Hardware Co-Optimization for Sparse Spiking Neural Networks

    cs.NE 2025-05 conditional novelty 6.0 of 10

    A simulated spike-based accelerator with spatiotemporal dispatch and sparsity-aware training claims 15.1x to 150.87x better energy-delay product than a prior SNN systolic baseline.

  2. Accelerating Linear Recurrent Neural Networks for the Edge with Unstructured Sparsity

    cs.LG 2025-02 conditional novelty 6.0 of 10

    Sparse, 8-bit quantized S5 linear RNNs match dense model audio denoising accuracy with 2x less compute and 36% less memory, and run 42x faster with 149x lower energy on Loihi 2 than a dense FP32 model on Jetson Orin Nano.

  3. Event-based backpropagation on the neuromorphic platform SpiNNaker2

    cs.NE 2024-12 conditional novelty 6.0 of 10

    The authors implement EventProp on SpiNNaker2 and show that it can train a small spiking network on-chip, with an off-chip simulator that closely matches the hardware.

  4. Dynamic neural manifolds for flexible closed-loop control on neuromorphic hardware

    cs.NE 2026-07 conditional novelty 5.0 of 10

    A spiking ring-network model with dynamically controllable manifold geometry is deployed on SpiNNaker 2 hardware to drive closed-loop robotic maze navigation.

  5. AIGOR: A Modular, Event-Driven Neuromorphic Architecture for Configurable SNN Inference

    cs.AR 2026-07 conditional novelty 5.0 of 10

    AIGOR generates modular, timestep-synchronized FPGA SNN cores from a declarative spec and matches snnTorch accuracy and NEST spike patterns on the same Versal cores across two FPGAs.

  6. Higher-Order Neuromorphic Ising Machines -- Autoencoders and Fowler-Nordheim Annealers are all you need for Scalability

    cs.NE 2025-06 conditional novelty 5.0 of 10

    A clause-based autoencoder architecture with Fowler-Nordheim annealing solves higher-order Ising problems directly, avoiding quadratization overhead and matching or beating prior Ising solvers on benchmarks.

  7. NeuroCoreX: An Open-Source FPGA-Based Spiking Neural Network Emulator with On-Chip Learning

    cs.NE 2025-06 conditional novelty 5.0 of 10

    An FPGA-based spiking neural network emulator with all-to-all connectivity and on-chip STDP learning is presented and tested on digit classification and a citation-graph task.

  8. SENMAP: Multi-objective data-flow mapping and synthesis for hybrid scalable neuromorphic systems

    cs.NE 2025-06 conditional novelty 5.0 of 10

    SENMap, a multi-objective mapping tool for the SENECA neuromorphic architecture, claims 40% energy savings in simulation by jointly optimizing network placement and event rate.

  9. Lightweight LIF-only SNN accelerator using differential time encoding

    cs.NE 2025-05 conditional novelty 4.0 of 10

    A LIF-only SNN accelerator using differential time encoding reports 99.03% MNIST accuracy on FPGA and ASIC with no multiplication operations.

  10. Noise Adaptor: Enhancing Low-Latency Spiking Neural Networks through Noise-Injected Low-Bit ANN Conversion

    cs.NE 2024-11 conditional novelty 4.0 of 10

    Injecting uniform noise before activation quantization in ANN training improves converted low-latency SNN accuracy without runtime noise correction.

  11. Contemporary implementations of spiking bio-inspired neural networks

    cs.NE 2024-12 conditional

    A review of CMOS, memristive, superconducting, and optical hardware for spiking neural networks, concluding that hybrid approaches are the most promising direction.

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