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ForgeEDA: A Comprehensive Multimodal Dataset for Advancing EDA

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arxiv 2505.02016 v1 pith:PDM5LBUU submitted 2025-05-04 cs.AR

classification cs.AR
keywords forgeedacomprehensiveperformancecircuitdatasetnetliststasksability
verification ladder T0 review T1 audit T2 compute T3 formal
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We introduce ForgeEDA, an open-source comprehensive circuit dataset across various categories. ForgeEDA includes diverse circuit representations such as Register Transfer Level (RTL) code, Post-mapping (PM) netlists, And-Inverter Graphs (AIGs), and placed netlists, enabling comprehensive analysis and development. We demonstrate ForgeEDA's utility by benchmarking state-of-the-art EDA algorithms on critical tasks such as Power, Performance, and Area (PPA) optimization, highlighting its ability to expose performance gaps and drive advancements. Additionally, ForgeEDA's scale and diversity facilitate the training of AI models for EDA tasks, demonstrating its potential to improve model performance and generalization. By addressing limitations in existing datasets, ForgeEDA aims to catalyze breakthroughs in modern IC design and support the next generation of innovations in EDA.

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Cited by 4 Pith papers

Reviewed papers in the Pith corpus that reference this work. Sorted by Pith novelty score.

  1. RTL-BenchLS: A Large-Scale Benchmark for RTL Reasoning and Generation with Large Language Models

    cs.AI 2026-06 unverdicted novelty 8.0 of 10

    RTL-BenchLS supplies a large-scale formally verified benchmark and three novel tasks that expose low performance of frontier LLMs on realistic RTL reasoning and generation.

  2. CapBench: A Multi-PDK Dataset for Machine-Learning-Based Post-Layout Capacitance Extraction

    cs.AR 2026-04 accept novelty 7.0 of 10

    CapBench is a new multi-PDK dataset of post-layout 3D windows with high-fidelity capacitance labels and multiple ML-ready representations, plus baseline results showing CNN accuracy versus GNN speed trade-offs.

  3. R2G: A Multi-View Circuit Graph Benchmark Suite from RTL to GDSII

    cs.CV 2026-04 accept novelty 7.0 of 10

    R2G is a multi-view circuit graph benchmark showing that representation choice affects GNN accuracy more than model architecture, with node-centric views and deeper decoders performing best.

  4. Miter-Aware LUT Mapping: Aligning Structure and Solvability for Efficient Logic Equivalence Checking

    cs.AR 2026-07 conditional novelty 6.0 of 10

    Joint LUT mapping of golden and implementation circuits, combined with Gaussian-guided XOR modeling and solver-oriented LUT selection, reduces SAT-based logic equivalence checking runtime by up to 92.1%.

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