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Paper Citation Record · LEDGER

LUTNet: Rethinking Inference in FPGA Soft Logic

As of 10 August 2026, this Paper Citation Record lists 0 of 0 outbound references and 2 inbound Pith citation observations for arXiv:1904.00938.

A citation records a reference. It does not transfer a finding from one paper to another.

pith.paper-citation-record.v1
1904.00938 v1

Coverage vector

measured 0 of 0 reference resolution

Typed states for the displayed outbound observations.

Source: paper_references, paper_reference_links

measured 2 of 2 standing notices

One-hop event checks from named stored sources.

Source: scholarly_work_events, retraction_status_cache, observed 2026-08-09T06:31:02.800959+00:00

measured 2 of 2 inbound itemization

Pith citing papers itemized under the disclosed page cap.

Source: paper_references, paper_reference_links, observed 2026-08-03T16:38:11.406901Z

measured 1 of 1 external citation measurements

A source-named dated measurement, never combined with another source.

Source: pith, observed 2026-08-05T02:28:24.338817Z

Reference resolution

0 of 0 outbound references displayed

  • verified exact0
  • verified fuzzy0
  • unresolved0
  • parse uncertain0
  • malformed identifier0
  • metadata mismatch0

External citation measurements

8
pith, observed 2026-08-05T02:28:24.338817Z

Outbound references

No outbound reference observations are available for this paper version.

Pith citing papers

Observation a23ff049-62c3-4f2b-bcef-b1859b01ae35 · inbound

KANEL\'E: Kolmogorov-Arnold Networks for Efficient LUT-based Evaluation cites this paper.

KANEL\'E: Kolmogorov-Arnold Networks for Efficient LUT-based Evaluation LUTNet: Rethinking Inference in FPGA Soft Logic

Reference 2019

Resolution
unresolved
no resolver link, observed 2026-08-03T16:38:11.406901Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

source=pdf_text observed=2026-08-03T16:38:11.406901Z digest=sha256:a6f8332fbef9379702331dd5508a0d574b0bfda9ee19524784c60e6176e7ed8d

Observation 1310200d-f523-4348-af12-eda6e69346bc · inbound

Fully Trainable Deep Differentiable Logic Gate Networks and Lookup Table Networks cites this paper.

Fully Trainable Deep Differentiable Logic Gate Networks and Lookup Table Networks LUTNet: Rethinking Inference in FPGA Soft Logic

Reference 17

Resolution
verified exact
local_arxiv, observed 2026-07-13T03:19:17.413327Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-09T06:31:02.800959+00:00.

source=arxiv_source observed=2026-07-13T03:18:58.883951Z digest=sha256:fa91c783247ddf8d7268a68ac7927ec7092b5ae5ab642b8569252e3e563ae384