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arxiv: 2606.13354 · v1 · pith:QBDUZ5TEnew · submitted 2026-06-11 · 💻 cs.AR · cs.DC· cs.NE

SupraSNN: Exploiting Synapse-Level Parallelism in Spiking Neural Network Accelerators through Co-Optimized Mapping and Scheduling

Seyed Sadra Ghavami , Mohammad Hossein Nikkhah , Mohammad Rasoul Roshanshah , Saeed Safari This is my paper

Pith reviewed 2026-06-27 05:20 UTC · model grok-4.3

classification 💻 cs.AR cs.DCcs.NE
keywords spiking neural networksFPGA acceleratorsynapse parallelismhardware-software co-designmapping and schedulingenergy efficiencysuperscalar architecture
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The pith

SupraSNN decouples synaptic and neuronal computations in an FPGA architecture to run multiple synapse operations in parallel through co-optimized mapping and scheduling.

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

Spiking neural networks generate many independent synaptic events that could execute simultaneously, yet most hardware keeps these steps tied to shared neuron state and loses the parallelism. SupraSNN draws from superscalar processor ideas to split the work: a Multi-Cast Tree fans spike data out to several Synapse Processing Units while a Merge Tree gathers results for one central Neuron Unit. A partitioning step first places the network onto the available memory, then a heuristic scheduler orders the synaptic executions to keep the units busy. On a Xilinx Zynq FPGA the resulting design records 149 microseconds per MNIST image at 0.025 millijoules and 47.6 percent lower latency than earlier FPGA accelerators.

Core claim

SupraSNN presents a hardware architecture that physically decouples synaptic computations from neuronal state updates, routing spikes through a Multi-Cast Tree to parallel Synapse Processing Units whose outputs are consolidated by a Merge Tree into a single Neuron Unit, with efficacy provided by a partitioning and heuristic scheduling framework that first maps the SNN under memory limits and then orders synaptic executions to maximize throughput and resource utilization.

What carries the argument

The decoupled superscalar-inspired architecture of Multi-Cast Tree, parallel Synapse Processing Units, Merge Tree, and unified Neuron Unit, supported by the partitioning and heuristic scheduling framework.

If this is right

  • The architecture reaches 149 microseconds inference latency and 0.025 millijoules per image (0.276 nanojoules per synapse) for a 93.44 percent accurate feedforward SNN on MNIST.
  • It delivers 47.6 percent lower latency and 5.6 times better energy efficiency than prior FPGA-based SNN accelerators.
  • A recurrent SNN on the Spiking Heidelberg Dataset achieves 1.41 milliseconds latency and 0.77 millijoules per sample at 71.82 percent accuracy on an XC7Z030 device.
  • Centralizing neuron dynamics in one unit reduces hardware overhead and avoids duplicating complex state logic across many units.

Where Pith is reading between the lines

These are editorial extensions of the paper, not claims the author makes directly.

  • The number of Synapse Processing Units could be increased on larger FPGAs to scale throughput for deeper networks while neuron hardware stays fixed.
  • The same separation of event routing from state update could be applied to other sparse, event-driven workloads beyond spiking networks.
  • Replacing the heuristic scheduler with an automated search might further improve utilization when memory constraints change.

Load-bearing premise

The partitioning and scheduling framework can map the SNN onto hardware and order synaptic executions to raise throughput and utilization without adding unaccounted overhead from the decoupled units.

What would settle it

Running the same MNIST-trained feedforward SNN on the Xilinx Zynq XC7Z020 and measuring inference latency above 149 microseconds or energy above 0.025 millijoules per image, or finding no improvement over the cited prior FPGA accelerators.

Figures

Figures reproduced from arXiv: 2606.13354 by Mohammad Hossein Nikkhah, Mohammad Rasoul Roshanshah, Saeed Safari, Seyed Sadra Ghavami.

Figure 1
Figure 1. Figure 1: Synaptic and neuronal computations in a discrete-time LIF neuron. Presynaptic input spikes are weighted [PITH_FULL_IMAGE:figures/full_fig_p005_1.png] view at source ↗
Figure 2
Figure 2. Figure 2: Common connectivity schemes in SNNs. (a) Feedforward SNNs with either sparse or fully-connected layers. [PITH_FULL_IMAGE:figures/full_fig_p005_2.png] view at source ↗
Figure 3
Figure 3. Figure 3: Overview block diagram of SupraSNN Hardware Architecture. [PITH_FULL_IMAGE:figures/full_fig_p007_3.png] view at source ↗
Figure 4
Figure 4. Figure 4: Abstract representation of the execution dataflow of a sample SNN on SupraSNN for one timestep. [PITH_FULL_IMAGE:figures/full_fig_p008_4.png] view at source ↗
Figure 5
Figure 5. Figure 5: (a) Micro architecture of a MC switch (b) Micro architecture of a ME switch. [PITH_FULL_IMAGE:figures/full_fig_p010_5.png] view at source ↗
Figure 6
Figure 6. Figure 6: Micro-architecture of SPU. Reception of an MC packet carrying the end index indicates that all spike events for the current timestep have been delivered. At this point, the SPU can safely assume that Spike Memory contains a complete and consistent snapshot of presynaptic activity and can begin synaptic computation (as explained in section 4.2 and shown in [PITH_FULL_IMAGE:figures/full_fig_p011_6.png] view at source ↗
Figure 7
Figure 7. Figure 7: Micro-architecture of Neuron Unit. 5 Centralized Neuron Unit As discussed previously, neuronal computation in SupraSNN is performed by a centralized Neuron Unit, which time-multiplexes neuron updates and maintains all neuron state. The LIF dynamics are implemented using simple add-and-shift operations derived from (2)–(5), minimizing area and power consumption [PITH_FULL_IMAGE:figures/full_fig_p013_7.png] view at source ↗
Figure 8
Figure 8. Figure 8: Flowchart of the software framework responsible for partitioning and scheduling. It has utilized a probabilistic [PITH_FULL_IMAGE:figures/full_fig_p015_8.png] view at source ↗
Figure 9
Figure 9. Figure 9: The overview of the probabilistic partitioning algorithm. The partitioning tree consists of switches with the [PITH_FULL_IMAGE:figures/full_fig_p016_9.png] view at source ↗
Figure 10
Figure 10. Figure 10: The overview of the heuristic scheduling algorithm. [PITH_FULL_IMAGE:figures/full_fig_p017_10.png] view at source ↗
Figure 11
Figure 11. Figure 11: (a) Accuracy of the 700–300–20 SNN architecture at different sparsity levels. (b) Accuracy of the quantized [PITH_FULL_IMAGE:figures/full_fig_p021_11.png] view at source ↗
Figure 12
Figure 12. Figure 12: (a) Total number of LUTs and FFs utilized by the trained SNN at different sparsity levels (b) [PITH_FULL_IMAGE:figures/full_fig_p022_12.png] view at source ↗
Figure 13
Figure 13. Figure 13: (a) Minimum required Operation Table depth determined by the proposed framework (directly related to inference latency) for different Unified Memory depths, compared with three baseline solutions. (b) Required memory of the framework’s solutions for different Unified Memory depths, compared with three baseline solutions. increases, approaching zero under fully relaxed constraints and demonstrating converg… view at source ↗
Figure 14
Figure 14. Figure 14: (a) Maximum and minimum numbers of synapses mapped to a single SPU for different [PITH_FULL_IMAGE:figures/full_fig_p026_14.png] view at source ↗
Figure 15
Figure 15. Figure 15: (a) Average number of post-neurons mapped to each SPU for different [PITH_FULL_IMAGE:figures/full_fig_p027_15.png] view at source ↗
read the original abstract

Spiking Neural Networks (SNNs) offer a brain-inspired path toward highly efficient computation, but their practical deployment is constrained by the challenge of managing and executing their massive parallelism on physical hardware. This problem mirrors the historical challenge in processor design of moving beyond serial execution, a barrier broken by superscalar architectures that dispatch multiple instructions to parallel functional units. Drawing inspiration from this paradigm, we introduce a hardware-software co-design framework that treats synaptic events as parallelizable micro-operations. We present SupraSNN, a superscalar-inspired architecture that achieves high synapse-level parallelism by physically decoupling synaptic and neuronal computations. Within this architecture, a Multi-Cast Tree routes spike data to multiple parallel Synapse Processing Units serve as the computational pipelines, while a Merge Tree consolidates distributed results for processing by a unified Neuron Unit--deliberately centralizing complex neuron state dynamics to mitigate hardware overhead and resource duplication. The efficacy of this architecture is enabled by a sophisticated partitioning and scheduling framework that first maps the SNN onto hardware respecting memory constraints, then heuristic scheduling determines the synaptic execution order, maximizing throughput and resource utilization. Implementing a feedforward SNN trained on MNIST (93.44% accuracy), SupraSNN achieves 149 $\mu s$ inference latency and 0.025 mJ per image (0.276 nJ per synapse) on the Xilinx Zynq XC7Z020 FPGA--delivering 47.6% lower latency and 5.6$\times$ better energy efficiency than prior FPGA-based SNN accelerators. Beyond vision tasks, a recurrent SNN on the Spiking Heidelberg Dataset (71.82% accuracy) achieves 1.41 ms latency and 0.77 mJ per sample on XC7Z030.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit. Tearing a paper down is the easy half of reading it; the pith above is the substance, this is the friction.

Referee Report

2 major / 2 minor

Summary. The paper proposes SupraSNN, a superscalar-inspired SNN accelerator architecture that decouples synaptic computation (via Multi-Cast Tree and parallel Synapse Processing Units) from neuronal state updates (via Merge Tree and centralized Neuron Unit) to exploit synapse-level parallelism. A co-optimized partitioning and heuristic scheduling framework maps feedforward and recurrent SNNs to FPGA hardware while respecting memory constraints. On a Xilinx Zynq XC7Z020, a MNIST-trained feedforward SNN (93.44% accuracy) achieves 149 μs latency and 0.025 mJ per image (0.276 nJ/synapse), claimed to be 47.6% lower latency and 5.6× more energy-efficient than prior FPGA SNN accelerators; a recurrent SNN on the Spiking Heidelberg Dataset reports 1.41 ms latency and 0.77 mJ per sample on XC7Z030.

Significance. If the overhead attribution holds, the work demonstrates a practical path to high synapse-level parallelism in SNN accelerators on resource-limited FPGAs, with concrete measured results that could influence co-design approaches for event-driven hardware. The explicit FPGA implementation and cross-dataset evaluation provide reproducible baselines for the field.

major comments (2)
  1. [Evaluation] Evaluation section: The headline claims of 149 μs latency and 0.025 mJ/image (with 47.6% and 5.6× improvements) are presented without a cycle-accurate breakdown or power measurement that isolates overheads from the Multi-Cast Tree routing, Merge Tree consolidation, heuristic scheduling, and buffering in the deliberately decoupled architecture versus an idealized fully-parallel execution. This directly affects whether the gains can be attributed to synapse-level parallelism.
  2. [Mapping and Scheduling Framework] Scheduling framework description: The heuristic scheduling that determines synaptic execution order after partitioning is described at a high level but lacks quantitative characterization of its runtime overhead, worst-case utilization loss, or comparison against an oracle schedule that would be feasible if memory constraints were ignored.
minor comments (2)
  1. [Abstract] The abstract states comparisons to 'prior FPGA-based SNN accelerators' without naming the specific baselines or their reported metrics in the same paragraph; this should be clarified for immediate context.
  2. [Results] Notation for energy per synapse (0.276 nJ per synapse) is introduced without an explicit equation showing how total energy is normalized by synapse count across the network.

Simulated Author's Rebuttal

2 responses · 0 unresolved

We thank the referee for the thoughtful and constructive comments. We address each major point below and indicate the revisions made to the manuscript.

read point-by-point responses

  1. Referee: [Evaluation] Evaluation section: The headline claims of 149 μs latency and 0.025 mJ/image (with 47.6% and 5.6× improvements) are presented without a cycle-accurate breakdown or power measurement that isolates overheads from the Multi-Cast Tree routing, Merge Tree consolidation, heuristic scheduling, and buffering in the deliberately decoupled architecture versus an idealized fully-parallel execution. This directly affects whether the gains can be attributed to synapse-level parallelism.

    Authors: The reported latency and energy figures are end-to-end measurements obtained from the actual FPGA implementation on the target device, which necessarily incorporate all overheads of the Multi-Cast Tree, Merge Tree, scheduling, and buffering. Direct comparison is made to prior FPGA SNN accelerators that likewise report full-system metrics. We agree that finer-grained attribution would strengthen the paper. In the revised manuscript we add a new subsection (Section 5.4) containing a cycle-accurate breakdown derived from the implemented design and Xilinx power analysis that quantifies the contribution of each architectural component relative to the overall gains. revision: yes

  2. Referee: [Mapping and Scheduling Framework] Scheduling framework description: The heuristic scheduling that determines synaptic execution order after partitioning is described at a high level but lacks quantitative characterization of its runtime overhead, worst-case utilization loss, or comparison against an oracle schedule that would be feasible if memory constraints were ignored.

    Authors: We acknowledge that the original description of the heuristic was high-level. The revised manuscript expands Section 4.3 with quantitative data: measured host-CPU runtime of the scheduler, observed utilization loss across the evaluated networks, and a comparison against an idealized schedule that relaxes memory constraints (showing the heuristic remains within a modest bound of the oracle). We note that a true memory-ignorant oracle cannot be realized on the resource-limited FPGA, but the added analysis bounds the impact of the memory-aware decisions. revision: yes

Circularity Check

0 steps flagged

No circularity: empirical FPGA measurements with no fitted predictions or self-referential derivations

full rationale

The paper reports measured latency (149 μs) and energy (0.025 mJ/image) from direct FPGA implementation of a feedforward SNN on MNIST, plus a recurrent SNN on SHD. The architecture description (Multi-Cast Tree, Synapse Processing Units, Merge Tree, partitioning + heuristic scheduling) is presented as a design choice whose efficacy is validated by hardware execution, not by any equation, parameter fit, or self-citation that reduces the reported numbers to the inputs by construction. No self-definitional loops, fitted-input predictions, or load-bearing self-citations appear in the provided text. The central claims rest on external benchmark comparisons and physical measurements rather than internal re-derivation.

Axiom & Free-Parameter Ledger

0 free parameters · 0 axioms · 0 invented entities

Abstract-only; no explicit free parameters, axioms, or invented entities identifiable beyond the high-level architectural description. The central claim rests on the unverified efficacy of the partitioning and scheduling framework.

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