Typed states for the displayed outbound observations.
Source: paper_references, paper_reference_links, observed 2026-08-14T12:45:40.680600Z
Paper Citation Record · LEDGER
As of 16 August 2026, this Paper Citation Record lists 10 of 10 outbound references and 0 inbound Pith citation observations for arXiv:1908.07413.
A citation records a reference. It does not transfer a finding from one paper to another.
Typed states for the displayed outbound observations.
Source: paper_references, paper_reference_links, observed 2026-08-14T12:45:40.680600Z
One-hop event checks from named stored sources.
Source: scholarly_work_events, retraction_status_cache, observed 2026-08-16T06:30:59.297886+00:00
Pith citing papers itemized under the disclosed page cap.
Source: paper_references, paper_reference_links
A source-named dated measurement, never combined with another source.
Source: cited_works
10 of 10 outbound references displayed
External citation measurements
No source-named external measurement is stored.
Observation 82cdd941-42e2-4e7f-96c9-d1d3300a9385 · outbound
Reference 1
Source-reported events for the cited work
No event found in the named queried sources as of 2026-08-16T06:30:59.297886+00:00.
Observation eabbaaec-e97e-4aab-a0a8-b263dd05b9a0 · outbound
A bi-directional Address-Event transceiver block for low-latency inter-chip communication in neuromorphic systems Unresolved cited work
Reference 2
Source-reported events for the cited work
No event found in the named queried sources as of 2026-08-16T06:30:59.297886+00:00.
Observation c4088fd9-c996-4232-803e-92c57b92a585 · outbound
A bi-directional Address-Event transceiver block for low-latency inter-chip communication in neuromorphic systems Unresolved cited work
Reference 3
Source-reported events for the cited work
Unavailable: canonical work link unavailable.
Observation b81d7912-3504-44c6-b2a8-748e7fb8b464 · outbound
A bi-directional Address-Event transceiver block for low-latency inter-chip communication in neuromorphic systems A scalable multi-core architecture with heterogeneous memory structures for Dynamic Neuromorphic Asynchronous Processors (DYNAPs)
Reference 4
Source-reported events for the cited work
No event found in the named queried sources as of 2026-08-16T06:30:59.297886+00:00.
Observation 20a5b629-f270-4358-b429-0a715a01725b · outbound
Reference 5
Source-reported events for the cited work
No event found in the named queried sources as of 2026-08-16T06:30:59.297886+00:00.
Observation 42c2dc2f-7c9c-47c1-ae37-43fd73295576 · outbound
A bi-directional Address-Event transceiver block for low-latency inter-chip communication in neuromorphic systems Unresolved cited work
Reference 6
Source-reported events for the cited work
No event found in the named queried sources as of 2026-08-16T06:30:59.297886+00:00.
Observation 7115714d-3ffd-47fd-b29d-94497da6c1bc · outbound
Reference 7
Source-reported events for the cited work
No event found in the named queried sources as of 2026-08-16T06:30:59.297886+00:00.
Observation 1b9787af-ada5-4107-8790-6bbae1bf8d2c · outbound
A bi-directional Address-Event transceiver block for low-latency inter-chip communication in neuromorphic systems Zamarre \ n o-Ramos, R
Reference 8
Source-reported events for the cited work
No event found in the named queried sources as of 2026-08-16T06:30:59.297886+00:00.
Observation 4ef05399-f76c-4afd-a2c2-28a52aaa1751 · outbound
Reference 9
Source-reported events for the cited work
No event found in the named queried sources as of 2026-08-16T06:30:59.297886+00:00.
Observation 17556cb3-0477-42c9-86a4-fb8493abeee6 · outbound
A bi-directional Address-Event transceiver block for low-latency inter-chip communication in neuromorphic systems C Î) :@@wm; c[&>Sc1h df e;r 9LF=̎ 6] 'i@6l6! Sǘ!tNۺ b4KT ǵXK lT/ ^ShЕ? ¡)ղlf* ? f bU' djا5he] lM柮ٳe h& B s ƛZ!A]th !8 u B440 B i !s8CTan/I BAM[B bc^gX ,XFS4
Reference 10
Source-reported events for the cited work
No event found in the named queried sources as of 2026-08-16T06:30:59.297886+00:00.
No inbound Pith citation observations are available.