Paper Citation Record · LEDGER

TicToc: Enabling Bandwidth-Efficient DRAM Caching for both Hits and Misses in Hybrid Memory Systems

As of 15 August 2026, this Paper Citation Record lists 54 of 54 outbound references and 1 inbound Pith citation observation for arXiv:1907.02184.

A citation records a reference. It does not transfer a finding from one paper to another.

pith.paper-citation-record.v1
1907.02184 v1

Coverage vector

measured 54 of 54 reference resolution

Typed states for the displayed outbound observations.

Source: paper_references, paper_reference_links, observed 2026-05-25T09:14:14.428280Z

measured 55 of 55 standing notices

One-hop event checks from named stored sources.

Source: scholarly_work_events, retraction_status_cache, observed 2026-08-15T06:32:42.880941+00:00

measured 1 of 1 inbound itemization

Pith citing papers itemized under the disclosed page cap.

Source: paper_references, paper_reference_links, observed 2026-05-25T09:14:14.428280Z

measured 0 of 1 external citation measurements

A source-named dated measurement, never combined with another source.

Source: pith, observed 2026-05-25T09:15:34.096604Z

Reference resolution

54 of 54 outbound references displayed

verified exact2
verified fuzzy47
unresolved2
parse uncertain0
malformed identifier2
metadata mismatch1

External citation measurements

No source-named external measurement is stored.

Outbound references

Observation 6c5d20bf-848c-480c-b586-e244fd8ad78d · outbound

This paper cites TicToc: Enabling Bandwidth-Efficient DRAM Caching for both Hits and Misses in Hybrid Memory Systems.

TicToc: Enabling Bandwidth-Efficient DRAM Caching for both Hits and Misses in Hybrid Memory Systems TicToc: Enabling Bandwidth-Efficient DRAM Caching for both Hits and Misses in Hybrid Memory Systems

Reference 1

Resolution: metadata mismatch; local_arxiv, observed 2026-05-25T09:15:34.100078Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-15T06:32:42.880941+00:00.

Observation 6f549c14-1923-4a57-a083-3324309a1ef1 · outbound

This paper cites A DRAM cache design has to balance multiple goals.

TicToc: Enabling Bandwidth-Efficient DRAM Caching for both Hits and Misses in Hybrid Memory Systems A DRAM cache design has to balance multiple goals

Reference 2

Resolution: verified fuzzy; raw_fallback, observed 2026-05-25T09:15:34.892190Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-15T06:32:42.880941+00:00.

Observation a7b0b9f2-506b-4629-b4c8-11e0c454291f · outbound

This paper cites We extend USIMM to include a DRAM cache.

TicToc: Enabling Bandwidth-Efficient DRAM Caching for both Hits and Misses in Hybrid Memory Systems We extend USIMM to include a DRAM cache

Reference 3

Resolution: malformed identifier; raw_fallback, observed 2026-05-25T09:15:34.903093Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-15T06:32:42.880941+00:00.

Observation 7e207e99-6760-4f02-a891-f35c5fe0fa8f · outbound

This paper cites Predicted-Dirty.

TicToc: Enabling Bandwidth-Efficient DRAM Caching for both Hits and Misses in Hybrid Memory Systems Predicted-Dirty

Reference 4

Resolution: verified fuzzy; raw_fallback, observed 2026-05-25T09:15:34.880199Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-15T06:32:42.880941+00:00.

Observation 2ec03ecf-0ec8-48e7-a1b4-877297f0c689 · outbound

This paper cites no DRAM cache.

TicToc: Enabling Bandwidth-Efficient DRAM Caching for both Hits and Misses in Hybrid Memory Systems no DRAM cache

Reference 5

Resolution: verified fuzzy; raw_fallback, observed 2026-05-25T09:15:34.856784Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-15T06:32:42.880941+00:00.

Observation ee4643c7-8b72-4c18-bfc0-3fca7947c683 · outbound

This paper cites Due to space constraints, we limit results to TicToc with dirty-bit optimizations.

TicToc: Enabling Bandwidth-Efficient DRAM Caching for both Hits and Misses in Hybrid Memory Systems Due to space constraints, we limit results to TicToc with dirty-bit optimizations

Reference 6

Resolution: malformed identifier; raw_fallback, observed 2026-05-25T09:15:34.872096Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-15T06:32:42.880941+00:00.

Observation 5d37c9f0-4f84-4337-ab8f-3fc0c1d2440f · outbound

This paper cites TIC designs [7, 11, 18, 30, 31, 32] organize their cache as direct-mapped and store tag inside the cacheline, such that one access can retrieve both tag and data.

TicToc: Enabling Bandwidth-Efficient DRAM Caching for both Hits and Misses in Hybrid Memory Systems TIC designs [7, 11, 18, 30, 31, 32] organize their cache as direct-mapped and store tag inside the cacheline, such that one access can retrieve both tag and data

Reference 7

Resolution: verified fuzzy; raw_fallback, observed 2026-05-25T09:15:34.962207Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-15T06:32:42.880941+00:00.

Observation 04021a64-ea89-4d97-8a6c-a4ff07f2f4c3 · outbound

This paper cites an unresolved cited work.

TicToc: Enabling Bandwidth-Efficient DRAM Caching for both Hits and Misses in Hybrid Memory Systems Unresolved cited work

Reference 8

Resolution: unresolved; raw_fallback, observed 2026-05-25T09:15:35.008718Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-15T06:32:42.880941+00:00.

Observation eaa44128-7d08-40d6-8809-21d785170d3e · outbound

This paper cites A revolutionary breakthrough in memory technology.

TicToc: Enabling Bandwidth-Efficient DRAM Caching for both Hits and Misses in Hybrid Memory Systems A revolutionary breakthrough in memory technology

Reference 9

Resolution: verified fuzzy; raw_fallback, observed 2026-05-25T09:15:34.974698Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-15T06:32:42.880941+00:00.

Observation acbe48c8-2b1e-416d-89a6-f810c162fd31 · outbound

This paper cites Basic Performance Measurements of the Intel Optane DC Persistent Memory Module.

TicToc: Enabling Bandwidth-Efficient DRAM Caching for both Hits and Misses in Hybrid Memory Systems Basic Performance Measurements of the Intel Optane DC Persistent Memory Module

Reference 10

Resolution: verified exact; arxiv_id, observed 2026-05-25T09:15:34.093632Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-15T06:32:42.880941+00:00.

Observation 40b51391-70f3-4786-b2d5-9908cc03e73e · outbound

This paper cites Intel© optane™ dc persistent memory operating modes explained.

TicToc: Enabling Bandwidth-Efficient DRAM Caching for both Hits and Misses in Hybrid Memory Systems Intel© optane™ dc persistent memory operating modes explained

Reference 11

Resolution: verified fuzzy; raw_fallback, observed 2026-05-25T09:15:34.949588Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-15T06:32:42.880941+00:00.

Observation 9f7881a7-4b4c-4ed4-871b-820fd40b97ed · outbound

This paper cites Scalable high performance main memory system using phase-change memory technology.

TicToc: Enabling Bandwidth-Efficient DRAM Caching for both Hits and Misses in Hybrid Memory Systems Scalable high performance main memory system using phase-change memory technology

Reference 12

Resolution: verified fuzzy; raw_fallback, observed 2026-05-25T09:15:34.952439Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-15T06:32:42.880941+00:00.

Observation 4890fad7-ef22-4e02-9a67-8a23e9fe64dd · outbound

This paper cites Pdram: A hybrid pram and dram main memory system.

TicToc: Enabling Bandwidth-Efficient DRAM Caching for both Hits and Misses in Hybrid Memory Systems Pdram: A hybrid pram and dram main memory system

Reference 13

Resolution: verified fuzzy; raw_fallback, observed 2026-05-25T09:15:34.943219Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-15T06:32:42.880941+00:00.

Observation 7e04496f-00fb-4c83-8f51-f12e299d9743 · outbound

This paper cites Architectural design for next generation heterogeneous memory systems.

TicToc: Enabling Bandwidth-Efficient DRAM Caching for both Hits and Misses in Hybrid Memory Systems Architectural design for next generation heterogeneous memory systems

Reference 14

Resolution: verified fuzzy; raw_fallback, observed 2026-05-25T09:15:34.946439Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-15T06:32:42.880941+00:00.

Observation e804308b-8830-400b-aab3-f1083033ff3c · outbound

This paper cites Fundamental latency trade-off in architecting dram caches: Outperforming impractical sram-tags with a simple and practical design.

TicToc: Enabling Bandwidth-Efficient DRAM Caching for both Hits and Misses in Hybrid Memory Systems Fundamental latency trade-off in architecting dram caches: Outperforming impractical sram-tags with a simple and practical design

Reference 15

Resolution: verified fuzzy; raw_fallback, observed 2026-05-25T09:15:34.958477Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-15T06:32:42.880941+00:00.

Observation 63942a1e-0df1-407d-a41c-3a40de45ee16 · outbound

This paper cites Enabling efﬁcient and scalable hybrid memories using ﬁne-granularity dram cache management.

TicToc: Enabling Bandwidth-Efficient DRAM Caching for both Hits and Misses in Hybrid Memory Systems Enabling efﬁcient and scalable hybrid memories using ﬁne-granularity dram cache management

Reference 16

Resolution: verified fuzzy; raw_fallback, observed 2026-05-25T09:15:34.971844Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-15T06:32:42.880941+00:00.

Observation d09eeb6b-13a5-4422-ad7e-fb12e7b3d273 · outbound

This paper cites Efﬁciently enabling conventional block sizes for very large die-stacked dram caches.

TicToc: Enabling Bandwidth-Efficient DRAM Caching for both Hits and Misses in Hybrid Memory Systems Efﬁciently enabling conventional block sizes for very large die-stacked dram caches

Reference 17

Resolution: verified fuzzy; raw_fallback, observed 2026-05-25T09:15:35.002636Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-15T06:32:42.880941+00:00.

Observation e0dab4a0-4322-451d-a049-189ace4d8760 · outbound

This paper cites Die-stacked dram caches for servers: Hit ratio, latency, or bandwidth? have it all with footprint cache.

TicToc: Enabling Bandwidth-Efficient DRAM Caching for both Hits and Misses in Hybrid Memory Systems Die-stacked dram caches for servers: Hit ratio, latency, or bandwidth? have it all with footprint cache

Reference 18

Resolution: verified fuzzy; raw_fallback, observed 2026-05-25T09:15:35.040455Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-15T06:32:42.880941+00:00.

Observation c409ef54-b4d8-45b9-8ad8-6a8ed3d4df16 · outbound

This paper cites Knights landing: Second-generation intel xeon phi product.

TicToc: Enabling Bandwidth-Efficient DRAM Caching for both Hits and Misses in Hybrid Memory Systems Knights landing: Second-generation intel xeon phi product

Reference 19

Resolution: verified fuzzy; raw_fallback, observed 2026-05-25T09:15:34.859535Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-15T06:32:42.880941+00:00.

Observation 329de65a-a141-4d70-8a43-5400b9095362 · outbound

This paper cites Resilient die-stacked dram caches.

TicToc: Enabling Bandwidth-Efficient DRAM Caching for both Hits and Misses in Hybrid Memory Systems Resilient die-stacked dram caches

Reference 20

Resolution: verified fuzzy; raw_fallback, observed 2026-05-25T09:15:34.882738Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-15T06:32:42.880941+00:00.

Observation aa3b5fb4-d823-416d-9b81-b4ee23c8eb5f · outbound

This paper cites Unison cache: A scalable and effective die-stacked dram cache.

TicToc: Enabling Bandwidth-Efficient DRAM Caching for both Hits and Misses in Hybrid Memory Systems Unison cache: A scalable and effective die-stacked dram cache

Reference 21

Resolution: verified fuzzy; raw_fallback, observed 2026-05-25T09:15:34.906049Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-15T06:32:42.880941+00:00.

Observation 12e9bd5f-646e-42ed-b7b3-b6c8aeed597d · outbound

This paper cites High bandwidth memory (hbm) dram.

TicToc: Enabling Bandwidth-Efficient DRAM Caching for both Hits and Misses in Hybrid Memory Systems High bandwidth memory (hbm) dram

Reference 22

Resolution: verified fuzzy; raw_fallback, observed 2026-05-25T09:15:35.045688Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-15T06:32:42.880941+00:00.

Observation 47747a0c-d49c-426d-bcf8-02855811bf3c · outbound

This paper cites an unresolved cited work.

TicToc: Enabling Bandwidth-Efficient DRAM Caching for both Hits and Misses in Hybrid Memory Systems Unresolved cited work

Reference 23

Resolution: unresolved; raw_fallback, observed 2026-05-25T09:15:35.011438Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-15T06:32:42.880941+00:00.

Observation 133d693a-322b-4a90-bdd9-3ef01b671af9 · outbound

This paper cites Intel’s crazy-fast 3d xpoint optane memory heads for ddr slots (but with a catch).

TicToc: Enabling Bandwidth-Efficient DRAM Caching for both Hits and Misses in Hybrid Memory Systems Intel’s crazy-fast 3d xpoint optane memory heads for ddr slots (but with a catch)

Reference 24

Resolution: verified fuzzy; raw_fallback, observed 2026-05-25T09:15:35.018163Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-15T06:32:42.880941+00:00.

Observation 870c28c4-0d29-44b9-9e0d-1e9e5c6fea2f · outbound

This paper cites Cascade lake: Next generation intel xeon scalable processor.

TicToc: Enabling Bandwidth-Efficient DRAM Caching for both Hits and Misses in Hybrid Memory Systems Cascade lake: Next generation intel xeon scalable processor

Reference 25

Resolution: verified fuzzy; raw_fallback, observed 2026-05-25T09:15:35.025539Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-15T06:32:42.880941+00:00.

Observation 1a2d3e65-ad86-45fd-9c1b-aeeab8de5f8c · outbound

This paper cites Bear: Techniques for mitigating bandwidth bloat in gigascale dram caches.

TicToc: Enabling Bandwidth-Efficient DRAM Caching for both Hits and Misses in Hybrid Memory Systems Bear: Techniques for mitigating bandwidth bloat in gigascale dram caches

Reference 26

Resolution: verified fuzzy; raw_fallback, observed 2026-05-25T09:15:35.050355Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-15T06:32:42.880941+00:00.

Observation a3a69390-25d7-4a56-ae9c-8e8cac72e353 · outbound

This paper cites Sector cache design and performance.

TicToc: Enabling Bandwidth-Efficient DRAM Caching for both Hits and Misses in Hybrid Memory Systems Sector cache design and performance

Reference 27

Resolution: verified fuzzy; raw_fallback, observed 2026-05-25T09:15:35.005727Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-15T06:32:42.880941+00:00.

Observation fb32c781-6445-4f80-9f60-54edb2e8e279 · outbound

This paper cites Usimm: the utah simulated memory module.

TicToc: Enabling Bandwidth-Efficient DRAM Caching for both Hits and Misses in Hybrid Memory Systems Usimm: the utah simulated memory module

Reference 28

Resolution: verified fuzzy; raw_fallback, observed 2026-05-25T09:15:34.996370Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-15T06:32:42.880941+00:00.

Observation 030e5ef1-2f72-4fb2-ab67-e1a034fbe0fc · outbound

This paper cites Fact sheet: New intel architectures and technologies target expanded market opportunities.

TicToc: Enabling Bandwidth-Efficient DRAM Caching for both Hits and Misses in Hybrid Memory Systems Fact sheet: New intel architectures and technologies target expanded market opportunities

Reference 29

Resolution: verified fuzzy; raw_fallback, observed 2026-05-25T09:15:34.989763Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-15T06:32:42.880941+00:00.

Observation 00e5df59-f339-4395-a1a0-3c41f54ed414 · outbound

This paper cites Pinpointing representative portions of large intel itanium programs with dynamic instrumentation.

TicToc: Enabling Bandwidth-Efficient DRAM Caching for both Hits and Misses in Hybrid Memory Systems Pinpointing representative portions of large intel itanium programs with dynamic instrumentation

Reference 30

Resolution: verified fuzzy; raw_fallback, observed 2026-05-25T09:15:34.986582Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-15T06:32:42.880941+00:00.

Observation 6f1e9bf4-440a-4e1e-880a-c537e3188331 · outbound

This paper cites Spec cpu2006 benchmark descriptions.

TicToc: Enabling Bandwidth-Efficient DRAM Caching for both Hits and Misses in Hybrid Memory Systems Spec cpu2006 benchmark descriptions

Reference 31

Resolution: verified fuzzy; raw_fallback, observed 2026-05-25T09:15:35.014072Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-15T06:32:42.880941+00:00.

Observation c1b9ecec-0fca-411b-93df-caff54d09816 · outbound

This paper cites The GAP Benchmark Suite.

TicToc: Enabling Bandwidth-Efficient DRAM Caching for both Hits and Misses in Hybrid Memory Systems The GAP Benchmark Suite

Reference 32

Resolution: verified exact; local_arxiv, observed 2026-05-25T09:15:34.105476Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-15T06:32:42.880941+00:00.

Observation ddb166d6-0069-4327-95c3-feb0bc71ca0d · outbound

This paper cites A mostly-clean dram cache for effective hit speculation and self-balancing dispatch.

TicToc: Enabling Bandwidth-Efficient DRAM Caching for both Hits and Misses in Hybrid Memory Systems A mostly-clean dram cache for effective hit speculation and self-balancing dispatch

Reference 33

Resolution: verified fuzzy; raw_fallback, observed 2026-05-25T09:15:34.993231Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-15T06:32:42.880941+00:00.

Observation 5e8bd4ff-6353-4abf-9ce5-2325049f8d5c · outbound

This paper cites Ship: Signature-based hit predictor for high performance caching.

TicToc: Enabling Bandwidth-Efficient DRAM Caching for both Hits and Misses in Hybrid Memory Systems Ship: Signature-based hit predictor for high performance caching

Reference 34

Resolution: verified fuzzy; raw_fallback, observed 2026-05-25T09:15:34.999435Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-15T06:32:42.880941+00:00.

Observation ed333fc1-e219-4f6b-ba7b-42bd80758e27 · outbound

This paper cites Ship++: Enhancing signature-based hit predictor for improved cache performance.

TicToc: Enabling Bandwidth-Efficient DRAM Caching for both Hits and Misses in Hybrid Memory Systems Ship++: Enhancing signature-based hit predictor for improved cache performance

Reference 35

Resolution: verified fuzzy; raw_fallback, observed 2026-05-25T09:15:34.977663Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-15T06:32:42.880941+00:00.

Observation 1d9a3b3d-ada7-4291-9573-ced78b867c19 · outbound

This paper cites Counter-based cache replacement and bypassing algorithms.

TicToc: Enabling Bandwidth-Efficient DRAM Caching for both Hits and Misses in Hybrid Memory Systems Counter-based cache replacement and bypassing algorithms

Reference 36

Resolution: verified fuzzy; raw_fallback, observed 2026-05-25T09:15:35.031023Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-15T06:32:42.880941+00:00.

Observation f11c70e8-4a4d-4d07-93b3-afe87128cd77 · outbound

This paper cites A dueling segmented lru replacement algorithm with adaptive bypassing.

TicToc: Enabling Bandwidth-Efficient DRAM Caching for both Hits and Misses in Hybrid Memory Systems A dueling segmented lru replacement algorithm with adaptive bypassing

Reference 37

Resolution: verified fuzzy; raw_fallback, observed 2026-05-25T09:15:34.965407Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-15T06:32:42.880941+00:00.

Observation 4dd5fc8e-f437-47af-9b2b-f100697392d2 · outbound

This paper cites Accord: Enabling associativity for gigascale dram caches by coordinating way-install and way-prediction.

TicToc: Enabling Bandwidth-Efficient DRAM Caching for both Hits and Misses in Hybrid Memory Systems Accord: Enabling associativity for gigascale dram caches by coordinating way-install and way-prediction

Reference 38

Resolution: verified fuzzy; raw_fallback, observed 2026-05-25T09:15:34.955523Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-15T06:32:42.880941+00:00.

Observation b87c7ccd-10ae-4ffb-befb-e6c2589d5a26 · outbound

This paper cites Candy: Enabling coherent dram caches for multi-node systems.

TicToc: Enabling Bandwidth-Efficient DRAM Caching for both Hits and Misses in Hybrid Memory Systems Candy: Enabling coherent dram caches for multi-node systems

Reference 39

Resolution: verified fuzzy; raw_fallback, observed 2026-05-25T09:15:34.968759Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-15T06:32:42.880941+00:00.

Observation cb1c870f-ec74-466b-a2df-840f80ee010f · outbound

This paper cites Dice: Compressing dram caches for bandwidth and capacity.

TicToc: Enabling Bandwidth-Efficient DRAM Caching for both Hits and Misses in Hybrid Memory Systems Dice: Compressing dram caches for bandwidth and capacity

Reference 40

Resolution: verified fuzzy; raw_fallback, observed 2026-05-25T09:15:34.980580Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-15T06:32:42.880941+00:00.

Observation a42b46c0-6ee1-4553-be68-3d52b5df6e1d · outbound

This paper cites Atcache: reducing dram cache latency via a small sram tag cache.

TicToc: Enabling Bandwidth-Efficient DRAM Caching for both Hits and Misses in Hybrid Memory Systems Atcache: reducing dram cache latency via a small sram tag cache

Reference 41

Resolution: verified fuzzy; raw_fallback, observed 2026-05-25T09:15:34.983430Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-15T06:32:42.880941+00:00.

Observation 8c7c3e12-9ddf-482b-b48c-4b87338187fe · outbound

This paper cites Building a low latency, highly associative dram cache with the buffered way predictor.

TicToc: Enabling Bandwidth-Efficient DRAM Caching for both Hits and Misses in Hybrid Memory Systems Building a low latency, highly associative dram cache with the buffered way predictor

Reference 42

Resolution: verified fuzzy; raw_fallback, observed 2026-05-25T09:15:35.036126Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-15T06:32:42.880941+00:00.

Observation f1b843d4-7250-4a11-bfef-4b7e07841935 · outbound

This paper cites A fully associative, tagless dram cache.

TicToc: Enabling Bandwidth-Efficient DRAM Caching for both Hits and Misses in Hybrid Memory Systems A fully associative, tagless dram cache

Reference 43

Resolution: verified fuzzy; raw_fallback, observed 2026-05-25T09:15:34.897876Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-15T06:32:42.880941+00:00.

Observation 9d61dc34-1bf4-4d1f-a5d6-df8ef435b216 · outbound

This paper cites Efﬁcient footprint caching for tagless dram caches.

TicToc: Enabling Bandwidth-Efficient DRAM Caching for both Hits and Misses in Hybrid Memory Systems Efﬁcient footprint caching for tagless dram caches

Reference 44

Resolution: verified fuzzy; raw_fallback, observed 2026-05-25T09:15:34.900661Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-15T06:32:42.880941+00:00.

Observation 4cc89b40-93c4-44ee-8321-69c71fc24eee · outbound

This paper cites Challenges in heterogeneous die-stacked and off-chip memory systems.

TicToc: Enabling Bandwidth-Efficient DRAM Caching for both Hits and Misses in Hybrid Memory Systems Challenges in heterogeneous die-stacked and off-chip memory systems

Reference 45

Resolution: verified fuzzy; raw_fallback, observed 2026-05-25T09:15:34.935875Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-15T06:32:42.880941+00:00.

Observation f52122f2-6696-42c3-a26d-6031bba0d199 · outbound

This paper cites Banshee: Bandwidth-efﬁcient dram caching via software/hardware cooperation.

TicToc: Enabling Bandwidth-Efficient DRAM Caching for both Hits and Misses in Hybrid Memory Systems Banshee: Bandwidth-efﬁcient dram caching via software/hardware cooperation

Reference 46

Resolution: verified fuzzy; raw_fallback, observed 2026-05-25T09:15:34.895093Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-15T06:32:42.880941+00:00.

Observation 62e42c59-0818-4a4a-9dcc-d9228b83999e · outbound

This paper cites Cameo: A two-level memory organization with capacity of main memory and ﬂexibility of hardware-managed cache.

TicToc: Enabling Bandwidth-Efficient DRAM Caching for both Hits and Misses in Hybrid Memory Systems Cameo: A two-level memory organization with capacity of main memory and ﬂexibility of hardware-managed cache

Reference 47

Resolution: verified fuzzy; raw_fallback, observed 2026-05-25T09:15:34.939657Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-15T06:32:42.880941+00:00.

Observation d6d9dc2a-2872-490c-8921-8b02c21dcb4b · outbound

This paper cites Transparent hardware management of stacked dram as part of memory.

TicToc: Enabling Bandwidth-Efficient DRAM Caching for both Hits and Misses in Hybrid Memory Systems Transparent hardware management of stacked dram as part of memory

Reference 48

Resolution: verified fuzzy; raw_fallback, observed 2026-05-25T09:15:34.877281Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-15T06:32:42.880941+00:00.

Observation af917269-e13f-4e03-b00e-ad36d7767c11 · outbound

This paper cites Silc-fm: Subblocked interleaved cache-like ﬂat memory organization.

TicToc: Enabling Bandwidth-Efficient DRAM Caching for both Hits and Misses in Hybrid Memory Systems Silc-fm: Subblocked interleaved cache-like ﬂat memory organization

Reference 49

Resolution: verified fuzzy; raw_fallback, observed 2026-05-25T09:15:34.865334Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-15T06:32:42.880941+00:00.

Observation 92b3e468-8ca5-41f8-8f9d-1c54d8424945 · outbound

This paper cites Mempod: A clustered architecture for efﬁcient and scalable migration in ﬂat address space multi-level memories.

TicToc: Enabling Bandwidth-Efficient DRAM Caching for both Hits and Misses in Hybrid Memory Systems Mempod: A clustered architecture for efﬁcient and scalable migration in ﬂat address space multi-level memories

Reference 50

Resolution: verified fuzzy; raw_fallback, observed 2026-05-25T09:15:34.889255Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-15T06:32:42.880941+00:00.

Observation 82ca9846-f2ca-4b9e-9837-9b44b73b0022 · outbound

This paper cites Pageseer: Using page walks to trigger page swaps in hybrid memory systems.

TicToc: Enabling Bandwidth-Efficient DRAM Caching for both Hits and Misses in Hybrid Memory Systems Pageseer: Using page walks to trigger page swaps in hybrid memory systems

Reference 51

Resolution: verified fuzzy; raw_fallback, observed 2026-05-25T09:15:34.862201Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-15T06:32:42.880941+00:00.

Observation a0bec327-fff5-45ea-a2f2-243082220284 · outbound

This paper cites C3d: Mitigating the numa bottleneck via coherent dram caches.

TicToc: Enabling Bandwidth-Efficient DRAM Caching for both Hits and Misses in Hybrid Memory Systems C3d: Mitigating the numa bottleneck via coherent dram caches

Reference 52

Resolution: verified fuzzy; raw_fallback, observed 2026-05-25T09:15:34.869088Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-15T06:32:42.880941+00:00.

Observation 1732a02f-eb05-479b-9a8c-0cfd2c62b599 · outbound

This paper cites Cache coherence for GPU architectures.

TicToc: Enabling Bandwidth-Efficient DRAM Caching for both Hits and Misses in Hybrid Memory Systems Cache coherence for GPU architectures

Reference 53

Resolution: verified fuzzy; raw_fallback, observed 2026-05-25T09:15:34.874556Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-15T06:32:42.880941+00:00.

Observation a6a79781-481b-44b1-9345-6fec6375971a · outbound

This paper cites Combining hw/sw mechanisms to improve numa performance of multi-gpu systems.

TicToc: Enabling Bandwidth-Efficient DRAM Caching for both Hits and Misses in Hybrid Memory Systems Combining hw/sw mechanisms to improve numa performance of multi-gpu systems

Reference 54

Resolution: verified fuzzy; raw_fallback, observed 2026-05-25T09:15:34.886152Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-15T06:32:42.880941+00:00.

Pith citing papers

Observation 6c5d20bf-848c-480c-b586-e244fd8ad78d · inbound