Pith. sign in

REVIEW 1 major objections 4 minor 32 references

NetlistBench: Evaluating LLM Reliability in SPICE Netlist Recognition and Manipulation

T0 review · 1 major / 4 minor · reviewed 2026-08-16 · deepseek-v4-flash

Challenge this review Re-run · record.json Download PDF Read on arXiv ↗ Review JSON

Pith's one-line read NetlistBench makes the case that LLM reliability on SPICE netlists is a distinct bottleneck: local edits pass near-perfectly, while device addition, equivalence judgment, and multi-step compound edits fail at high rates.

desk verdict NetlistBench is a credible, reproducible benchmark that isolates netlist-level LLM reliability; the exact-name scoring rule is a real but minor soft spot, not a flaw that breaks the headline. read the letter →

arxiv 2608.12197 v1 pith:QPGXJGAR submitted 2026-08-12 eess.SY cs.AIcs.SY

Jiarui Ma , Jianghan Wang , Yuheng Ma , Ziyi Zhuang , Xiaoguang Liu This is my paper · ORCID
classification eess.SYcs.AIcs.SY
keywords LargelanguagemodelsSPICEnetlistsnetlistrecognitionmanipulationelectronicdesignautomationstructure-awareevaluationanalogcircuitsbenchmark
verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

NetlistBench asks whether large language models can be relied on to read and modify SPICE netlists as structured circuit objects, not merely as text. To answer it, the paper constructs 2,342 test cases across 24 task families and grades every output with a deterministic oracle that compares the parsed circuit structure against a canonical target. The results show a sharp split: local edits such as parameter changes and device removal pass 96%–100% of the time, while adding a device passes only 41%–83%, equivalence judgment 49%–90%, and multi-step compound edits degrade as the horizon grows—the strongest tested model falls from 80% at three steps to 26% at fifteen. Reasoning modes improve weaker models substantially but do not stop the long-horizon collapse. If the benchmark is right, LLMs are not yet safe as standalone unverified netlist editors, and production workflows should verify structure after every edit.

What carries the argument

The load-bearing machinery is a canonical intermediate representation (IR) of a SPICE netlist: a normalized structure that lists every device by kind with ordered terminal nodes and parameters, plus top-level directives and, for hierarchical circuits, each subcircuit's port interface and internal devices. A deterministic structure-aware oracle passes an output only if its IR matches the target IR up to fixed semantic-preserving normalizations—numeric parameter equivalence, unordered terminals for symmetric two-terminal passives, and identical hierarchy and directives. This exact-match rule is what encodes the locality constraints of editing: renaming an untouched node, dropping or duplicating a device, or perturbing an unrelated parameter all surface as IR mismatches and fail the case. Equivalence-judgment labels are audited separately by projecting the IR onto a labeled bipartite device–net graph and running a VF2 graph-isomorphism check on the constructed ground truth; the oracle itself does not use isomorphism, because matching up to renaming would mask the name- and locality-violations the edit tasks are designed to catch.

What would settle it

Take a random sample of NetlistBench manipulation and compound-edit cases, have experienced analog designers perform the same edits without seeing the reference targets, and grade their outputs with the canonical-IR oracle; if a substantial fraction of human-accepted, simulation-valid outputs are rejected, the exact-match rule is too strict and the reported degradation partly reflects the scoring rule. A complementary experiment would give the model its own output after each step of a compound edit and ask it to verify or repair before continuing; sharp recovery at 15 steps would show the bottleneck is missing self-verification rather than absent circuit representation.

Watch

Extended reading notes

Core claim

The central discovery is a structure-preservation bottleneck. On NetlistBench, models are reliable when the required operation touches only explicit text—a parameter value, a device statement, a listed port—but reliability drops when the operation requires maintaining an implicit circuit graph: terminal-role bindings, node identities, subcircuit port order, and edit locality across dependent changes. The benchmark reports this in numbers: device removal and parameter editing reach 96%–100% across models, device addition 41%–83%, connectivity editing 47%–97%, and structural equivalence judgment 49%–90%. Compound editing makes the bottleneck visible: with three dependent edits, the best model passes 80%; with fifteen, it passes 26%, and most models fall to 0%–6%. The paper's further claim is causal rather than incidental: these failures are not format or syntax errors but structural ones—omitted edits, duplicated edits, unintended terminal rebinding, and topology drift—which match the representational requirement that connectivity is encoded implicitly by shared node names.

Load-bearing premise

The benchmark assumes each manipulation instruction has exactly one acceptable target netlist and that a correct edit must match that target after standard formatting normalizations; if a real edit instruction allows electrically valid outcomes that differ structurally beyond those normalizations, the grading would mark correct edits as failures and understate how reliable the models really are.

Editorial extensions

If this is right

  • Current LLMs should not be used as standalone unverified SPICE netlist editors; any workflow that automates netlist changes should verify structure after each edit.
  • High accuracy on isolated edits does not transfer to multi-step reliability: with dependent edits, joint success falls to near zero at 15 steps even for models whose single-edit performance is near perfect.
  • Reasoning modes (native thinking and chain-of-thought) improve aggregate pass rates substantially—up to roughly 30–40 points in the paired subset—but long-horizon compound editing, hierarchical operations, and relational structural queries remain failure-prone.
  • Netlist reliability is a distinct evaluation axis: models can follow the required output format while inserting incorrect circuit facts, so format compliance does not imply structural correctness.
  • Representation choice matters less than reasoning: switching from SPICE to PySpice improves one model overall but not the other, and neither mitigation removes the structure-preservation bottleneck.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

  • If the benchmark's exact-match oracle were replaced with a semantic equivalence check that accepts any electrically valid outcome, absolute pass rates might rise, but the qualitative ordering—local edits above additions above equivalence above long compound edits—would likely survive because the observed failures are structural and systematic, not marginal.
  • The oracle is a natural verification critic for a repair loop: because it returns deterministic pass/fail with no model involved, NetlistBench could be turned into a training or decoding signal for stepwise netlist editing, where the model edits, checks, and re-edits until the IR matches.
  • The paper's explanation that implicit connectivity in flat text causes the bottleneck predicts a testable extension: representing netlists with explicit graph or adjacency structure should improve connectivity-sensitive and compound tasks more than it improves parameter or removal tasks.
Share X Bluesky LinkedIn Reddit HN

Signed reviews

No signed human review yet.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Referee Report

1 major / 4 minor

Summary. NetlistBench introduces a structure-verified benchmark for evaluating LLM reliability on SPICE netlist recognition and manipulation. It contains 2,342 cases across 24 task families, generated by a deterministic template pipeline from AnalogGenie and ALIGN netlists. Model outputs are scored by a canonical intermediate-representation oracle that compares device sets, terminal bindings, parameters, directives, and hierarchy up to fixed normalizations. The authors evaluate six non-thinking LLMs plus reasoning-enabled variants, reporting that simple local edits (device removal, parameter editing) reach 96–100% accuracy, while device addition (41–83%), equivalence judgment (49–90%), relational recognition queries, and compound editing degrade substantially, with performance falling as the number of dependent edits increases. They conclude that netlist reliability is a distinct bottleneck and that current LLMs should not be treated as standalone unverified netlist editors.

Significance. If the measurements hold, NetlistBench fills a real gap by isolating representation-level netlist reliability from high-level circuit design reasoning. The benchmark's strengths are substantial: a deterministic, semantics-aware oracle; VF2 validation of the equivalence-judgment labels; case-weighted aggregates; explicit Wilson intervals for aggregate ablations; and a public release with cases, oracle code, and prompt templates. The headline contrast between local edits and structure-sensitive operations is a falsifiable and practically relevant prediction, and the paper's cautious statements about reasoning-mode improvements are appropriate. The main risk to the validity of one headline number is the exact-name grading rule for newly introduced devices, discussed below.

major comments (1)
  1. [§3.2, §3.3, Table 2] The oracle in §3.3 requires that the output and reference contain 'the same set of named devices,' so Device add and Device replace are graded by exact instance-name identity. This is fair only if the task instruction itself fixes the instance name of the newly introduced (or replacement) device. Section 3.2 states that each manipulation instance has a uniquely determined target netlist, but the paper does not quote the device-add or device-replace prompt templates or state that the new device name is specified. If the prompt says, for example, 'add a 10k resistor between n1 and n2' without naming it, then any unused instance name is a semantically valid SPICE edit, and the reported Device add range of 41–83% in Table 2 is a lower bound rather than an unbiased reliability estimate. Please state the naming convention explicitly, include the relevant templates, and provide a robustness analysis that scores newly introduced devices up to consistent renaming (or justify why name identity is the intended semantics for these tasks).
minor comments (4)
  1. [Table 2] Per-family Wilson confidence intervals are not shown; with n=100, intervals of roughly ±10 percentage points are material for the mid-range families such as Device add, Node incidence, and Equiv. judge. Adding them would make the cross-model comparisons easier to interpret.
  2. [Figure 3 and §3.4] A complete prompt template for at least one manipulation family, ideally Device add, would make the scoring rule checkable without downloading the repository; the current figure examples do not show the exact instruction format.
  3. [§4.3] The compound-editing tasks are described as 'long-horizon' editing, but all 3–15 edits are delivered in a single instruction and the model emits one final netlist; this is a joint multi-edit instruction-following task rather than an autoregressive multi-turn execution task. The text should clarify this distinction, since the cited prior work on long-horizon execution concerns multi-turn settings.
  4. [Abstract and Figure 2] There are minor formatting issues, including 'We presentNetlistBench' in the abstract (missing space) and the dense legend in Table 2; these should be cleaned up in the final version.

Circularity Check

0 steps flagged · score 0.0 of 10

No circularity found: NetlistBench is an empirical measurement benchmark with a transparent, deterministic oracle and no fitted parameters or derivation chain.

full rationale

NetlistBench is an empirical benchmark paper rather than a derivation, so the circularity patterns do not apply. The central claims—that pass rates vary by operation type and that compound editing degrades with horizon—are measurements obtained by a deterministic structure-aware oracle over fixed prompts, source netlists, and target instances; none of the measured outcomes is used to define the oracle, and no parameter is fitted to the reported test results. The exact-match canonical-IR grading rule is a transparent scoring convention: it is the definition of correctness used for the benchmark, not a conclusion derived from that correctness. The equivalence-judgment ground-truth labels are audited with a VF2 graph-isomorphism check, but the paper explicitly states that this check is used only to validate generated labels and is not part of scoring model outputs, so it cannot force the reported pass rates. The concern that exact-name grading may understate device-add pass rates is a measurement-validity or scoring-fairness question, not a case where the claimed result is equivalent to its inputs by construction. The limitations section openly restricts the scope to circuit-block-level analog netlists and template-generated instructions, which limits external generalization but does not indicate internal circularity. There is no load-bearing self-citation: the cited prior circuit benchmarks and tools are background evidence, and the authors' own prior work is not invoked as the justification for any result. The repository, seeded generation scripts, prompt templates, and deterministic oracle are made public, allowing independent reproduction. Therefore no circular step is identifiable in this paper.

Assumptions & free parameters 0 free parameters · 3 assumptions · 0 invented entities

The benchmark is an empirical measurement with no fitted parameters. Its validity rests on design assumptions: unique canonical targets, representativeness of the analog-CMOS corpus, and single-query sampling. These are documented in the paper and do not amount to circularity.

assumptions (3)
  • domain assumption A manipulation task has a uniquely determined correct target netlist under the canonical IR exact-match rule.
    Section 3.2 constructs Y_target as uniquely determined and Section 3.3 grades by exact IR match after fixed normalizations; alternative valid edits count as failures.
  • domain assumption The source netlists from AnalogGenie and ALIGN represent the structure-level SPICE operations the benchmark claims to measure.
    Section 3.1 restricts the corpus to flat and hierarchical analog CMOS blocks; Section 5.2 acknowledges results may not transfer to RF, power, digital, or mixed-signal netlists.
  • domain assumption A single deterministic query per model-case is treated as the model's reliability on that case.
    Section 4.1 states each model is queried once per case with deterministic decoding; Section 5.2 notes results characterize tested API snapshots rather than complete output distributions.

how reviews work

0 comments
Cite this review

Pith. "Pith review of NetlistBench: Evaluating LLM Reliability in SPICE Netlist Recognition and Manipulation." pith.science (2026). https://pith.science/paper/QPGXJGAR

@misc{pith2026260812197,
  author       = {Pith},
  title        = {Pith review of: NetlistBench: Evaluating LLM Reliability in SPICE Netlist Recognition and Manipulation},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/QPGXJGAR}},
  note         = {Machine review of arXiv:2608.12197}
}
abstract

Large Language Models (LLMs) are increasingly used in circuit design workflows, yet their reliability on simulator-facing SPICE netlist recognition and manipulation remains poorly understood and is rarely separated from high-level design reasoning. Although netlists are textual, they encode structured circuit objects through topology and parameters. We present \textbf{NetlistBench}, a structure-verified benchmark for SPICE netlist recognition and manipulation. NetlistBench contains 2,342 cases across 24 task families, covering parameter and connectivity recognition and edits, hierarchical operations, equivalence judgment, and long-horizon compound editing. Model outputs are evaluated by a deterministic structure-aware oracle. Across six non-thinking LLMs, performance varies substantially with operation-level structural complexity. Simple local edits reach $96\%$--$100\%$ accuracy, while device addition drops to $41\%$--$83\%$ and equivalence judgment to $49\%$--$90\%$. Enabling reasoning substantially improves weaker models but does not eliminate structure-preservation failures, with performance still degrading sharply as the edit horizon increases. NetlistBench identifies netlist reliability as a distinct bottleneck for trustworthy LLM-based circuit design automation.

Figures

Figures reproduced from arXiv: 2608.12197 by the authors.

Figure 1
Figure 1. SPICE netlists as a common representation layer in [PITH_FULL_IMAGE:figures/full_fig_p002_1.png] view at source ↗
Figure 2
Figure 2. NetlistBench pipeline for generating benchmark [PITH_FULL_IMAGE:figures/full_fig_p003_2.png] view at source ↗
Figure 3
Figure 3. Overview of the NetlistBench benchmark, showing the distribution of cases across task families and representative [PITH_FULL_IMAGE:figures/full_fig_p004_3.png] view at source ↗
Figures from the paper (3 more)
Figure 4
Figure 4. Figure 4: Pass rates under compound editing with increasing [PITH_FULL_IMAGE:figures/full_fig_p005_4.png]
Figure 5
Figure 5. Figure 5: Task-level performance under SPICE and PySpice [PITH_FULL_IMAGE:figures/full_fig_p008_5.png]
Figure 6
Figure 6. Figure 6: Task-level performance under non-thinking, think [PITH_FULL_IMAGE:figures/full_fig_p008_6.png]

Discussion (0). Continue with ORCID to comment.

Reference graph

Works this paper leans on

32 extracted references · 12 canonical work pages

  1. [1]

    Jitendra Bhandari, Vineet Bhat, Yuheng He, Siddharth Garg, Hamed Rahmani, and Ramesh Karri. 2024. Masala-CHAI: A Large-Scale SPICE Netlist Dataset for Analog Circuits by Harnessing AI. arXiv:2411.14299 [cs.AR]

    arXiv 2024

  2. [2]

    Jayeeta Chaudhuri, Dhruv Thapar, Arjun Chaudhuri, Farshad Firouzi, and Krish- nendu Chakrabarty. 2024. SPICED: Syntactical Bug and Trojan Pattern Identifica- tion in A/MS Circuits using LLM-Enhanced Detection. arXiv:2408.16018 [cs.AR]

    work page Pith review arXiv 2024

  3. [3]

    Mark Chen, Jerry Tworek, Heewoo Jun, Qiming Yuan, Henrique Ponde de Oliveira Pinto, Jared Kaplan, Harri Edwards, Yuri Burda, Nicholas Joseph, Greg Brockman, et al. 2021. Evaluating Large Language Models Trained on Code.arXiv preprint arXiv:2107.03374(2021)

    arXiv 2021

  4. [4]

    Cordella, Pasquale Foggia, Carlo Sansone, and Mario Vento

    Luigi P. Cordella, Pasquale Foggia, Carlo Sansone, and Mario Vento. 2004. A (Sub)Graph Isomorphism Algorithm for Matching Large Graphs.IEEE Trans- actions on Pattern Analysis and Machine Intelligence26, 10 (2004), 1367–1372. doi:10.1109/TPAMI.2004.75

    doi:10.1109/tpami.2004.75 2004

  5. [5]

    Sharma, Wenbin Xu, Steven M

    Tonmoy Dhar, Kishor Kunal, Yaguang Li, Meghna Madhusudan, Jitesh Poojary, Arvind K. Sharma, Wenbin Xu, Steven M. Burns, Ramesh Harjani, Jiang Hu, Desmond A. Kirkpatrick, Parijat Mukherjee, Soner Yaldiz, and Sachin S. Sapat- nekar. 2021. ALIGN: A System for Automating Analog Layout.IEEE Design & Test38, 2 (2021), 8–18. doi:10.1109/MDAT.2020.3042177

    arXiv 2021

  6. [6]

    Aakash Divakar, Aditya Anekar, and Manas Kulkarni. 2026. Spice Wizard: A Uni- fied AI Agent for Netlist Generation. doi:10.36227/techrxiv.177162431.10627206 Preprint

    work page arXiv 2026

  7. [7]

    Jian Gao, Weidong Cao, Junyi Yang, and Xuan Zhang. 2025. AnalogGenie: A Generative Engine for Automatic Discovery of Analog Circuit Topologies. InThe Thirteenth International Conference on Learning Representations

    work page 2025

  8. [8]

    Helmut Graeb and Markus Leibl. 2023. Learning from the Implicit Functional Hierarchy in an Analog Netlist. InProceedings of the 2023 ACM International Symposium on Physical Design (ISPD). Association for Computing Machinery, 93–100. doi:10.1145/3569052.3578921

    arXiv 2023

Show all 32 references
  1. [9]

    Ruehli, and Pierce A

    Chung-Wen Ho, Albert E. Ruehli, and Pierce A. Brennan. 1975. The Modified Nodal Approach to Network Analysis.IEEE Transactions on Circuits and Systems 22, 6 (1975), 504–509. doi:10.1109/TCS.1975.1084079

    1975

  2. [10]

    Chun-Yen Huang, Hsuan-I Chen, Hao-Wen Ho, Pei-Hsin Kang, Mark Po-Hung Lin, Wen-Hao Liu, and Haoxing Ren. 2025. Netlistify: Transforming Circuit Schematics into Netlists with Deep Learning. InProceedings of the 2025 ACM/IEEE 7th Symposium on Machine Learning for CAD (MLCAD). IE...

    2025

  3. [11]

    Md Touhidul Islam, Sujan Kumar Saha, Farimah Farahmandi, and Mark Tehra- nipoor. 2026. CircuitFormer: A Circuit Language Model for Analog Topology Design from Natural Language Prompt. arXiv:2605.05773 [cs.AR]

    2026 arXiv

  4. [12]

    Jimenez, John Yang, Alexander Wettig, Shunyu Yao, Kexin Pei, Ofir Press, and Karthik Narasimhan

    Carlos E. Jimenez, John Yang, Alexander Wettig, Shunyu Yao, Kexin Pei, Ofir Press, and Karthik Narasimhan. 2024. SWE-bench: Can Language Models Resolve Real- World GitHub Issues?. InInternational Conference on Learning Representations

    2024

  5. [13]

    Sharma, Wenbin Xu, Steven M

    Kishor Kunal, Tonmoy Dhar, Meghna Madhusudan, Jitesh Poojary, Arvind K. Sharma, Wenbin Xu, Steven M. Burns, Jiang Hu, Ramesh Harjani, and Sachin S. Sapatnekar. 2020. GANA: Graph Convolutional Network Based Automated Netlist Annotation for Analog Circuits. InProceedings of the ...

    2020

  6. [14]

    Sharma, Wenbin Xu, Steven M

    Kishor Kunal, Tonmoy Dhar, Meghna Madhusudan, Jitesh Poojary, Arvind K. Sharma, Wenbin Xu, Steven M. Burns, Jiang Hu, Ramesh Harjani, and Sachin S. Sapatnekar. 2023. GNN-Based Hierarchical Annotation for Analog Circuits.IEEE Transactions on Computer-Aided Design of Integrated ...

    2023

  7. [15]

    Pan, and Ping Luo

    Yao Lai, Sungyoung Lee, Guojin Chen, Souradip Poddar, Mengkang Hu, David Z. Pan, and Ping Luo. 2025. AnalogCoder: Analog Circuit Design via Training-Free Code Generation. InProceedings of the AAAI Conference on Artificial Intelligence, Vol. 39. 379–387. doi:10.1609/aaai.v39i1.32016

    2025 doi

  8. [16]

    Mingjie Liu, Teodor-Dumitru Ene, Robert Kirby, Chris Cheng, Nathaniel Pinckney, Rongjian Liang, Jonah Alben, Himyanshu Anand, Sanmitra Banerjee, Ismet Bayraktaroglu, et al. 2023. ChipNeMo: Domain-Adapted LLMs for Chip Design. arXiv:2311.00176 [cs.CL]

    2023 arXiv

  9. [17]

    Ryoga Matsuo, Stefan Uhlich, Arun Venkitaraman, Andrea Bonetti, Chia-Yu Hsieh, Ali Momeni, Lukas Mauch, Augusto Capone, Eisaku Ohbuchi, and Lorenzo Servadei. 2024. Schemato: An LLM for Netlist-to-Schematic Conversion. arXiv:2411.13899 [cs.LG]

    2024 arXiv

  10. [18]

    Laurence W. Nagel. 1975.SPICE2: A Computer Program to Simulate Semiconductor Circuits. Technical Report UCB/ERL M520. Electronics Research Laboratory, Uni- versity of California, Berkeley. https://www2.eecs.berkeley.edu/Pubs/TechRpts/ 1975/9602.html

    1975

  11. [19]

    Nagel and Donald O

    Laurence W. Nagel and Donald O. Pederson. 1973.SPICE (Simulation Program with Integrated Circuit Emphasis). Technical Report UCB/ERL M382. Electronics Research Laboratory, University of California, Berkeley. https://www2.eecs. berkeley.edu/Pubs/TechRpts/1973/22871.html

    1973

  12. [20]

    Simon Nau, Jan Krummenauer, and André Zimmermann. 2025. Eval- uating LLM-based Workflows for Switched-Mode Power Supply Design. arXiv:2507.10639 [cs.AR]

    2025

  13. [21]

    Jingyu Pan, Guanglei Zhou, Chen-Chia Chang, Isaac Jacobson, Jiang Hu, and Yiran Chen. 2025. A Survey of Research in Large Language Models for Electronic Design Automation.ACM Transactions on Design Automation of Electronic Systems 30, 3, Article 34 (2025), 21 pages. doi:10.114...

    2025 doi

  14. [22]

    Fabrice Salvaire. 2021. PySpice: Simulate Electronic Circuit using Python and the Ngspice/Xyce Simulators. Software. https://pyspice.fabrice-salvaire.fr/ Accessed 2026-07-28

    2021

  15. [23]

    Yichen Shi, Ze Zhang, Hongyang Wang, Zhuofu Tao, Zhongyi Li, Bingyu Chen, Yaxin Wang, Zhiping Yu, Ting-Jung Lin, and Lei He. 2025. AMSbench: A Comprehensive Benchmark for Evaluating MLLM Capabilities in AMS Circuits. arXiv:2505.24138 [cs.LG]

    2025

  16. [24]

    Akshit Sinha, Arvindh Arun, Shashwat Goel, Steffen Staab, and Jonas Geiping

  17. [25]

    Lejla Skelic, Yan Xu, Matthew Cox, Wenjie Lu, Tao Yu, and Ruonan Han. 2025. CIRCUIT: A Benchmark for Circuit Interpretation and Reasoning Capabilities of LLMs. arXiv:2502.07980 [cs.LG]

    2025 arXiv

  18. [26]

    Deepak Vungarala, Sakila Alam, Arnob Ghosh, and Shaahin Angizi. 2024. SPI- CEPilot: Navigating SPICE Code Generation and Simulation with AI Guidance. arXiv:2410.20553 [cs.AR]

    2024 arXiv

  19. [27]

    Heng Wang, Shangbin Feng, Tianxing He, Zhaoxuan Tan, Xiaochuang Han, and Yulia Tsvetkov. 2023. Can Language Models Solve Graph Problems in Natural Language?. InAdvances in Neural Information Processing Systems, Vol. 36. 30840– 30861

    2023

  20. [28]

    Chi, Quoc V

    Jason Wei, Xuezhi Wang, Dale Schuurmans, Maarten Bosma, Brian Ichter, Fei Xia, Ed H. Chi, Quoc V. Le, and Denny Zhou. 2022. Chain-of-Thought Prompting Elicits Reasoning in Large Language Models. InAdvances in Neural Information Processing Systems, Vol. 35. 24824–24837

    2022

  21. [29]

    Pan, and Xiyuan Tang

    Ziming Wei, Zichen Kong, Yuan Wang, David Z. Pan, and Xiyuan Tang. 2025. TopoSizing: An LLM-aided Framework of Topology-based Understanding and Sizing for AMS Circuits. arXiv:2509.14169 [cs.LG]

    2025

  22. [30]

    Edwin B. Wilson. 1927. Probable Inference, the Law of Succession, and Statistical Inference.J. Amer. Statist. Assoc.22, 158 (1927), 209–212. doi:10.1080/01621459. 1927.10502953

    1927

  23. [31]

    Haohang Xu, Chengjie Liu, Qihang Wang, Wenhao Huang, Yongjian Xu, Weiyu Chen, Anlan Peng, Zhijun Li, Bo Li, Lei Qi, Jun Yang, Yuan Du, and Li Du. 2025. Image2Net: Datasets, Benchmark and Hybrid Framework to Convert Analog Circuit Diagrams into Netlists. arXiv:2508.13157 [cs.AR...

    2025

  24. [2025]

    arXiv:2509.09677 [cs.AI]

    The Illusion of Diminishing Returns: Measuring Long Horizon Execution in LLMs. arXiv:2509.09677 [cs.AI]

Pith tools

Reviewed August 16, 2026 · model on record in the stance chip above.