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REVIEW 4 major objections 6 minor 62 references

Considerations on the Design of Transceivers for Ambient Internet of Things

T0 review · 4 major / 6 minor · reviewed 2026-08-16 · deepseek-v4-flash

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Pith's one-line read This paper proposes a crystal-less Ambient IoT receiver whose local oscillator locks to the incoming RF carrier through a carrier-auxiliary IF feedback loop, reaching better than -88 dBm sensitivity in 55 nm CMOS.

desk verdict A plausible crystal-less A-IoT receiver architecture, but the headline -88 dBm sensitivity is a link-budget projection from post-sim data, not a measured result. read the letter →

arxiv 2504.14956 v2 pith:QZBSAFWI submitted 2025-04-21 eess.SY cs.ARcs.SY

Yuxiao Zhao , Zhen Shen , Shiyu Li , Jing Feng , Hao Min This is my paper · ORCID
classification eess.SYcs.ARcs.SY
keywords AmbientInternetofThingscrystal-lessreceiverapproximatelow-IFcarrier-auxiliaryIFfeedbackLOfrequencycalibrationmixer-firstbackscattercommunicationsub-mW
verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

The paper tries to establish that Ambient IoT devices in the semi-passive Type-B and active Type-C classes can receive downlink signals at sensitivities better than $-88$ dBm without any external crystal. The proposed architecture derives the local-oscillator frequency from the incoming RF carrier: a feedback loop locks the receiver's intermediate frequency (IF) to a reference generated by a cheap on-chip low-frequency oscillator, then switches from a wide uncertain-IF mode to a narrow approximate low-IF mode. If true, this matters because removing the crystal removes a major cost, volume, and power obstacle to the trillions-of-nodes, battery-free A-IoT vision. The paper reports a 55 nm CMOS prototype whose front-end has about 12 dB noise figure at the $1.035$ MHz IF, and behavioral simulation of the calibration loop locking in about 12 microseconds.

What carries the argument

The load-bearing mechanism is the carrier-auxiliary IF feedback frequency loop: the RF carrier is down-converted to an IF near $1.035$ MHz, a rotational frequency detector compares that IF against a low-frequency synthesizer reference, and a charge pump adjusts the VCO until the IF locks. The comparison happens at MHz rather than GHz, so the feedback path avoids a high-frequency divider and high-power phase tracking; because there is no frequency conversion inside the IF path, the loop transfer function is first-order, which the paper argues removes loop-stability concerns. The second element is the 'approximate low-IF' receiver itself, which operates in two bandwidth modes: a wide uncertain-IF mode for acquisition and a narrow low-IF mode for sensitivity after lock.

What would settle it

Take the fabricated 55 nm chip, feed it a 900 MHz OOK carrier, and measure the down-converted IF at the VCO control node while the loop is supposed to be locked: if the IF does not settle to $1.035$ MHz within about 12 microseconds and stay within a few tens of kHz across temperature, the crystal-free claim fails. Equivalently, an end-to-end demodulation test at an input power of $-88$ dBm over a $180$ kHz channel that fails to meet the 1-10% BLER target would falsify the sensitivity claim.

Watch

Extended reading notes

Core claim

The central claim is that a 'carrier-auxiliary IF feedback' LO synthesizer can replace the external crystal in a Type-B/C A-IoT receiver. The receiver starts in an uncertain-IF mode with a wide IF bandwidth to tolerate PVT-induced LO drift; once the on-off-keyed (OOK) carrier is present, a rotational frequency detector compares the down-converted IF with a reference derived from a temperature-compensated on-chip oscillator, and a charge pump tunes a ring VCO until the IF locks near $1.035$ MHz. With the loop locked, the receiver enters an approximate low-IF mode with a narrow IF path, and the paper's sensitivity calculation, assuming 15 dB required SNR, 12 dB noise figure, and 6 dB margin over a $180$ kHz channel, gives a sensitivity better than $-88$ dBm. The paper also claims the loop is first-order in the frequency domain, so it has no stability problem, and that the mixer-first 4-path RFFE with a gyrator provides image rejection and out-of-band suppression. Measurement results shown include S11, frequency response, and noise figure; the loop dynamics are demonstrated by behavioral simulation.

Load-bearing premise

The stated sensitivity and crystal-free operation rest on the fabricated calibration loop actually locking and holding the IF at $1.035$ MHz with small residual error, and on the measured front-end noise figure being close to the 12 dB post-simulation value; but the paper validates the loop only through behavioral simulation and reports no measured phase noise, locked-frequency error, or end-to-end bit-error rate.

Editorial extensions

If this is right

  • Type-B and Type-C A-IoT devices can drop the external crystal and still meet or exceed the Type-C sensitivity target, since $-88$ dBm is well below the $-70$ dBm level the paper associates with that class.
  • The two-mode receiver lets a free-running oscillator be used, avoiding the power cost of a PLL while still narrowing the IF bandwidth once locked.
  • The first-order loop with roughly 12 microsecond lock time supports duty-cycled, wake-up-style operation, since the device can re-lock quickly when it wakes.
  • The mixer-first RFFE with gyrator-tuned center frequency provides image rejection and out-of-band suppression, removing the need for a SAW filter.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

  • If the -88 dBm figure survives end-to-end silicon measurement, the same front-end could serve both wake-up reception and data reception in one radio, shrinking the bill of materials for battery-less nodes.
  • A natural testable extension is to apply the same carrier-auxiliary anchoring to other narrowband downlinks that provide a calibration carrier, such as BLE advertising or LoRa, though the paper's scheme is tied to A-IoT's OOK/PRDCH structure.
  • The paper's own proposed digital successors (SAR and counter-based digital FLL) suggest the analog loop's 12 microsecond lock time and power can be traded against digital area; whether that trade improves sensitivity depends on the digital blocks' added noise and current.
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Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Referee Report

4 major / 6 minor

Summary. The paper discusses design considerations for Ambient IoT (A-IoT) transceivers and proposes a crystal-less receiver architecture for Type-B and Type-C devices. The architecture combines an approximate low-IF receiver with a carrier-auxiliary IF feedback LO frequency synthesizer that tracks the RF carrier and eliminates the external crystal. A prototype in 55 nm CMOS is described, and the abstract claims that after locking the LO calibration loop the receiver sensitivity is better than -88 dBm. The report of Section VI includes S11, frequency response, noise figure, and a behavioral simulation of the LO calibration loop, but the manuscript does not present measured end-to-end demodulation, bit-error-rate, sensitivity, phase noise, or locked-loop frequency-error results.

Significance. If fully validated, the proposed architecture could enable low-cost, sub-mW, crystal-less A-IoT receivers with sensitivity near -88 dBm, which would be a useful contribution to the A-IoT ecosystem. The paper also provides a helpful classification of A-IoT device types and a survey of design considerations. However, the central sensitivity and crystal-less-operation claims currently rest on the combination of a link-budget calculation and a behavioral simulation, so the significance is prospective rather than demonstrated. The transparent link-budget equation and the identification of the key loop dynamics are strengths, but the absence of measured silicon results is a major gap.

major comments (4)
  1. [Section VI-C, Eq. (4)] The headline sensitivity claim of better than -88 dBm is a link-budget projection, not a measured result. Equation (4) uses a noise figure of 12 dB that Figure 12 labels 'Post-Simulation', an assumed SNR of 15 dB, and an assumed margin of 6 dB. No measured sensitivity, bit-error-rate, or noise figure is reported anywhere in the manuscript. The abstract and conclusion state the -88 dBm value as a demonstrated outcome, which overstates the evidence. The claim should be rephrased as a simulation-based estimate unless the authors add measured sensitivity data.
  2. [Section VI-B, Fig. 13] The LO calibration loop, which is the key enabling block for crystal-less operation, is validated only with a behavioral-level simulation. The paper does not report any measured locked-loop frequency error, hold range, phase noise, or temperature behavior from the fabricated 55 nm die. Whether the fabricated loop actually locks and maintains the IF at 1.035 MHz with sufficient accuracy is load-bearing for the central claim of crystal-less operation with -88 dBm sensitivity. This missing experimental validation cannot be replaced by a simulation-only figure in a paper that claims experimental verification.
  3. [Section VI-A, Fig. 12] The experimental section is misleadingly labeled 'Measurements and Experimental Results' when the NF curve and frequency response are explicitly marked 'Post-Simulation' and the image rejection ratio is also from simulation. The only silicon evidence is the die photo in Figure 11. Consequently, the conclusion's statement that 'Experimental results validate the proposed architecture' is not supported by the content of Section VI. The paper should either present actual measured results or clearly and consistently frame the results as simulation-based.
  4. [Section IV-A and Reference [53]] The paper states that the proposed architecture is improved based on the Class-AB crystal-less receiver defined in [53], which is the authors' own ISCAS 2025 paper. The manuscript should explicitly delineate the incremental contribution of this work over [53] and disclose the relationship to avoid self-overlap concerns. Without such a statement, readers cannot assess which contributions are new here relative to the prior conference publication.
minor comments (6)
  1. [Figure 1] The data rate entry '1s kbps' appears to be a typo; it should read '1-10s kbps' or similar.
  2. [Section IV-D, Eq. (3)] The IF selection formula is presented without derivation. The relationship between the channel bandwidth, guard band, and the chosen 1035 kHz IF should be spelled out so that the reader can verify the reasoning.
  3. [Section V-B] The Schmitt trigger's programmable threshold is described, but the threshold range and its effect on the frequency detector's accuracy are not quantified. A brief design equation or simulation result would help.
  4. [Section VI-B] The text says the LO calibration loop is evaluated by a 'behavioural-level simulation model' but Figure 13 might be mistaken for a measured waveform. State explicitly in the caption or text that this is a simulation result.
  5. [Acknowledgment] The acknowledgment contains unusual copyright, licensing, and 'initial draft' notices that are not appropriate for a journal submission. These should be removed or replaced with a standard acknowledgment statement.
  6. [References] Reference [53] is listed as an ISCAS 2025 paper; if it is not yet published, the citation should indicate 'to appear' or include a preprint identifier so that the relationship with the present manuscript is transparent.

Circularity Check

0 steps flagged · score 2.0 of 10

No significant circularity: the -88 dBm claim is a standard link-budget estimate from Eq. (4) with assumed SNR/margin and post-sim NF; the only self-citation is architectural lineage and is not load-bearing.

full rationale

The paper's core derivation chain runs from the proposed architecture (Sec. IV) through circuit implementation (Sec. V) to the sensitivity estimate of Sec. VI-C. Eq. (4) is the standard receiver sensitivity equation: P_sens = -174 dBm/Hz + 10log(BW) + SNR_min + NF + Margin. The inputs are BW=180 kHz (from the 3GPP A-IoT channelization), SNR_min=15 dB (an assumed R2D decoding requirement), NF=12 dB (from the post-simulation RFFE curve in Fig. 12), and a 6 dB design margin. The resulting -88 dBm is an arithmetic consequence of these independent inputs; no parameter is fitted to the claimed number, and the equation is not defined in terms of the result. Likewise, the LO calibration loop is validated by a behavioral simulation (Fig. 13) that shows f_IF settling to the preselected 1.035 MHz target; this is a self-consistency check, not a circular prediction. The only self-citation is [53], which supplies the 'Class-AB crystal-less receiver' taxonomy and states that this class reduces high-power RF modules. That citation is used for architectural lineage, but the present paper provides full circuit schematics, design equations, and a chip implementation, so the central claim does not reduce to the self-citation. The abstract's 'better than -88 dBm' phrasing and the conclusion's 'Experimental results validate' overstate the evidence (the sensitivity is estimated, not measured), but that is a verification/correctness gap rather than circularity. No equation reduces to its own input, no fitted input is renamed as a prediction, and no uniqueness theorem is imported from the authors' prior work.

Assumptions & free parameters 5 free parameters · 5 assumptions · 0 invented entities

The central sensitivity claim rests on assumed parameters (NF, SNR, margin) and a behavioral simulation of the loop, not on measured end-to-end performance. No new physical entities are introduced; the named architectures are circuit topologies.

free parameters (5)
  • Receiver noise figure (NF) = 12 dB (post-simulation)
    Used in Eq. (4) to compute -88 dBm sensitivity; obtained from post-layout simulation of RFFE, not from a measured full-receiver NF.
  • Required SNR for R2D decoding = 15 dB
    Eq. (4) uses SNR_min = 15 dB, while the text states 10-15 dB, without a measured BER curve to justify the value.
  • System margin = 6 dB
    Assumed margin in Eq. (4); no source or measurement justifies it.
  • LO frequency drift after temperature compensation = ±500 ppm
    Used to derive IF > 540 kHz in Eq. (2); assumed from MEMS/LC oscillator literature, not measured for the ring VCO in this chip.
  • Target IF frequency = 1035 kHz
    Chosen by hand from Eq. (3) and flicker-noise considerations; a design choice, not derived from measurements.
assumptions (5)
  • domain assumption 3GPP A-IoT physical-layer parameters (180 kHz channel, 15 kHz subcarrier, OOK downlink, FDD band n8) are taken as given.
    Section II and Fig. 1 adopt 3GPP TR 38.769 parameters; the receiver design targets depend on these.
  • domain assumption The received RF carrier is available and can serve as a frequency reference for LO calibration.
    Section IV-B assumes the carrier-auxiliary IF feedback loop locks LO to the received carrier while the reader is transmitting; the paper does not analyze behavior during carrier loss or sleep intervals.
  • domain assumption The frequency calibration loop is first-order with L(s)=1 and unconditionally stable.
    Section IV-B and Fig. 4 model the loop without frequency conversion in the IF path; stability is asserted from the model and behavioral simulation, not measured on silicon.
  • standard math Passive mixer-first receivers can map baseband impedance to RF to form a high-Q RF bandpass filter (mixer transparency).
    Section IV-C invokes standard passive-mixer transparency from [56] to justify the SAW-less image-reject RFFE.
  • standard math The thermal noise floor is -174 dBm/Hz and the channel bandwidth is 180 kHz.
    Used in Eq. (4); standard physical constants, not fitted.

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Cite this review

Pith. "Pith review of Considerations on the Design of Transceivers for Ambient Internet of Things." pith.science (2026). https://pith.science/paper/QZBSAFWI

@misc{pith2026250414956,
  author       = {Pith},
  title        = {Pith review of: Considerations on the Design of Transceivers for Ambient Internet of Things},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/QZBSAFWI}},
  note         = {Machine review of arXiv:2504.14956}
}
abstract

The Ambient IoT (A-IoT) will introduce trillions of connections and enable low-cost battery-less devices. The A-IoT nodes can achieve low cost ($\sim\$ 0.1$ like RFID tag), sub-1mW average power consumption, $\leq 10$ kbps data rates, maintenance-free working for decades, cm-scale size, and support applications like supply chain and smart agriculture. The transceiver challenges in A-IoT focus on sub-mW receivers and crystal-less clock generation. The paper proposes an approximate low-IF receiver and carrier-auxiliary IF feedback LO synthesizer architecture for Type-B/C A-IoT devices, which tracks the RF carrier frequency and eliminates external crystals. The proposed receiver and LO generator are implemented using 55nm CMOS technology. After locking the LO calibration loop, the receiver sensitivity is better than -88 dBm. The proposed receiver architecture will promote zero-power devices for ubiquitous IoT connectivity, bridging digital and physical worlds.

Figures

Figures reproduced from arXiv: 2504.14956 by the authors.

Figure 1
Figure 1. Key RF Performance Parameters of Ambient IoT [PITH_FULL_IMAGE:figures/full_fig_p003_1.png] view at source ↗
Figure 2
Figure 2. Zero-IF Receiver Architecture for A-IoT Type-C Devices [PITH_FULL_IMAGE:figures/full_fig_p004_2.png] view at source ↗
Figure 4
Figure 4. Simplified s-domain Model of LO Frequency Calibration Loop [PITH_FULL_IMAGE:figures/full_fig_p005_4.png] view at source ↗
Figures from the paper (7 more)
Figure 5
Figure 5. Figure 5: 4-path Passive Mixer-First RF Front-end MP1 MP3 MN2 MN3 VDD VDD MP2 MN1 VIN VOUT VY VST [PITH_FULL_IMAGE:figures/full_fig_p006_5.png]
Figure 6
Figure 6. Figure 6: Schmitt Trigger with Programmable Threshold [PITH_FULL_IMAGE:figures/full_fig_p006_6.png]
Figure 7
Figure 7. Figure 7: Rotating Frequency Detector VDD GND UP DN GND VDD M3 M4 M6 M7 M1 M2 M9 M10 M5 M8 VCTRL IUP IDN IREF LPF Bandgap [PITH_FULL_IMAGE:figures/full_fig_p007_7.png]
Figure 8
Figure 8. Figure 8: Source-Switch Charge Pump C. Ultra-low Power Baseband The low-power analog baseband circuit used in this paper is shown in [PITH_FULL_IMAGE:figures/full_fig_p007_8.png]
Figure 11
Figure 11. Figure 11: The Photos of the Designed A-IoT Prototype Receiver Chip [PITH_FULL_IMAGE:figures/full_fig_p008_11.png]
Figure 12
Figure 12. Figure 12: S11, Frequency Response and NF of RFFE PSensitivity = −174dBm/Hz + 10log(BW) + SNRmin + NF + M argin = −174dBm/Hz + 10log(180kHz) + 15dB + 12dB + 6dB < −88dBm (4) VII. DISCUSSION AND FUTURE ARCHITECTURE Based on the above discussion, the current analog loop implementa…
Figure 15
Figure 15. Figure 15: Class-A Receiver with Digital Frequency Locked Loop [PITH_FULL_IMAGE:figures/full_fig_p008_15.png]

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Pith tools

Reviewed August 16, 2026 · model on record in the stance chip above.